CN204465461U - A kind of power control circuit for improving power amplifier switches spectrum - Google Patents
A kind of power control circuit for improving power amplifier switches spectrum Download PDFInfo
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- CN204465461U CN204465461U CN201420700624.XU CN201420700624U CN204465461U CN 204465461 U CN204465461 U CN 204465461U CN 201420700624 U CN201420700624 U CN 201420700624U CN 204465461 U CN204465461 U CN 204465461U
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Abstract
The utility model provides a kind of power control circuit for improving power amplifier switches spectrum, comprises linear voltage-stabilizing circuit and dynamic current source.Linear voltage stabilization module also comprises error amplifier (102), feedback circuit (104) and crosses logical element (105); Wherein, the inverting input of error amplifier (102) connects the extraneous power control signal (Vramp) provided, in-phase input end is connected with feedback circuit (104) one end, and output (103) is connected with the grid crossing logical element (105); The source electrode crossing logical element (105) is connected on power end (Vdd), and drain electrode (106) is connected to the other end of feedback circuit; The other end of feedback circuit (104) is connected with the grid crossing logical element (105).The utility model adopts succinctly, circuit design cleverly, can reduce the rate of change of output voltage, prevent it comparatively fast close to supply voltage, maintains the saturation of leading to element, and significantly improves the switch spectral property of power amplifier.
Description
Technical field
The utility model relates to a kind of power control circuit for improving mobile terminal power amplifier switch spectral property, belongs to radio circuit technical field.
Background technology
Radio-frequency power amplifier (RF PA) is widely used in the Wireless Telecom Equipments such as mobile phone.In the front stage circuits of transmitter, the RF signal power that modulation oscillator circuit produces is very little, need to carry out a series of amplification-buffer stage, interstage amplifier section, final power amplifying stage through radio-frequency power amplifier, after obtaining enough radio-frequency powers, just can be fed on antenna and radiate.In this process, accurate power controls the normal use to guaranteeing Wireless Telecom Equipment is vital.
At present, there is various kinds of mobile communication standard or wireless communication standard on the market, such as GSM, TD-LTE, WCDMA, Wi-Fi etc.Various communication standard all requires that in very large dynamic range, realize accurate power controls.The output characteristic of radio-frequency power amplifier must observe relevant communication standard, such as, covers the requirement of (Burst Mask) when output power must meet burst.In order to meet this requirement, be usually added with a specialized circuitry detection saturation in power control circuit, but its implementation is often too complicated.
Such as in existing a kind of power control circuit, meet above-mentioned requirements by the voltage arranging a current offset power amplifier base stage.This voltage signal is formed by the linear combination of a power control signal and a reference voltage.Although under low power scenarios, the program makes power added efficiency increase, and in high power situation, especially in high power and low supply voltage situation, the phenomenon that switch spectrum worsens easily appears in the program.
Be in the Chinese patent application of CN102354242A in publication No., disclose a kind of power control circuit, can the base voltage of dynamic conditioning power amplifier be carried out according to the requirement of different output power thus reach the object optimizing electric current.This power control circuit comprises an error amplifier, pressurizer and a current detection circuit.Current detection circuit detects the electric current flowing through power amplifier, and produces a detection signal.This signal can be voltage or electric current.In a specific implementation, the electric current flowing through power amplifier can be replicated and reduce by a certain percentage.Electric current after copying through input power control signal further modulation and feed back on error amplifier.Error amplifier produces output voltage to control the base stage at power amplifier thus, thus reaches the object of Dynamic controlling base voltage and then optimization electric current.But the program also exists following defect: when the supply voltage of mobile terminal is too low, still can there is the situation of deterioration in the switch spectral property of power amplifier.
Summary of the invention
For the deficiencies in the prior art, technical problem to be solved in the utility model is to provide a kind of power control circuit for improving mobile terminal power amplifier switch spectral property.
For achieving the above object, the utility model adopts following technical scheme:
For improving a power control circuit for power amplifier switches spectrum, comprising: linear voltage-stabilizing circuit and dynamic current source; Wherein, described linear voltage stabilization module also comprises error amplifier 102, feedback circuit 104 and crosses logical element 105;
Described error amplifier 102 is operational amplifiers, and inverting input connects the extraneous power control signal Vramp provided, and in-phase input end is connected with feedback circuit 104 one end, and output 103 is connected with the grid crossing logical element 105; The source electrode that described mistake leads to element 105 is connected on power end Vdd, and drain electrode 106 is connected to the other end of feedback circuit; The other end of feedback circuit 104 is connected with the grid crossing logical element 105;
Described dynamic current source 201 has three ends, first end 2011 is connected with the output 103 of error amplifier 102, second end 2012 is connected with the in-phase input end of error amplifier 102, and the 3rd end 2013 was connected to drain electrode or the power end Vdd of logical element 105.
Wherein more preferably, when described power control signal Vramp is lower or power end Vdd voltage is larger, described dynamic current source 201 does not work, when described power control signal Vramp raise gradually be greater than set point or power end Vdd voltage be reduced to set point time, namely, when the grid that described mistake leads to element 105 is down to the value of setting, work is carried out in described dynamic current source 201 conducting.
Wherein more preferably, described dynamic current source 201 is made up of a PMOS 202 and a NMOS tube 203; The grid of described PMOS 202 is connected to the output 103 of described error amplifier 102, and drain electrode is connected to the in-phase input end of described error amplifier 102, and source electrode was connected to the drain electrode of logical element 105; The grid of described NMOS tube 203 is connected with source electrode, is connected to the drain electrode that described mistake leads to element 105 further, and drain electrode is connected to the in-phase input end of described error amplifier 102.
Wherein more preferably, described dynamic current source 201 is made up of the first PMOS 202, second PMOS 204 and a NMOS tube 203; The grid of described first PMOS 202 is connected to the output 103 of described error amplifier 102, drain electrode is connected to the in-phase input end of described error amplifier 102, source electrode is connected to grid and the source electrode of described NMOS tube 203, is connected to the drain electrode of described second PMOS 204 further; The drain electrode of described NMOS tube 203 is connected to the in-phase input end of described error amplifier 102; The grid of described PMOS 204 was connected to the grid of logical element 105, and source electrode is connected to the source electrode that described mistake leads to element 105.
Wherein more preferably, one end of dynamic clamp device 301 is connected to power end Vdd; The other end is connected with the output 103 of described error amplifier 102.
Wherein more preferably, when described power control signal Vramp is less, the voltage of the output 103 of described error amplifier 102 is higher, and described dynamic clamp device 301 does not work; When described power control signal Vramp exceedes set point, the voltage of the output 103 of described error amplifier 102 reduces, and described dynamic clamp device 301 has electric current to pass through, and the grid described mistake being led to element 105 charges in case voltage overshoot reduces.
Wherein more preferably, described dynamic clamp device 301 can be in series by one or more PMOS, and wherein the grid of each PMOS is connected to the drain electrode of self, and the source electrode of next PMOS is linked in the drain electrode of a upper PMOS;
The source electrode of first PMOS is connected to power end Vdd, and drain electrode is connected with the source electrode of another PMOS, and the rest may be inferred, and the drain electrode of last PMOS is connected to the output 103 of described error amplifier 102.
Compared with prior art, the utility model adopts succinctly, circuit design cleverly, can reduce the rate of change of output voltage, prevent it comparatively fast close to supply voltage, maintains the saturation of leading to element, and significantly improves the switch spectral property of power amplifier.The utility model is particularly suitable for using in low supply voltage situation.
Accompanying drawing explanation
Fig. 1 is the schematic diagram for implementing linear voltage-stabilizing circuit of the present utility model;
Fig. 2 is in an embodiment of the present utility model, a kind of power control circuit schematic diagram for improving power amplifier switches spectral property;
Fig. 3 is in an embodiment of the present utility model, adopts the power control circuit schematic diagram in the first dynamic current source;
Fig. 4 is in an embodiment of the present utility model, adopts the power control circuit schematic diagram in the second dynamic current source;
Fig. 5 is power control circuit schematic diagram Fig. 2 basis increasing dynamic clamp device;
Fig. 6 is power control circuit schematic diagram Fig. 3 basis increasing dynamic clamp device;
Fig. 7 is power control circuit schematic diagram Fig. 4 basis increasing dynamic clamp device.
Embodiment
Below in conjunction with the drawings and specific embodiments, technology contents of the present utility model is further described.
As shown in Figure 1, comprising error amplifier 102, feedback circuit 104 for implementing linear voltage-stabilizing circuit 101 of the present utility model, crossing logical element 105.Error amplifier 102 is operational amplifiers, and inverting input connects the extraneous power control signal Vramp provided, and in-phase input end is connected with feedback circuit 104 one end, and output 103 is connected with the grid crossing logical element 105; The source electrode crossing logical element 105 is connected on power end Vdd, and drain electrode 106 is connected to the other end of feedback circuit, is also connected to the collector electrode of one or more power amplifier simultaneously, represents in FIG with load.Linear voltage-stabilizing circuit 101 has two outputs: one exports was the drain electrode 106 of leading to element 105, and voltage is Vcc herein; Another exports the output 103 for error amplifier.Due to the negative feedback characteristic of linear voltage-stabilizing circuit 101, cross the voltage vcc at drain electrode 106 place of logical element 105 in response to power control signal Vramp.The output voltage signal Vcc linear response of linear voltage-stabilizing circuit 101, in power control signal Vramp, controls the collector electrode of power amplifier, represents in Fig. 1 ~ 4 with load.Cross logical element 105 normally PMOS, in like manner, PMOS also can adopt NMOS tube to substitute, then does adjustment a little.
As everyone knows, two kinds of operating states are usually had as the PMOS crossing logical element: linear work district and operate in saturation district.When power control signal is less, PMOS is in operate in saturation district.Now, whole linear voltage-stabilizing circuit has larger bandwidth of operation, has very strong voltage stabilizing function.When power control signal increases, PMOS departs from operate in saturation district gradually and enters linear zone.Now the bandwidth of system narrows, and voltage stabilizing function weakens.Which kind of operating state PMOS is in, and can be determined by the relative size of each port voltage of PMOS.Specifically, if
Vsg〈Vsd+|Vtp| (1)
So, PMOS is in saturation region.Otherwise, then in linear zone.Here Vsg is the source voltage of PMOS and the difference of gate voltage, and Vsd is the difference of source voltage and drain voltage.Vtp is the threshold voltage of PMOS.When power control signal is very large, Vsg is far longer than Vsd+|Vtp|, and PMOS is in degree of depth linear zone, and its saturation is just very little, and switch spectral property is very poor.
Due in linear voltage-stabilizing circuit, the saturation crossing logical element 105 for power amplifier switch spectral property very crucial.Its saturation is less, and the switch spectral property of power amplifier is poorer.Therefore, the performance that a dynamic current source and a dynamic clamp device improve switch spectrum under low supply voltage is introduced in the utility model.
Being a kind of power control circuit for improving power amplifier switches spectrum that the utility model provides shown in Fig. 2, comprising: linear voltage-stabilizing circuit 101, dynamic current source 201.Wherein, dynamic current source 201 has three ends, first end 2011 is connected with the output 103 of error amplifier 102, and the second end 2012 is connected with the in-phase input end of error amplifier 102, and the 3rd end 2013 was connected to drain electrode 106 or the power end of logical element 105.The effect in dynamic current source 201 is, when having served as the grid voltage reduction of logical element 105, the drain electrode 106 of crossing logical element 105 has very large electric current and passes through, now voltage vcc can become very large, cause rising to of voltage vcc, concerning whole Circuits System, radio-frequency (RF) switch spectrum now can increase high-frequency noise; When the first end 2011 in dynamic current source 201 records the output 103 voltage instantaneous reduction of error amplifier 102, now dynamic current source 201 conducting, the larger current of the drain electrode 106 of crossing logical element 105 is shunted, can be diminished by the electric current of resistance R1, voltage vcc is reduced, namely instantaneous variation can obtain certain alleviation, thus improves the rate of change of electric current or voltage, reduces high-frequency noise.That is, achieve voltage vcc in close to power end Vdd voltage, reduce the object of its rate of change.
Can there be several embodiment in dynamic current source.See Fig. 3, the first embodiment is made up of a PMOS 202 and a NMOS tube 203.The grid of PMOS 202 is connected to the output 103 of error amplifier 102, and drain electrode is connected to the in-phase input end of error amplifier 102, and source electrode was connected to the drain electrode of logical element 105.The grid of NMOS tube 203 is connected with source electrode, and be connected to the drain electrode of logical element 105 further, its drain electrode is connected to the in-phase input end of error amplifier 102.
When power control signal is less, the grid voltage crossing logical element 105 is higher, and now have less electric current by drain electrode, namely output voltage Vcc is lower, PMOS 202 and NMOS tube not conducting due to gate pmos pole tension higher, have less electric current to pass through; NMOS tube is lower due to voltage, also has less electric current to pass through, and namely dynamic current source 201 has less electric current to pass through, but does not affect the normal work of other circuit.That is, when Vramp is less, dynamic current source not conducting.This circuit does not affect the normal work of other circuit.When Vramp exceedes certain threshold value, the conducting of dynamic current source, starts have electric current to flow through; When in the process that power control signal increases gradually, the grid voltage crossing logical element 105 reduces gradually, and also increased gradually by the electric current of drain electrode, namely output voltage Vcc raises gradually; Served as logical element 105 by when departing from saturation region, its switch spectrum can worsen; Now the grid voltage of PMOS 202 is lower, reaches design load, starts working, and output voltage Vcc is also higher, has larger current by PMOS 202; And the grid voltage of NMOS tube 203 is higher, drain voltage and output voltage Vcc also higher, start working and have larger current by NMOS tube 203.Due to Vcc=Vramp*R1/R2+Vramp*R2/R2, namely output voltage Vcc equals the voltage Vramp*R1/R2 of resistance R1 and the voltage Vramp*R2/R2 sum of resistance R2, when dynamic current source 201 works, due to the shunting action in dynamic current source 201, the electric current flowing through resistance R1 can be less than the electric current flowing through resistance R2, therefore, output voltage Vcc diminishes.Namely dynamic current source 201 can reduce the rate of change of output voltage Vcc, prevents it comparatively fast close to power end Vdd voltage, maintains the saturation of logical element 105, alleviates the switch spectrum deterioration of power amplifier to a certain extent.
See Fig. 4, the second embodiment in dynamic current source is made up of PMOS 202, PMOS 204 and a NMOS tube 203.The grid of PMOS 202 is connected to the output 103 of error amplifier 102, and drain electrode is connected to the in-phase input end of error amplifier 102, and source electrode is connected to grid and the source electrode of NMOS tube 203, is connected to the drain electrode of PMOS 204 further; NMOS tube 203 drain electrode is connected to the in-phase input end of error amplifier 102; The grid of PMOS 204 was connected to the grid of logical element 105, and source electrode was connected to the source electrode of logical element 105, also can be connected to power end.
The second embodiment is on the basis of the first embodiment, add a PMOS 204.When the grid voltage of PMOS 204 is lower, and when power end Vdd voltage is also low, PMOS 204 has larger current and passes through, and PMOS 202 and NMOS tube 203 are also worked simultaneously.The Main Function of PMOS 204 is by power end Vdd voltage step-down, and the larger situation of power control signal Vramp detects, and then triggers PMOS 202 and NMOS tube 203 works.Other the course of work is identical with the first embodiment, does not just specifically illustrate at this.
For optimizing the implementation result of this power control circuit further, the utility model additionally provides a kind of dynamic clamp device, see Fig. 5.One end of dynamic clamp device 301 is connected with power end, and namely one end is power end Vdd voltage; The other end is connected with the output 103 of error amplifier 102.The effect of this dynamic clamp device 301 is: prevented the grid voltage of logical element 105 from becoming too low instantaneously, and alleviated large the brought impact of instantaneous change of power control signal Vramp to a certain extent.
Dynamic clamp device 301 can be made up of one or more PMOS, wherein the grid of each pipe is connected to its drain electrode, multiple PMOS is connected, and the source electrode of first PMOS is connected to power end Vdd voltage, the drain electrode of the PMOS at end is connected to the output 103 of error amplifier 102.See Fig. 6 and Fig. 7, in an embodiment of the present utility model, dynamic clamp device 301 comprises two PMOS: PMOS 3011 and PMOS 3012.The grid of PMOS 3011, PMOS 3012 is connected to self drain electrode, and the source electrode of PMOS 3011 connects power end, and its voltage is power end Vdd voltage; The drain electrode of PMOS 3011 is connected to the source electrode of PMOS 3012; The drain electrode of PMOS 3012 is connected to the output 103 of error amplifier 102.
When power control signal Vramp is less, the voltage of the output 103 of error amplifier 102 is higher, and dynamic clamp device 201 is inoperative, does not affect the function of basic circuit.When power control signal Vramp is larger, the voltage of the output 103 of error amplifier 102 reduces, and makes dynamic clamp device 201 have electric current to pass through, and charges, prevent it from excessively reducing to the grid crossing logical element 105.
Above the power control circuit for improving power amplifier switches spectrum provided by the utility model is described in detail.For one of ordinary skill in the art, to any apparent change that it does under the prerequisite not deviating from the utility model connotation, all by formation to the utility model infringement of patent right, corresponding legal liabilities will be born.
Claims (7)
1., for improving a power control circuit for power amplifier switches spectrum, it is characterized in that comprising: linear voltage-stabilizing circuit and dynamic current source; Described linear voltage stabilization module also comprises error amplifier (102), feedback circuit (104) and crosses logical element (105); Wherein,
The inverting input of described error amplifier (102) connects the extraneous power control signal (Vramp) provided, in-phase input end is connected with feedback circuit (104) one end, and output (103) is connected with the grid crossing logical element (105); The source electrode crossing logical element (105) is connected on power end (Vdd), and drain electrode (106) is connected to the other end of feedback circuit; The other end of feedback circuit (104) is connected with the grid crossing logical element (105);
Described dynamic current source (201) has three ends, first end (2011) is connected with the output (103) of error amplifier 102, second end (2012) is connected with the in-phase input end of error amplifier (102), and the 3rd end (2013) was connected to drain electrode or the power end (Vdd) of logical element (105).
2. power control circuit as claimed in claim 1, is characterized in that:
When described power control signal (Vramp) is lower or power end (Vdd) voltage is larger, described dynamic current source (201) does not work, when described power control signal (Vramp) raise gradually be greater than set point or power end (Vdd) voltage be reduced to set point time, namely, when the grid that described mistake leads to element (105) is down to the value of setting, work is carried out in the conducting of described dynamic current source (201).
3. power control circuit as claimed in claim 2, is characterized in that:
Described dynamic current source (201) is made up of a PMOS (202) and a NMOS tube (203); The grid of described PMOS (202) is connected to the output (103) of described error amplifier (102), drain electrode is connected to the in-phase input end of described error amplifier (102), and source electrode is connected to the drain electrode that described mistake leads to element (105); The grid of described NMOS tube (203) is connected with source electrode, is connected to the drain electrode that described mistake leads to element (105) further, and drain electrode is connected to the in-phase input end of described error amplifier (102).
4. power control circuit as claimed in claim 2, is characterized in that:
Described dynamic current source (201) is made up of the first PMOS (202), the second PMOS (204) and a NMOS tube (203); The grid of described first PMOS (202) is connected to the output (103) of described error amplifier (202), drain electrode is connected to the in-phase input end of described error amplifier (102), source electrode is connected to grid and the source electrode of described NMOS tube (203), is connected to the drain electrode of described second PMOS (204) further; The drain electrode of described NMOS tube (203) is connected to the in-phase input end of described error amplifier (102); The grid of described PMOS (204) was connected to the grid of logical element (105), and source electrode is connected to the source electrode that described mistake leads to element (105).
5. the power control circuit as described in claim 3 or 4, characterized by further comprising dynamic clamp device (301);
One end of described dynamic clamp device (301) is connected to power end (Vdd); The other end is connected with the output (103) of described error amplifier (102).
6. power control circuit as claimed in claim 5, is characterized in that:
When described power control signal (Vramp) is less, the voltage of the output (103) of described error amplifier (102) is higher, and described dynamic clamp device (301) does not work; When described power control signal (Vramp) exceedes set point, the voltage of the output (103) of described error amplifier (102) reduces, described dynamic clamp device (301) has electric current to pass through, and the grid described mistake being led to element (105) charges in case voltage overshoot reduces.
7. power control circuit as claimed in claim 5, is characterized in that:
Described dynamic clamp device (301) is in series by one or more PMOS, and wherein the grid of each PMOS is connected to the drain electrode of self;
The source electrode of first PMOS is connected to power end (Vdd), drain electrode is connected with the source electrode of next PMOS, the rest may be inferred, and the drain electrode of last PMOS is connected to the output (103) of described error amplifier (102).
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420700624.XU CN204465461U (en) | 2014-11-20 | 2014-11-20 | A kind of power control circuit for improving power amplifier switches spectrum |
| EP15860536.0A EP3223109B1 (en) | 2014-11-20 | 2015-11-20 | Power control method, device and communication terminal for improving power amplifier switch spectrum |
| PCT/CN2015/095228 WO2016078620A1 (en) | 2014-11-20 | 2015-11-20 | Power control method, device and communication terminal for improving power amplifier switch spectrum |
| US15/528,409 US10305430B2 (en) | 2014-11-20 | 2015-11-20 | Power control method, device and communication terminal for improving power amplifier switch spectrum |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420700624.XU CN204465461U (en) | 2014-11-20 | 2014-11-20 | A kind of power control circuit for improving power amplifier switches spectrum |
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| CN204465461U true CN204465461U (en) | 2015-07-08 |
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| CN201420700624.XU Active CN204465461U (en) | 2014-11-20 | 2014-11-20 | A kind of power control circuit for improving power amplifier switches spectrum |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617886A (en) * | 2014-11-20 | 2015-05-13 | 北京芯麒电子技术有限公司 | Power control method for improving power amplifier switch spectrum and circuit thereof |
| WO2016078620A1 (en) * | 2014-11-20 | 2016-05-26 | 北京芯麒电子技术有限公司 | Power control method, device and communication terminal for improving power amplifier switch spectrum |
| CN106685370A (en) * | 2016-12-27 | 2017-05-17 | 江苏博普电子科技有限责任公司 | GaN microwave power amplifier protection circuit |
| CN109660216A (en) * | 2018-12-11 | 2019-04-19 | 四川长虹电器股份有限公司 | Circuit occurs for amplifier output signal clamp voltage |
| CN112787675A (en) * | 2019-11-11 | 2021-05-11 | 海能达通信股份有限公司 | Method for improving transmitter performance, storage medium and communication equipment |
| CN113064462A (en) * | 2021-03-01 | 2021-07-02 | 江苏硅国微电子有限公司 | LDO circuit with dynamic power consumption and fast transient response |
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2014
- 2014-11-20 CN CN201420700624.XU patent/CN204465461U/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617886A (en) * | 2014-11-20 | 2015-05-13 | 北京芯麒电子技术有限公司 | Power control method for improving power amplifier switch spectrum and circuit thereof |
| WO2016078620A1 (en) * | 2014-11-20 | 2016-05-26 | 北京芯麒电子技术有限公司 | Power control method, device and communication terminal for improving power amplifier switch spectrum |
| US10305430B2 (en) | 2014-11-20 | 2019-05-28 | Beijing Vanchip Technologies Co., Ltd. | Power control method, device and communication terminal for improving power amplifier switch spectrum |
| CN106685370A (en) * | 2016-12-27 | 2017-05-17 | 江苏博普电子科技有限责任公司 | GaN microwave power amplifier protection circuit |
| CN106685370B (en) * | 2016-12-27 | 2023-10-13 | 江苏博普电子科技有限责任公司 | GaN microwave power amplifier protection circuit |
| CN109660216A (en) * | 2018-12-11 | 2019-04-19 | 四川长虹电器股份有限公司 | Circuit occurs for amplifier output signal clamp voltage |
| CN112787675A (en) * | 2019-11-11 | 2021-05-11 | 海能达通信股份有限公司 | Method for improving transmitter performance, storage medium and communication equipment |
| CN112787675B (en) * | 2019-11-11 | 2022-09-16 | 海能达通信股份有限公司 | Method for improving transmitter performance, storage medium and communication equipment |
| CN113064462A (en) * | 2021-03-01 | 2021-07-02 | 江苏硅国微电子有限公司 | LDO circuit with dynamic power consumption and fast transient response |
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Effective date of registration: 20170527 Address after: 100028, 3 floor, building 12, 302, 302 Sun Palace Road, Beijing, Chaoyang District Patentee after: Beijing Czech Electronics Technology Co., Ltd. Address before: 100176, Daxing District economic and Technological Development Zone, Hongda North Road, No. 1, 8, 4,, 405 Patentee before: BEIJING XINLIN ELECTRONIC TECHNOLOGY CO., LTD. |
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Effective date of registration: 20210220 Address after: 100176 room 801, 8th floor, building 8, courtyard 1, KEGU 4th Street, economic and Technological Development Zone, Daxing District, Beijing Patentee after: Beijing Weijie Chuangxin Precision Measurement Technology Co.,Ltd. Address before: 100028 Room 302, Room 302, 3 / F, building 12, Taiyanggong Middle Road, Chaoyang District, Beijing Patentee before: Beijing Czech Electronics Technology Co.,Ltd. |
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