CN204464266U - 一种小球间距的pop芯片叠层封装结构 - Google Patents

一种小球间距的pop芯片叠层封装结构 Download PDF

Info

Publication number
CN204464266U
CN204464266U CN201520238397.8U CN201520238397U CN204464266U CN 204464266 U CN204464266 U CN 204464266U CN 201520238397 U CN201520238397 U CN 201520238397U CN 204464266 U CN204464266 U CN 204464266U
Authority
CN
China
Prior art keywords
top layer
weld pad
packaging
base plate
potted element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201520238397.8U
Other languages
English (en)
Inventor
张珈铭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sichuan Meng Bao Industrial Co Ltd
Original Assignee
Sichuan Meng Bao Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sichuan Meng Bao Industrial Co Ltd filed Critical Sichuan Meng Bao Industrial Co Ltd
Priority to CN201520238397.8U priority Critical patent/CN204464266U/zh
Application granted granted Critical
Publication of CN204464266U publication Critical patent/CN204464266U/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本实用新型公开了一种小球间距的POP芯片叠层封装结构，它包括顶层封装元件（1）和底层封装元件（2），顶层封装元件（1）包括设置在顶层封装基板（4）上表面的上焊垫（7）、设置在顶层封装基板（4）下表面的下焊垫（8）和导通孔（9）；底层封装元件（2）还包括设置在底层密封件（12）上表面的上焊垫（7）、设置在底层封装基板（13）下表面的下焊垫（8）和导通孔（9）；相连接的上焊垫（7）、下焊垫（8）和导通孔（9）组成工字型结构，顶层封装基板（4）的下焊垫（8）通过顶层焊球（11）与底层封装元件（2）的上焊垫（7）连接，导通孔（9）呈梯形结构。本实用新型具有结构强度大、承压性能好、散热效率高、小球间距等特点。

Description

一种小球间距的POP芯片叠层封装结构
技术领域
本实用新型涉及半导体封装领域，特别是涉及一种小球间距的POP芯片叠层封装结构。
背景技术
PoP(Package on Package)堆叠装配技术的出现更加模糊了一级封装与二级装配之间的界线，在大大提高逻辑运算功能和存储空间的同时，也为终端用户提供了自由选择器件组合的可能，生产成本也得以更有效的控制。对于3G手机PoP无疑是一个值得考虑的优选方案。勿庸置否，随着小型化高密度封装的出现，对高速与高精度装配的要求变得更加关键。相关的组装设备和工艺也更具先进性与高灵活性。元器件堆叠装配（Package on Package）技术必须经受这一新的挑战。
目前的POP叠层封装结构，常常会遇到封装体翘曲、承压性能差、散热效率低、焊球间距大等问题，。
实用新型内容
本实用新型的目的在于克服现有技术的不足，提供一种小球间距的POP芯片叠层封装结构，具有结构强度大、承压性能好、散热效率高、小球间距等特点。
本实用新型的目的是通过以下技术方案来实现的：一种小球间距的POP芯片叠层封装结构，它包括顶层封装元件和底层封装元件，顶层封装元件中从上至下依次包括顶层密封件、一个或多个顶层封装芯片、封装垫片、顶层封装基板和顶层焊球，底层封装元件中从上至下依次包括底层密封件、底层封装芯片、底层封装基板和底层焊球。
顶层封装元件还包括设置在顶层封装基板上表面的上焊垫、设置在顶层封装基板下表面的下焊垫和用于连接上焊垫与下焊垫的导通孔。
底层封装元件还包括设置在底层密封件上表面的上焊垫、设置在底层封装基板下表面的下焊垫和用于连接上焊垫与下焊垫的导通孔。
相连接的上焊垫、下焊垫和导通孔组成工字型结构，顶层封装基板的下焊垫通过顶层焊球与底层封装元件的上焊垫连接，导通孔呈梯形结构。
顶层焊球的球径为0.26 mm，底层焊球的球径为0.25 mm，相邻两个顶层焊球的中心球间距为0.5mm，相邻两个底层焊球的中心球间距为0.283 mm。
所述的顶层封装芯片固定在封装垫片上，并通过连接线与顶层封装基板上表面的上焊垫连接，底层封装芯片通过倒装的方式固定在底层封装基板上。
所述的底层封装芯片设置在底层密封件的梯形锥台型凹槽里。
本实用新型的有益效果是：
1）本实用新型采用组成工字型结构的上焊垫、下焊垫和导通孔，其中，导通孔也设置为梯形结构，有效提升叠层封装体的承压性能，使得较薄的基板也不会影响，多叠层芯片的承压性问题，本实用新型结构强度更大。
2）本实用新型中，底层密封件设置有梯形锥台型凹槽，既保证底层封装元件具有较强的结构性，又扩大了底层封装芯片的散热空间，能够更好地解决叠层封装芯片的散热问题。
3）本实用新型中，焊球球径可设置在0.245mm～0.25mm之间，焊球间的间距可以制作为0.283mm，达到细间距POP封装的目的。
附图说明
图1为本实用新型POP芯片叠层封装结构的结构图；
图中，1-顶层封装元件，2-底层封装元件，3-顶层密封件，4-顶层封装基板，5-顶层封装芯片，6-封装垫片，7-上焊垫，8-下焊垫，9-导通孔，10-焊线，11-顶层焊球，12-底层密封件，13-底层封装基板，14-底层封装芯片，15-底层焊球。
具体实施方式
下面结合附图进一步详细描述本实用新型的技术方案，但本实用新型的保护范围不局限于以下所述。
如图1所示，一种小球间距的POP芯片叠层封装结构，它包括顶层封装元件1和底层封装元件2。
顶层封装元件1中从上至下依次包括顶层密封件3、一个或多个顶层封装芯片5、封装垫片6、顶层封装基板4和顶层焊球11。
顶层封装元件1还包括设置在顶层封装基板4上表面的上焊垫7、设置在顶层封装基板4下表面的下焊垫8和用于连接上焊垫7与下焊垫8的导通孔9。
底层封装元件2中从上至下依次包括底层密封件12、一个或多个底层封装芯片14、底层封装基板13和底层焊球15。
底层封装元件2还包括设置在底层密封件12上表面的上焊垫7、设置在底层封装基板13下表面的下焊垫8和用于连接上焊垫7与下焊垫8的导通孔9。
导通孔9内为铜柱，顶层封装元件1的导通孔9的高度与顶层封装基板4的厚度相同，底层封装元件2的导通孔9的高度与底层密封件12和底层封装基板13的厚度之后相同。
相连接的上焊垫7、下焊垫8和导通孔9组成工字型结构，顶层封装基板4的下焊垫8通过顶层焊球11与底层封装元件2的上焊垫7连接，导通孔9呈梯形结构。有效提升叠层封装体的承压性能，使得较薄的基板也不会影响，多叠层芯片的承压性问题，本实用新型结构强度更大。
顶层焊球11的球径为0.26mm，底层焊球15的球径为0.25mm，相邻两个顶层焊球11的球中心间距为0.5mm，相邻两个底层焊球15的中心球间距为0.283mm。
顶层封装元件1与底层封装元件2之间还设置有0.175mm厚的助焊剂。底层封装元件2的厚度为0.3mm。
所述的顶层封装芯片5固定在封装垫片6上，并通过连接线10与顶层封装基板4上表面的上焊垫7连接，多个顶层封装芯片5均通过正装的方式与顶层封装基板4电连接。底层封装芯片14通过倒装的方式与底层封装基板13电连接。
所述的底层封装芯片14设置在底层密封件12的梯形锥台型凹槽里。既保证底层封装元件具有较强的结构性，又扩大了底层封装芯片的散热空间，能够更好地解决叠层封装芯片的散热问题。

Claims (3)

1.一种小球间距的POP芯片叠层封装结构，其特征在于：它包括顶层封装元件（1）和底层封装元件（2），顶层封装元件（1）中从上至下依次包括顶层密封件（3）、一个或多个顶层封装芯片（5）、封装垫片（6）、顶层封装基板（4）和顶层焊球（11），底层封装元件（2）中从上至下依次包括底层密封件（12）、一个或多个底层封装芯片（14）、底层封装基板（13）和底层焊球（15）；
顶层封装元件（1）还包括设置在顶层封装基板（4）上表面的上焊垫（7）、设置在顶层封装基板（4）下表面的下焊垫（8）和用于连接上焊垫（7）与下焊垫（8）的导通孔（9）；
底层封装元件（2）还包括设置在底层密封件（12）上表面的上焊垫（7）、设置在底层封装基板（13）下表面的下焊垫（8）和用于连接上焊垫（7）与下焊垫（8）的导通孔（9）；
相连接的上焊垫（7）、下焊垫（8）和导通孔（9）组成工字型结构，顶层封装基板（4）的下焊垫（8）通过顶层焊球（11）与底层封装元件（2）的上焊垫（7）连接，导通孔（9）呈梯形结构；
顶层焊球（11）的球径为0.26mm，底层焊球（15）的球径为0.25mm，相邻两个顶层焊球（11）的球中心间距为0.5mm，相邻两个底层焊球（15）的球中心间距为0.283mm。
2.根据权利要求1所述的一种小球间距的POP芯片叠层封装结构，其特征在于：所述的顶层封装芯片（5）固定在封装垫片（6）上，并通过连接线（10）与顶层封装基板（4）上表面的上焊垫（7）连接，底层封装芯片（14）通过倒装的方式固定在底层封装基板（13）上。
3.根据权利要求1所述的一种小球间距的POP芯片叠层封装结构，其特征在于：所述的底层封装芯片（14）设置在底层密封件（12）的梯形锥台型凹槽里。
CN201520238397.8U 2015-04-20 2015-04-20 一种小球间距的pop芯片叠层封装结构 Expired - Fee Related CN204464266U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520238397.8U CN204464266U (zh) 2015-04-20 2015-04-20 一种小球间距的pop芯片叠层封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520238397.8U CN204464266U (zh) 2015-04-20 2015-04-20 一种小球间距的pop芯片叠层封装结构

Publications (1)

Publication Number Publication Date
CN204464266U true CN204464266U (zh) 2015-07-08

Family

ID=53671114

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520238397.8U Expired - Fee Related CN204464266U (zh) 2015-04-20 2015-04-20 一种小球间距的pop芯片叠层封装结构

Country Status (1)

Country Link
CN (1) CN204464266U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115656968A (zh) * 2022-11-04 2023-01-31 扬州扬芯激光技术有限公司 一种高互连高集成化激光雷达芯片封装结构及封装工艺

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115656968A (zh) * 2022-11-04 2023-01-31 扬州扬芯激光技术有限公司 一种高互连高集成化激光雷达芯片封装结构及封装工艺
CN115656968B (zh) * 2022-11-04 2023-12-01 扬州扬芯激光技术有限公司 一种高互连高集成化激光雷达芯片封装结构及封装工艺

Similar Documents

Publication Publication Date Title
CN204464266U (zh) 一种小球间距的pop芯片叠层封装结构
CN204464274U (zh) 一种pop芯片叠层封装结构
CN207602549U (zh) 一种三维芯片堆叠芯片尺寸封装结构
CN201623107U (zh) 印刷线路板芯片倒装散热块外接散热板封装结构
CN211238226U (zh) 功率半导体封装器件
CN201623133U (zh) 印刷线路板芯片倒装矩型锁定孔散热块封装结构
CN201623022U (zh) 印刷线路板芯片倒装外接散热板封装结构
CN201623064U (zh) 内脚露出芯片倒装倒t散热块外接散热器封装结构
CN201751995U (zh) 印刷线路板芯片倒装散热块外接散热器封装结构
CN201623117U (zh) 印刷线路板芯片倒装倒t型散热块全包覆封装结构
CN201751992U (zh) 印刷线路板芯片倒装矩型散热块外接散热器封装结构
CN201751980U (zh) 内脚露出芯片倒装散热块外接散热器封装结构
CN201623136U (zh) 印刷线路板芯片倒装倒t型散热块封装结构
CN201623066U (zh) 印刷线路板芯片倒装散热块外接散热帽封装结构
CN201623089U (zh) 内脚露出芯片倒装矩型散热块封装结构
CN201623149U (zh) 印刷线路板芯片倒装倒t锁孔散热块外接散热器封装结构
CN201681816U (zh) 树脂线路板芯片倒装外接散热器封装结构
CN201623100U (zh) 印刷线路板芯片倒装锁孔散热块外接散热器封装结构
CN201623092U (zh) 内脚露出芯片倒装散热块全包覆封装结构
CN201629319U (zh) 树脂线路板芯片倒装带散热块封装结构
CN201623154U (zh) 印刷线路板芯片正装带矩形散热块封装结构
CN201623065U (zh) 树脂线路板芯片倒装散热块外接散热器封装结构
CN201623110U (zh) 印刷线路板芯片倒装矩型锁孔散热块外接散热器封装结构
CN201623095U (zh) 树脂线路板芯片倒装矩型散热块外接散热器封装结构
CN201751986U (zh) 树脂线路板芯片正装散热块外接散热器封装结构

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150708

Termination date: 20160420

CF01 Termination of patent right due to non-payment of annual fee