CN204462464U - Integrated photonics module - Google Patents

Abstract

The utility model relates to integrated photonics module.Integrated photonics module comprises the Semiconductor substrate being configured to be used as optical bench.Insulation and the alternating layer of conductive material to be deposited on substrate and to be patterned thus to limit electrical connection.Substrate is installed and the opto chip contacted.Substrate is installed driving chip, thus via electrical connection, electric drive electric current has been provided to opto chip.A technique effect of an embodiment of the present utility model is: provide alleviate such as electronic package and photoelectron subassembly should by the integrated photonics module of restriction very closely put together.

Description

Integrated photonics module

Technical field

The utility model relates generally to photoelectron (optoelectronic) assembly and system.

Background technology

Integrated photon (photonic) module generally includes the opto chip of such as laser diode chip and auxiliary micro-optic and/or electronic package.Chip and accessory part are installed together on exposed silicon nude film (die) (it is called as " silicon optical bench (optical bench) " (SiOB)).Usually, assembly is aligned and combines (cement) in position on SiOB, and opto chip is electrically connected to other electronic package by line joint.Alternatively, photoelectron and electronic package can be installed on suitable printed circuit board (PCB) and to be electrically connected by printed circuit traces (trace).

As the example of this class formation, U.S. Patent Application Publication 2011/0049334 describes a kind of optical module, and it is by multiple optical signal transmission fibers in parallel.Described optical module to comprise on the substrate comprising electrode pattern, the electrode pattern being arranged on the multiple optical element on the electrode pattern of substrate and being arranged on substrate and is electrically connected to the electron device of optical element.Optical element and electron device are closely arranged on substrate, and the length of the transmission line between optical element and electron device is minimized.

As another example, United States Patent (USP) 7,496,251 describe the apparatus and method comprising the optical communication device of the optical bench structure of such as silicon optical bench (SiOB) for encapsulation.Described optical bench comprises and is wherein formed with the substrate that electricity turns to path (electrical turning via).Photoelectron (OE) chip and integrated circuit (IC) chip to be installed on optical bench and to make electricity consumption turn to path to be electrically connected.Electricity turns to path not only perpendicular to the direction of substrate surface is extending transverse on the direction of substrate surface, OE chip and IC chip closely can be arranged in the vertical surface of optical bench and make electricity consumption turn to path to be electrically connected.

Utility model content

Usual regulation electronic package and photoelectron subassembly should very closely be put together, to make the length of conductor (and therefore inductance and overall impedance) minimize.

An object of an embodiment of the present utility model is: provide the integrated photonics module alleviating these restrictions.

The embodiment of the present utility model described hereinafter provides the method for novel photonic module and the preparation for them.

Therefore provide a kind of integrated photonics module according to the utility model embodiment, it comprises the Semiconductor substrate being configured to be used as optical bench.Insulation and the alternating layer of conductive material to be deposited on substrate and to be patterned thus to limit electrical connection.Opto chip is installed on substrate, and contacts.Driving chip is installed on substrate, thus via electrical connection, electric drive electric current is provided to opto chip.

In certain embodiments, the alternating layer of insulation and conductive material is patterned thus is limited to the transmission line between driving chip and opto chip, and wherein said transmission line has the characteristic impedance of the input impedance of coupling opto chip.Typically, the characteristic impedance of transmission line is less than 5 Ω.In the embodiment disclosed, the layer of conductive material comprises the first metal layer and the second metal level that are configured to ground plane, described second metal level is separated with the first metal layer by the layer of insulating material, forms at least one feeder line, limit transmission line thus in described second metal level.The ratio of the thickness h of the layer of described insulating material and the width W of at least one feeder line described is typically less than 1/50.

Additionally or alternatively, transmission line comprises difference (differential) transmission line, pair of parallel (parallel) feeder line formed in one of described difference transmission lines layer being included in conductive material.

Further additionally or alternatively, module comprises decoupling capacitor, it to be installed on substrate and to be inserted in the transmission line between driving chip and opto chip.

In the embodiment disclosed, opto chip comprises laser diode, and module comprises and is arranged at least one optical element on substrate, that aim at opto chip.

A technique effect of an embodiment of the present utility model is: provide alleviate such as electronic package and photoelectron subassembly should by the integrated photonics module of restriction very closely put together.

The utility model will be understood more fully together with accompanying drawing to the following detailed description of the utility model embodiment.

Accompanying drawing explanation

Fig. 1 is the schematic sectional view of the integrated photonics module (IPM) according to the utility model embodiment;

Fig. 2 is the schematic top view of the IPM according to the utility model embodiment;

Fig. 3 is the schematic sectional view of the IPM according to the utility model embodiment, it illustrates the parameter for designing the transmission line in IPM and size; And

Fig. 4 is the circuit diagram of the IPM according to the utility model embodiment.

Embodiment

Laser diode general features is low-down input impedance (magnitude at 1 Ω) and usually at high-frequency operation.In order to driving laser diode effectively, line or the trace of therefore wishing laser instrument to be connected to other circuit unit have low-down inductance and low overall impedance.These require the design strict constraint being put on the module comprising laser diode, and usually allocated circuit assembly and laser diode are very closely put together, to make the length of conductor (and therefore inductance and overall impedance) minimize.

Embodiment of the present utility model described here provides active (active) SiOB alleviating these restrictions.With regard to following meaning, SiOB is " active ": it comprises multiple metal conducting layer, and described multiple metallic conduction is deposited upon on the wafer as SiOB.By one or more insulation course (such as oxide (SiO between two parties ₂) layer) separate metal layer, described insulation course is similarly deposited on wafer.The manufacturing technology of standard can be used at deposition on wafer and pattern metal and oxide skin(coating).

Such manufacturing technology can produce very thin insulation course, 1 μm or less magnitude (contrasting with the much thick insulation course in stacked ceramic printed-circuit board).As the result of the small distance between the conductor in very thin insulation course and the metal level that deposits on a silicon substrate, very low-impedance transmission line-be typically less than 5 Ω can be produced on SiOB, and even 1 Ω or less-thus when needed, mates the input impedance of the device of such as laser diode.Active SiOB is simultaneously for two objects thus:

It is provided for accurate, the stable mounting platform of the optical module of the integrated photonics module of such as micro-reflector and lens together with laser diode self; And

It provides the matched well between the electronic package of the module comprising laser diode and drive circuit, low-impedance electrical connection.

Although the embodiment described hereinafter relates generally to, laser diode and accessory part are arranged on SiOB, but the optoelectronic integrated circuit (not only comprise transmitter, and comprise the assembly of such as modulator and receiver) of the Semiconductor substrate of other type and other kind can be used to apply principle of the present utility model similarly.

Thus, embodiments more of the present utility model provide integrated photonics module, and it comprises the Semiconductor substrate being configured to be used as optical bench.Insulation and the alternating layer of conductive material to be deposited on substrate and to be patterned thus to limit electrical connection.The opto chip of such as laser diode is installed on substrate, and contacts.Driving chip is also installed on substrate, thus provides electric drive electric current via electrical connection to opto chip.The alternating layer of insulation and conductive material by advantageously patterning, thus can limit the transmission line between driving chip and opto chip, and described transmission line has the characteristic impedance of the input impedance of mating opto chip.

Fig. 1 is the schematic sectional view of the integrated photonics module (IPM) 20 according to the utility model embodiment.From bottom upwards, IPM 20 comprises the silicon substrate 22 being configured to the SiOB being used as IPM.Such as SiO ₂insulating material 26,30 and the alternating layer of the such as conductive material 24,28 of gold, aluminium or another metal be deposited on the substrate 22.Although Fig. 1 only illustrates two insulation courses and two conductive layers, most zone of interest can be used in the embodiment (not shown) substituted, to realize more complicated circuit design.

As shown in figure subsequently, be used in photoetching known in the field of integrated circuit or other technology carrys out patterned layer 24,26,28 and 30, to limit electrical connection.These connections typically comprise conductor wire, path, connection pad and other required structure.Such as, the metal level 24 of the first patterning can be configured to be used as ground plane, and the metal level 28 of the second patterning comprises conductor wire and pad for photoelectron (OE) element 32 of such as laser diode chip being connected to driver chip 34.

The assembly of IPM 20 is installed on upper metallization layer 28.These assemblies such as can comprise the optoelectronic component 32 of such as laser diode chip and driver chip 34 and passive block 36.These passive blocks can comprise discrete electric assembly and the optical module of such as resistor and capacitor.Although typically via the conductor in the metal level 24 and 28 deposited on SiOB to the electric assembly interconnected in IPM 20, line engage can be used to particularly in IPM and outside power, produce additional electrical connection between sensing and Control Component.The optical module of such as lenticule and micro-reflector is installed on SiOB, accurately aims at laser diode or other OE element.Alternatively, can by additional optical element 38 (such as cover glass cap, it is supported on SiOB by the distance piece 40 of patterning) protection laser diode and other optical module.Additionally or alternatively, the optical module of other kind of such as lens, optical patterning element and/or light filter can be supported in like fashion on SiOB.

With reference now to Fig. 2-4, it schematically shows the IPM 42 of the Rotating fields based on Fig. 1 according to the utility model embodiment.Fig. 2 is the top view of IPM 42, and Fig. 3 is partial cross section figure, and Fig. 4 is circuit diagram.

Laser diode 48 is arranged on the active SiOB 44 in IPM 42.Laser diode 48 is connected to the current source 50 in driver chip 52 by low-impedance difference transmission lines 56, described difference transmission lines 56 current limit loop, decoupling capacitor 54 is inserted in the transmission line of ground connection (returning) side.Transmission line 56 is included in the pair of parallel feeder line 58,60 in the upper metallization layer (layer 28 corresponding in Fig. 1) on SiOB 44, and ground plane 46 is in lower metal layer (layer 24 in Fig. 1).Current loop and ground plane are connected to power pin (VCC) 62 and the ground pin (ground pin) 64 of IPM 42 respectively.

Although illustrate in the drawings feeder line 58 and 60 relatively away from, in the design of reality, feeder line can by closely interval to make inductance minimize.The electrical length of the input line 58 between driver 52 and laser instrument 48 equals the electrical length of the line of return 60 by capacitor.

Make it possible to the input impedance of the impedance of transmission line 56 and laser diode 48 to match to the suitable selection of the design parameter of transmission line as is further described hereinbelow, still allow driver chip 52 and laser diode 48 remotely to place relative to design as known in the art simultaneously, be typically separated until about 8mm (limiting by attenuation effect).This of the design is characterized as decoupling capacitor 54 and reserves more spaces, and provides larger dirigibility in the optical module placing IPM 42 on SiOB 44.

Fig. 3 illustrates parameter and the size of the characteristic impedance for determining the transmission line 56 in IPM 42.Impedance depends on the effective dielectric constant ε of the insulation course 66 between feeder line 58,60 and ground plane 46 _eff, it depends on the characteristic dielectric constant ε of the insulating material of constituting layer 66 then _rand the geometry of feeder line and insulation course.Particularly:

${\mathrm{\ϵ}}_{\mathrm{eff}}=\frac{{\mathrm{\ϵ}}_r+1.0}{2}+\frac{{\mathrm{\ϵ}}_r-1.0}{2}\left[\frac{1}{\sqrt{1+\frac{12h}{W}}}\right]$

Wherein, as shown in Figure 3, h is the thickness of insulation course 66, and W is the width of feeder line 58,60.For SiO ₂, ε _r=10.

For the transmission line (only having single feeder line on ground plane) of strip line type, characteristic impedance is Z ₀, as such in what provided by following formula (wherein, t is the thickness of feeder line):

$Z_0=\frac{120\mathrm{\π}}{2.0\sqrt{2.0}\mathrm{\π}\sqrt{{\mathrm{\ϵ}}_r+1.0}}\ln \{1.0+\frac{4.0h}{W^{\′}}[\frac{4.0h}{W^{\′}}\frac{14.0+\frac{8.0}{{\mathrm{\ϵ}}_{\mathrm{eff}}}}{11.00}+\sqrt{{\left(\frac{14.0+\frac{8.0}{{\mathrm{\ϵ}}_{\mathrm{eff}}}}{11.0}\right)}^2{\left(\frac{4.0h}{W^{\′}}\right)}^2+\frac{1.0+\frac{1.0}{{\mathrm{\ϵ}}_{\mathrm{eff}}}}{2.0}{\mathrm{\π}}^2}\left]\right\}$

In above formula, W '=W+ Δ W ',

$\mathrm{\Δ}{W}^{\′}=\mathrm{\ΔW}\left(\frac{1.0+\frac{1.0}{{\mathrm{\ϵ}}_{\mathrm{eff}}}}{\text{2.0}}\right)$

And

$\mathrm{\ΔW}=\frac{t}{\mathrm{\π}}\ln \left[\frac{4e}{{\left(\frac{t}{h}\right)}^2+{\left(\frac{1}{\mathrm{\π}}\right)}^2{\left(\frac{1}{W/t+1.1}\right)}^2}\right]$

For the difference transmission lines of transmission line 56 such as comprising feeder line 58 and 60, characteristic impedance is provided by following:

$Z_{\mathrm{diff}}={2Z}_0[1-0.48\exp \{-0.96\frac{S}{h}\left\}\right]$

Wherein, as shown in Figure 3, S is the interval between two feeder lines.In order to obtain the Low ESR of a few ohm level, for ε _r=10, the ratio of the thickness h of insulation course 66 and the width W of feeder line 58 and 60 should be less than about 1/50.In order to impedance being decreased to about 1 Ω, value should make h/W ≌ 1/150.When h very little (such as 0.5 μm, as can producing in above-described active SiOB design), utilize the W=75 μm of impedance that can obtain hope.

A kind of method for the preparation of photonic module is also provided according to the utility model embodiment.Described method comprises: provide and be configured to be used as the Semiconductor substrate of optical bench, and at the alternating layer of deposited on substrates insulation and conductive material, and layer described in patterning thus limit is electrically connected.Substrate installs opto chip, and to contact, and on substrate, driving chip is installed, thus via electrical connection, electric drive electric current is provided to opto chip.

In certain embodiments, the alternating layer of deposition insulation and conductive material comprises alternating layer described in patterning thus is limited to the transmission line between driving chip and opto chip, and described transmission line has the characteristic impedance of the input impedance of coupling opto chip.

In certain embodiments, the characteristic impedance of transmission line is less than 5 Ω.

In certain embodiments, alternating layer described in patterning comprises the first metal layer is configured to ground plane, and forms at least one feeder line in the second metal level be separated with the first metal layer at the layer by insulating material, thus limits transmission line.

In certain embodiments, described alternating layer is deposited and is patterned, and makes the ratio of the width W of the thickness h of the layer of described insulating material and at least one feeder line described be less than 1/50.

In certain embodiments, alternating layer described in patterning comprises formation difference transmission lines, the pair of parallel feeder line in one of described difference transmission lines layer being included in conductive material.

In certain embodiments, described method also comprises insertion decoupling capacitor, and described decoupling capacitor is installed on substrate, in the transmission line between driving chip and opto chip.

In certain embodiments, opto chip comprises laser diode.

In certain embodiments, described method is also included at least one optical element that on substrate, installation is aimed at opto chip.

Although the figure more than presented and describe and relate to certain specific IPM design (it has the layout of assembly in certain layer of order and those layers and conductor) for concrete object, but will be apparent based on other design of the utility model principle to those skilled in the art, and be considered within scope of the present utility model.Such as, although illustrate the IPM design comprising two insulation courses and two metal levels formed on a silicon substrate, other embodiment can use only single metal layer (have or do not have insulation course between two parties) or three or more layers.In addition, such design is not limited to silicon substrate, but can alternatively realize in the module of the Semiconductor substrate based on other type.

To understand thus, and quote above-described embodiment as an example, and the utility model is not limited to the content that illustrates particularly hereinbefore and describe.Not equal to scope of the present utility model is included in combination and the sub-portfolio of the various features above described, and those skilled in the art when reading foregoing description by expect and there is no its variation disclosed and amendment in the prior art.

Claims (9)

1. an integrated photonics module, is characterized in that comprising:

Semiconductor substrate, is configured to be used as optical bench;

Insulation and the alternating layer of conductive material, to be deposited on substrate and to be patterned thus to limit electrical connection;

Opto chip, is installed on substrate, and contacts; And

Driving chip, is installed on substrate, thus via electrical connection, electric drive electric current is provided to opto chip.

2. integrated photonics module according to claim 1, it is characterized in that, the alternating layer of insulation and conductive material is patterned thus is limited to the transmission line between driving chip and opto chip, and transmission line has the characteristic impedance of the input impedance of coupling opto chip.

3. integrated photonics module according to claim 2, is characterized in that, the characteristic impedance of transmission line is less than 5 Ω.

4. integrated photonics module according to claim 2, it is characterized in that, the layer of conductive material comprises the first metal layer and the second metal level, the first metal layer is configured to ground plane, second metal level is separated with the first metal layer by the layer of insulating material, in the second metal level, form at least one feeder line, limit transmission line thus.

5. integrated photonics module according to claim 4, is characterized in that, the ratio of the thickness h of the layer of described insulating material and the width W of at least one feeder line described is less than 1/50.

6. integrated photonics module according to claim 2, is characterized in that, transmission line comprises difference transmission lines, the pair of parallel feeder line formed in one of described difference transmission lines layer being included in conductive material.

7. integrated photonics module according to claim 2, characterized by further comprising decoupling capacitor, and described decoupling capacitor is installed on substrate, and is inserted in the transmission line between driving chip and opto chip.

8. integrated photonics module according to claim 1, is characterized in that, opto chip comprises laser diode.

9. integrated photonics module according to claim 1, characterized by further comprising and be arranged at least one optical element on substrate, that aim at opto chip.