CN204376873U - For wireless frequency synthesizer - Google Patents
For wireless frequency synthesizer Download PDFInfo
- Publication number
- CN204376873U CN204376873U CN201520121194.0U CN201520121194U CN204376873U CN 204376873 U CN204376873 U CN 204376873U CN 201520121194 U CN201520121194 U CN 201520121194U CN 204376873 U CN204376873 U CN 204376873U
- Authority
- CN
- China
- Prior art keywords
- frequency
- frequency synthesizer
- monocycle
- direct digital
- phase locking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model discloses for wireless frequency synthesizer, comprise crystal oscillator, monocycle frequency synthesizer of phase locking PLL, Direct Digital Frequency Synthesizers DDS, EP3C25F324C8 chip, bandwidth control circuit and loop filter, described crystal oscillator is connected with Direct Digital Frequency Synthesizers DDS, connection transformer and low pass filter successively between Direct Digital Frequency Synthesizers DDS and monocycle frequency synthesizer of phase locking PLL; Described EP3C25F324C8 chip connects the register on monocycle frequency synthesizer of phase locking PLL and the data input register on Direct Digital Frequency Synthesizers DDS simultaneously; To connect successively between the phase discriminator of described monocycle frequency synthesizer of phase locking PLL and VCO voltage controlled oscillator bandwidth control circuit and loop filter, also cascade amplifier and frequency spectrograph successively on VCO voltage controlled oscillator.The utility model is by above-mentioned principle, and this frequency synthesizer switch speed is fast and output spectrum is spuious few, is convenient to observe.
Description
Technical field
The utility model relates to radio art, particularly, relates to for wireless frequency synthesizer.
Background technology
high-quality local oscillation signal is all needed at present in high performance wideband frequency modulation transmitter and receiver, local oscillation signal needs rapid scanning to analyze accurately to received signal in receivers, carrier synchronization needs large-scale local oscillation signal saltus step, these are had higher requirement to the design of frequency synthesizer, the indexs such as such as resolution, change-over time, tuning range, phase noise.Such as in cognitive radio networks, there is the uninterrupted rapid scanning of access point by frequency spectrum of cognitive function, search out current not by the frequency spectrum cavity-pocket that primary user uses, in conjunction with the cognition to channel communication environment and quality, select best communication channel adaptively.Frequency synthesizer of today exists that frequency error factor speed is slow, the spuious defect such as more of output spectrum.
Utility model content
Technical problem to be solved in the utility model is to provide for wireless frequency synthesizer, and this frequency synthesizer switch speed is fast and output spectrum is spuious few, is convenient to observe.
The technical scheme in the invention for solving the above technical problem is: for wireless frequency synthesizer, comprise crystal oscillator, monocycle frequency synthesizer of phase locking PLL, Direct Digital Frequency Synthesizers DDS, EP3C25F324C8 chip, bandwidth control circuit and loop filter, described crystal oscillator is connected with Direct Digital Frequency Synthesizers DDS, connection transformer and low pass filter successively between Direct Digital Frequency Synthesizers DDS and monocycle frequency synthesizer of phase locking PLL; Described EP3C25F324C8 chip connects the register on monocycle frequency synthesizer of phase locking PLL and the data input register on Direct Digital Frequency Synthesizers DDS simultaneously; To connect successively between the phase discriminator of described monocycle frequency synthesizer of phase locking PLL and VCO voltage controlled oscillator bandwidth control circuit and loop filter, also cascade amplifier and frequency spectrograph successively on VCO voltage controlled oscillator.
Crystal oscillator provides 50MHz clock source as the reference frequency of DDS, the output frequency of DDS after transformer and low pass filter process as the derived reference signal of PLL, eventually pass PLL process, and by exporting after the filtering of loop filter circuit and the loop bandwidth process of bandwidth control circuit, EP3C25F324C8 chip wherein provides the configuration data of DDS and PLL, and this technology can be realized by prior art.This Direct Digital Frequency Synthesizers DDS chip adopts the large scale integrated chip (LSI chip) AD9851 of ADI company of the U.S., and the frequency control word of this chip is at 32, and clock frequency reaches 180MHz, and circuit resolution is high, and frequency error factor speed is fast.Monocycle frequency synthesizer of phase locking PLL chip adopts integrated chip ADF4360-7, and the signal that the filtering Direct Digital Frequency Synthesizers DDS frequency source that additional loop filter is used for continuing on this monocycle frequency synthesizer of phase locking PLL transmits, and then amplify output by monocycle frequency synthesizer of phase locking PLL.PLL also arranges bandwidth control circuit, and because loop bandwidth is wider, then hop frequencies is faster, this place's bandwidth control circuit be designed for control loop bandwidth width, thus realize the quick switching of frequency synthesizer further.Bandwidth control circuit wherein adopts existing conventional bandwidth control circuit to realize.Finally the signal after process is outputted on frequency spectrograph and oscilloscope and show, conveniently can observe the situation of frequency synthesis.The program combines the advantage of Direct Digital Frequency Synthesizers DDS and monocycle frequency synthesizer of phase locking PLL, overcomes its shortcoming, and is optimized, and improves the performance of frequency synthesizer.
Further, described monocycle frequency synthesizer of phase locking PLL inside comprises R frequency divider, Fractional-N frequency device, pre-divider, VCO voltage controlled oscillator, phase discriminator and lock detector, R frequency divider wherein, phase discriminator are connected successively with lock detector, R frequency divider is connected with low pass filter, and lock detector is connected with oscilloscope; Pre-divider wherein connects Fractional-N frequency device, R frequency divider, register and VCO voltage controlled oscillator simultaneously.R in R frequency divider wherein and Fractional-N frequency device is that N is main frequency dividing ratio, and its size as requested reference frequency output is determined with reference to frequency dividing ratio, and the frequency synthesized signal such as exporting 700-800MHz then R is set to 12, N and is set to 750.
Further, described Direct Digital Frequency Synthesizers DDS comprises multiplier, A/D converter, frequency plot control register and data input register, multiplier wherein connects crystal oscillator, A/D converter and frequency plot control register simultaneously, and connection data input register gone back by frequency plot control register.
Further, described frequency plot control register also connects EP3C25F324C8 chip.Realize configuration data.
Further, described crystal oscillator is temperature compensating crystal oscillator.Its frequency of oscillation is stablized, and can compensate because variations in temperature produces drift, performance is more stable.
To sum up, the beneficial effects of the utility model are:
1, adopt the circuit resolution of Direct Digital Frequency Synthesizers DDS high, frequency error factor speed is fast, also coordinate monocycle frequency synthesizer of phase locking PLL to carry out exporting after frequency multiplication is amplified simultaneously, PLL also arranges the signal that loop filter transmits for the filtering Direct Digital Frequency Synthesizers DDS frequency source continued, what arrange bandwidth control circuit is designed for control loop bandwidth width, thus ensures the quick switching of frequency synthesizer from many aspects and to export less frequency spectrum spuious.
2, monocycle frequency synthesizer of phase locking PLL also connects frequency spectrograph and oscilloscope, and also connected amplifier before output signal is transferred to frequency spectrograph, the situation of change of clear view output frequency signal can be facilitated.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present utility model.
Embodiment
Below in conjunction with embodiment and accompanying drawing, to the detailed description further of the utility model do, but execution mode of the present utility model is not limited thereto.
Embodiment 1:
As shown in Figure 1, the utility model comprises crystal oscillator, monocycle frequency synthesizer of phase locking PLL, Direct Digital Frequency Synthesizers DDS, EP3C25F324C8 chip, bandwidth control circuit and loop filter, described crystal oscillator is connected with Direct Digital Frequency Synthesizers DDS, connection transformer and low pass filter successively between Direct Digital Frequency Synthesizers DDS and monocycle frequency synthesizer of phase locking PLL; Described EP3C25F324C8 chip connects the register on monocycle frequency synthesizer of phase locking PLL and the data input register on Direct Digital Frequency Synthesizers DDS simultaneously; To connect successively between the phase discriminator of described monocycle frequency synthesizer of phase locking PLL and VCO voltage controlled oscillator bandwidth control circuit and loop filter, also cascade amplifier and frequency spectrograph successively on VCO voltage controlled oscillator.
Crystal oscillator provides 50MHz clock source as the reference frequency of DDS, the output frequency of DDS after transformer and low pass filter process as the derived reference signal of PLL, eventually pass PLL process, and by exporting after the filtering of loop filter circuit and the loop bandwidth process of bandwidth control circuit, EP3C25F324C8 chip wherein provides the configuration data of DDS and PLL, and this technology can be realized by prior art.This Direct Digital Frequency Synthesizers DDS chip adopts the large scale integrated chip (LSI chip) AD9851 of ADI company of the U.S., and the frequency control word of this chip is at 32, and clock frequency reaches 180MHz, and circuit resolution is high, and frequency error factor speed is fast.Monocycle frequency synthesizer of phase locking PLL chip adopts integrated chip ADF4360-7, and the signal that the filtering Direct Digital Frequency Synthesizers DDS frequency source that additional loop filter is used for continuing on this monocycle frequency synthesizer of phase locking PLL transmits, and then amplify output by monocycle frequency synthesizer of phase locking PLL.PLL also arranges bandwidth control circuit, and because loop bandwidth is wider, then hop frequencies is faster, this place's bandwidth control circuit be designed for control loop bandwidth width, thus realize the quick switching of frequency synthesizer further.Bandwidth control circuit wherein adopts existing conventional bandwidth control circuit to realize.Finally the signal after process is outputted on frequency spectrograph and oscilloscope and show, conveniently can observe the situation of frequency synthesis.The program combines the advantage of Direct Digital Frequency Synthesizers DDS and monocycle frequency synthesizer of phase locking PLL, overcomes its shortcoming, and is optimized, and improves the performance of frequency synthesizer.
Embodiment 2:
The present embodiment is preferably as follows on the basis of embodiment 1: monocycle frequency synthesizer of phase locking PLL inside comprises R frequency divider, Fractional-N frequency device, pre-divider, VCO voltage controlled oscillator, phase discriminator and lock detector, R frequency divider wherein, phase discriminator are connected successively with lock detector, R frequency divider is connected with low pass filter, and lock detector is connected with oscilloscope; Pre-divider wherein connects Fractional-N frequency device, R frequency divider, register and VCO voltage controlled oscillator simultaneously.R in R frequency divider wherein and Fractional-N frequency device is that N is main frequency dividing ratio, and its size as requested reference frequency output is determined with reference to frequency dividing ratio, and the frequency synthesized signal such as exporting 700-800MHz then R is set to 12, N and is set to 750.When EP3C25F324C8 chip sends configuration data information, this information passes to data register, R frequency divider, Fractional-N frequency device and pre-divider is acted on respectively by data register, then this data message to be passed to successively after phase discriminator, broadband control circuit, loop filter and the process of VCO voltage controlled oscillator through amplifier amplifier, be presented on frequency spectrograph.Some signal is directly presented on oscilloscope after qualification detector in addition.
Direct Digital Frequency Synthesizers DDS comprises multiplier, A/D converter, frequency plot control register and data input register, multiplier wherein connects crystal oscillator, A/D converter and frequency plot control register simultaneously, and connection data input register gone back by frequency plot control register.When EP3C25F324C8 chip sends configuration data information, this information exports as frequency source after passing to the conversion of data input register, frequency plot control register, multiplier and A/D converter successively.
In order to realize data configuration, described frequency plot control register also connects EP3C25F324C8 chip.
Described crystal oscillator is temperature compensating crystal oscillator.Its frequency of oscillation is stablized, and can compensate because variations in temperature produces drift, performance is more stable.
As mentioned above, the utility model can be realized preferably.
Claims (5)
1. for wireless frequency synthesizer, it is characterized in that, comprise crystal oscillator, monocycle frequency synthesizer of phase locking PLL, Direct Digital Frequency Synthesizers DDS, EP3C25F324C8 chip, bandwidth control circuit and loop filter, described crystal oscillator is connected with Direct Digital Frequency Synthesizers DDS, connection transformer and low pass filter successively between Direct Digital Frequency Synthesizers DDS and monocycle frequency synthesizer of phase locking PLL; Described EP3C25F324C8 chip connects the register on monocycle frequency synthesizer of phase locking PLL and the data input register on Direct Digital Frequency Synthesizers DDS simultaneously; To connect successively between the phase discriminator of described monocycle frequency synthesizer of phase locking PLL and VCO voltage controlled oscillator bandwidth control circuit and loop filter, also cascade amplifier and frequency spectrograph successively on VCO voltage controlled oscillator.
2. according to claim 1 for wireless frequency synthesizer, it is characterized in that, described monocycle frequency synthesizer of phase locking PLL inside comprises R frequency divider, Fractional-N frequency device, pre-divider, VCO voltage controlled oscillator, phase discriminator and lock detector, R frequency divider wherein, phase discriminator are connected successively with lock detector, R frequency divider is connected with low pass filter, and lock detector is connected with oscilloscope; Pre-divider wherein connects Fractional-N frequency device, R frequency divider, register and VCO voltage controlled oscillator simultaneously.
3. according to claim 1 for wireless frequency synthesizer, it is characterized in that, described Direct Digital Frequency Synthesizers DDS comprises multiplier, A/D converter, frequency plot control register and data input register, multiplier wherein connects crystal oscillator, A/D converter and frequency plot control register simultaneously, and connection data input register gone back by frequency plot control register.
4. according to claim 3ly it is characterized in that for wireless frequency synthesizer, described frequency plot control register also connects EP3C25F324C8 chip.
5. according to claim 1ly it is characterized in that for wireless frequency synthesizer, described crystal oscillator is temperature compensating crystal oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520121194.0U CN204376873U (en) | 2015-03-02 | 2015-03-02 | For wireless frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520121194.0U CN204376873U (en) | 2015-03-02 | 2015-03-02 | For wireless frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204376873U true CN204376873U (en) | 2015-06-03 |
Family
ID=53333049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520121194.0U Active CN204376873U (en) | 2015-03-02 | 2015-03-02 | For wireless frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204376873U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107894718A (en) * | 2017-11-08 | 2018-04-10 | 江西洪都航空工业集团有限责任公司 | A kind of radio signal processing system and method based on phaselocked loop |
| CN109873638A (en) * | 2019-01-11 | 2019-06-11 | 东南大学 | A kind of reference phase shifter and phase-moving method improving phase resolution |
| CN116155275A (en) * | 2023-04-19 | 2023-05-23 | 成都世源频控技术股份有限公司 | Broadband fine stepping phase-locked source with repeatable phase |
-
2015
- 2015-03-02 CN CN201520121194.0U patent/CN204376873U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107894718A (en) * | 2017-11-08 | 2018-04-10 | 江西洪都航空工业集团有限责任公司 | A kind of radio signal processing system and method based on phaselocked loop |
| CN109873638A (en) * | 2019-01-11 | 2019-06-11 | 东南大学 | A kind of reference phase shifter and phase-moving method improving phase resolution |
| CN116155275A (en) * | 2023-04-19 | 2023-05-23 | 成都世源频控技术股份有限公司 | Broadband fine stepping phase-locked source with repeatable phase |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9705511B2 (en) | Ultra low phase noise frequency synthesizer | |
| US7602254B2 (en) | System and method for generating signals with a preselected frequency relationship in two steps | |
| JP5021871B2 (en) | Digital small phase detector | |
| US11057040B2 (en) | Phase-locked loop circuit and clock generator including the same | |
| CN103490777B (en) | low spurious frequency synthesizer | |
| CN104135280B (en) | Harmonic generation and mixing frequency source circuit | |
| KR101274358B1 (en) | Low rate, direct conversion fsk radio-frequency signal receiver | |
| CN103762978A (en) | Broadband low-phase noise frequency synthesizer without frequency divider based on harmonic mixing | |
| US9130736B2 (en) | Transceiver system having phase and frequency detector and method thereof | |
| CN108055035B (en) | Broadband frequency extension device of photoelectric oscillator | |
| JP2019504520A (en) | Ultra-low phase noise frequency synthesizer | |
| CN101136631B (en) | Frequency synthesizer and frequency synthesis method | |
| CN105406864A (en) | Wide-band high-speed frequency hopping frequency synthesizer and working method thereof | |
| CN204376873U (en) | For wireless frequency synthesizer | |
| CN103975531A (en) | Frequency synthesis device and method | |
| CN102237890B (en) | Integrated RF transceiver circuit and method for forming digital clock signals | |
| CN102420608B (en) | ODU frequency source generation method | |
| CN102340308B (en) | Fractional-N frequency synthesizer | |
| CN203219288U (en) | Three-level superheterodyne receiver and local oscillation circuit thereof | |
| CN203457138U (en) | Frequency synthesizer | |
| CN202663383U (en) | S-band coherence multi-frequency signal source | |
| CN203014788U (en) | Interference removal device for signal transmission machine | |
| CN215818135U (en) | Frequency hopping frequency source and communication device | |
| CN110995259B (en) | Frequency synthesizer for handheld ultrashort wave frequency hopping radio station | |
| CN102158239A (en) | Broad-band radio-frequency generation circuit based on VC-TCXO (Voltage Control - Temperature Compensation Crystal Oscillator) array and frequency synthesizing chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |