CN204334481U - A kind of phase shift low noise frequency multiplier - Google Patents
A kind of phase shift low noise frequency multiplier Download PDFInfo
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- CN204334481U CN204334481U CN201420721149.4U CN201420721149U CN204334481U CN 204334481 U CN204334481 U CN 204334481U CN 201420721149 U CN201420721149 U CN 201420721149U CN 204334481 U CN204334481 U CN 204334481U
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Abstract
The utility model discloses a kind of phase shift low noise frequency multiplier, primarily of buffer circuit, the Voltage-Controlled oscillation circuit be connected with buffer circuit, the microwave circuit be connected with Voltage-Controlled oscillation circuit, the control circuit be connected with microwave circuit, the phase-locked loop circuit be connected with control circuit forms, and it is characterized in that: be also provided with Phase Processing circuit at phase-locked loop circuit output; Described Phase Processing circuit is by phase shift chip U1, triode VT6, triode VT7, the resistance R12 that one end is connected with the VCC+ pin of phase shift chip U1, the other end is connected with the IN1 pin of phase shift chip U1, the compositions such as the polar capacitor C13 that negative pole is connected with the IN1 pin of phase shift chip U1 after resistance R11, positive pole is connected with the IN2 pin of phase shift chip U1.The utility model is provided with Phase Processing circuit, and it can make the phase place of frequency multiplier more stable, thus can filter out noise signal thoroughly.
Description
Technical field
The utility model relates to electronic applications, specifically refers to a kind of phase shift low noise frequency multiplier.
Background technology
Frequency multiplier makes output signal frequency equal the circuit of frequency input signal integral multiple.Along with the development of electronic technology, frequency multiplier application is more and more extensive, as master oscillator made to vibrate at lower frequency, to improve frequency stability after transmitter employing frequency multiplier; Frequency modulation equipment frequency multiplier increases frequency shift (FS); In phase keying communication equipment, frequency multiplier is an important composition unit of carrier recovery circuit.But the frequency multiplier used at present makes phase of output signal unstable because producing a large amount of harmonic wave, thus make frequency multiplier noise excessive.Its frequency multiplication number of times is higher, and times audio-frequency noise is larger, and the application of frequency multiplier is restricted, and is being required then cannot use in the equipment that times audio-frequency noise is less by it.
Utility model content
The purpose of this utility model is to overcome the excessive defect of current frequency multiplier noise, provides a kind of phase shift low noise frequency multiplier.
The following technical scheme of the purpose of this utility model realizes: a kind of phase shift low noise frequency multiplier, primarily of buffer circuit, the Voltage-Controlled oscillation circuit be connected with buffer circuit, the microwave circuit be connected with Voltage-Controlled oscillation circuit, the control circuit be connected with microwave circuit, the phase-locked loop circuit be connected with control circuit forms: be also provided with Phase Processing circuit at phase-locked loop circuit output, described Phase Processing circuit is by phase shift chip U1, triode VT6, triode VT7, one end is connected with the VCC+ pin of phase shift chip U1, the resistance R12 that the other end is connected with the IN1 pin of phase shift chip U1, negative pole is connected with the IN1 pin of phase shift chip U1 after resistance R11, the polar capacitor C13 that positive pole is connected with the IN2 pin of phase shift chip U1, positive pole is connected with the NC pin of phase shift chip U1 after resistance R13, the polar capacitor C15 that negative pole is connected with the collector electrode of triode VT6, positive pole is connected with the OUT pin of phase shift chip U1, the polar capacitor C14 of minus earth, one end is connected with the OUT pin of phase shift chip U1, the potentiometer R14 of the signal output of the other end, P pole is connected with the OFF1 pin of phase shift chip U1, the diode D6 that N pole is connected with the base stage of triode VT6, and P pole is connected with the OFF2 pin of phase shift chip U1, the diode D7 that N pole is connected with the emitter of triode VT7 forms, the IN1 pin of described phase shift chip U1 is connected with phase-locked loop circuit, VCC-pin ground connection, OUT pin are connected with the sliding end of potentiometer R14, the emitter of triode VT6 is connected with the base stage of triode VT7, collector electrode another output signal of triode VT7, the negative pole of polar capacitor C13 is connected with phase-locked loop circuit.
Described buffer circuit comprises polar capacitor C1, polar capacitor C2, inductance L 1, inductance L 2; The negative pole of polar capacitor C1 is connected with Voltage-Controlled oscillation circuit after inductance L 2 through inductance L 1, positive pole is connected with Voltage-Controlled oscillation circuit, and the negative pole of polar capacitor C2 is connected with the tie point of inductance L 2 with inductance L 1, positive pole is connected with the positive pole of polar capacitor C1.
Described Voltage-Controlled oscillation circuit is by the chip U that vibrates, positive pole is connected with the VCC pin of vibration chip U after resistance R1 through resistance R2, the polar capacitor C3 of minus earth, positive pole is connected with the VCC pin of vibration chip U, the polar capacitor C5 of minus earth, the polar capacitor C6 that OUT pin is connected, negative pole is connected with microwave circuit of positive pole and vibration chip U, and positive pole is connected with the CONT pin of vibration chip U, the polar capacitor C4 of minus earth forms; The DISCH pin of described vibration chip U is connected with inductance L 2, RESET pin is connected with VCC pin, VCC pin is connected with external power source, GND pin ground connection, TRIG pin are connected with the positive pole of polar capacitor C1, THRES pin is connected with TRIG pin.
Described microwave circuit is by diode D1, and diode D2, diode D3, polar capacitor C7, polar capacitor C8, polar capacitor C9 form; The P pole of diode D2 is connected with the negative pole of polar capacitor C6, N pole is connected with control circuit, the P pole of diode D1 is connected with the positive pole of polar capacitor C5, N pole is connected with the positive pole of polar capacitor C5 after diode D3 and polar capacitor C7 through polar capacitor C8, and the negative pole of polar capacitor C9 is connected with control circuit with the positive pole of polar capacitor C5 simultaneously, positive pole is connected with the tie point of polar capacitor C8 and diode D3 and control circuit simultaneously.
Described control circuit is by triode VT1, triode VT2, the voltage stabilizing didoe D4 that P pole is connected with the negative pole of polar capacitor C9, N pole is connected with the base stage of triode VT1, the resistance R3 that one end is connected with the P pole of voltage stabilizing didoe D4, the other end is connected with the emitter of triode VT1, and the diode D5 that P pole is connected with the collector electrode of triode VT1, N pole is connected with the positive pole of polar capacitor C9 forms; The emitter of described triode VT1 is connected with the base stage of triode VT2, base stage is connected with the N pole of diode D2, the grounded collector of triode VT2, emitter are connected with the positive pole of polar capacitor C9 and phase-locked loop circuit simultaneously, and the P pole of voltage stabilizing didoe D4 is also connected with phase-locked loop circuit.
Described phase-locked loop circuit is by triode VT3, triode VT4, triode VT5, positive pole is connected with the P pole of voltage stabilizing didoe D4, the polar capacitor C10 that negative pole is connected with the base stage of triode VT3, one end is connected with the collector electrode of triode VT3, the resistance R6 that the other end is connected with the collector electrode of triode VT3 after resistance R5 through resistance R4, negative pole is connected with the collector electrode of triode VT4 after resistance R7 through resistance R8, the polar capacitor C11 that positive pole is connected with the emitter of triode VT3, and the polar capacitor C12 that negative pole is connected with its positive pole after resistance R9 through resistance R10 forms, the collector electrode of described triode VT5 is connected with the negative pole of polar capacitor C12, emitter is connected with the emitter of triode VT4, base stage is connected with the negative pole of polar capacitor C11, the base stage of triode VT4 is connected with the positive pole of polar capacitor C12, emitter is connected with the collector electrode of triode VT3, the collector electrode of triode VT3 is connected with the emitter of triode VT2, resistance R4 is connected with the negative pole of polar capacitor C10 with the tie point of resistance R5, the tie point of resistance R10 and resistance R9 and the tie point of resistance R8 and resistance R7, and resistance R6 interconnective with the tie point of resistance R4 while be connected with the IN1 pin of phase shift chip U1, the emitter of triode VT5 is connected with the negative pole of polar capacitor C13.
The utility model compared with prior art, has the following advantages and beneficial effect:
(1) the utility model is provided with Phase Processing circuit, and it can make the phase place of frequency multiplier more stable, thus can filter out noise signal thoroughly.
(2) the utility model noise is low, makes the range of application of frequency multiplier wider.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with specific embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, phase shift low noise frequency multiplier of the present utility model, primarily of buffer circuit, the Voltage-Controlled oscillation circuit be connected with buffer circuit, the microwave circuit be connected with Voltage-Controlled oscillation circuit, the control circuit be connected with microwave circuit, the phase-locked loop circuit be connected with control circuit forms: be also provided with Phase Processing circuit at phase-locked loop circuit output.
Described Phase Processing circuit is by phase shift chip U1, triode VT6, triode VT7, one end is connected with the VCC+ pin of phase shift chip U1, the resistance R12 that the other end is connected with the IN1 pin of phase shift chip U1, negative pole is connected with the IN1 pin of phase shift chip U1 after resistance R11, the polar capacitor C13 that positive pole is connected with the IN2 pin of phase shift chip U1, positive pole is connected with the NC pin of phase shift chip U1 after resistance R13, the polar capacitor C15 that negative pole is connected with the collector electrode of triode VT6, positive pole is connected with the OUT pin of phase shift chip U1, the polar capacitor C14 of minus earth, one end is connected with the OUT pin of phase shift chip U1, the potentiometer R14 of the signal output of the other end, P pole is connected with the OFF1 pin of phase shift chip U1, the diode D6 that N pole is connected with the base stage of triode VT6, and P pole is connected with the OFF2 pin of phase shift chip U1, the diode D7 that N pole is connected with the emitter of triode VT7 forms, the IN1 pin of described phase shift chip U1 is connected with phase-locked loop circuit, VCC-pin ground connection, OUT pin are connected with the sliding end of potentiometer R14, the emitter of triode VT6 is connected with the base stage of triode VT7, collector electrode another output signal of triode VT7, the negative pole of polar capacitor C13 is connected with phase-locked loop circuit.Phase Processing circuit, can make the phase place of frequency multiplier more stable, thus can filter out noise signal thoroughly.In order to ensure implementation result, described phase shift chip U1 is preferably LM741 integrated chip.
Described buffer circuit comprises polar capacitor C1, polar capacitor C2, inductance L 1, inductance L 2; The negative pole of polar capacitor C1 is connected with Voltage-Controlled oscillation circuit after inductance L 2 through inductance L 1, positive pole is connected with Voltage-Controlled oscillation circuit, and the negative pole of polar capacitor C2 is connected with the tie point of inductance L 2 with inductance L 1, positive pole is connected with the positive pole of polar capacitor C1.
Described Voltage-Controlled oscillation circuit is by the chip U that vibrates, positive pole is connected with the VCC pin of vibration chip U after resistance R1 through resistance R2, the polar capacitor C3 of minus earth, positive pole is connected with the VCC pin of vibration chip U, the polar capacitor C5 of minus earth, the polar capacitor C6 that OUT pin is connected, negative pole is connected with microwave circuit of positive pole and vibration chip U, and positive pole is connected with the CONT pin of vibration chip U, the polar capacitor C4 of minus earth forms; The DISCH pin of described vibration chip U is connected with inductance L 2, RESET pin is connected with VCC pin, VCC pin is connected with external power source, GND pin ground connection, TRIG pin are connected with the positive pole of polar capacitor C1, THRES pin is connected with TRIG pin.Vibration chip U is preferably NE555 integrated chip.
Described microwave circuit is by diode D1, and diode D2, diode D3, polar capacitor C7, polar capacitor C8, polar capacitor C9 form; The P pole of diode D2 is connected with the negative pole of polar capacitor C6, N pole is connected with control circuit, the P pole of diode D1 is connected with the positive pole of polar capacitor C5, N pole is connected with the positive pole of polar capacitor C5 after diode D3 and polar capacitor C7 through polar capacitor C8, and the negative pole of polar capacitor C9 is connected with control circuit with the positive pole of polar capacitor C5 simultaneously, positive pole is connected with the tie point of polar capacitor C8 and diode D3 and control circuit simultaneously.
In order to make frequency of oscillation strict be locked in incoming frequency doubly take advantage of in value, be therefore provided with control circuit.Described control circuit is by triode VT1, triode VT2, the voltage stabilizing didoe D4 that P pole is connected with the negative pole of polar capacitor C9, N pole is connected with the base stage of triode VT1, the resistance R3 that one end is connected with the P pole of voltage stabilizing didoe D4, the other end is connected with the emitter of triode VT1, and the diode D5 that P pole is connected with the collector electrode of triode VT1, N pole is connected with the positive pole of polar capacitor C9 forms; The emitter of described triode VT1 is connected with the base stage of triode VT2, base stage is connected with the N pole of diode D2, the grounded collector of triode VT2, emitter are connected with the positive pole of polar capacitor C9 and phase-locked loop circuit simultaneously, and the P pole of voltage stabilizing didoe D4 is also connected with phase-locked loop circuit.
Described phase-locked loop circuit is by triode VT3, triode VT4, triode VT5, positive pole is connected with the P pole of voltage stabilizing didoe D4, the polar capacitor C10 that negative pole is connected with the base stage of triode VT3, one end is connected with the collector electrode of triode VT3, the resistance R6 that the other end is connected with the collector electrode of triode VT3 after resistance R5 through resistance R4, negative pole is connected with the collector electrode of triode VT4 after resistance R7 through resistance R8, the polar capacitor C11 that positive pole is connected with the emitter of triode VT3, and the polar capacitor C12 that negative pole is connected with its positive pole after resistance R9 through resistance R10 forms, the collector electrode of described triode VT5 is connected with the negative pole of polar capacitor C12, emitter is connected with the emitter of triode VT4, base stage is connected with the negative pole of polar capacitor C11, the base stage of triode VT4 is connected with the positive pole of polar capacitor C12, emitter is connected with the collector electrode of triode VT3, the collector electrode of triode VT3 is connected with the emitter of triode VT2, resistance R4 is connected with the negative pole of polar capacitor C10 with the tie point of resistance R5, the tie point of resistance R10 and resistance R9 and the tie point of resistance R8 and resistance R7, and resistance R6 interconnective with the tie point of resistance R4 while be connected with the IN1 pin of phase shift chip U1, the emitter of triode VT5 is connected with the negative pole of polar capacitor C13.
As mentioned above, just well the utility model can be realized.
Claims (6)
1. a phase shift low noise frequency multiplier, primarily of buffer circuit, the Voltage-Controlled oscillation circuit be connected with buffer circuit, the microwave circuit be connected with Voltage-Controlled oscillation circuit, the control circuit be connected with microwave circuit, the phase-locked loop circuit be connected with control circuit forms, and it is characterized in that: be also provided with Phase Processing circuit at phase-locked loop circuit output, described Phase Processing circuit is by phase shift chip U1, triode VT6, triode VT7, one end is connected with the VCC+ pin of phase shift chip U1, the resistance R12 that the other end is connected with the IN1 pin of phase shift chip U1, negative pole is connected with the IN1 pin of phase shift chip U1 after resistance R11, the polar capacitor C13 that positive pole is connected with the IN2 pin of phase shift chip U1, positive pole is connected with the NC pin of phase shift chip U1 after resistance R13, the polar capacitor C15 that negative pole is connected with the collector electrode of triode VT6, positive pole is connected with the OUT pin of phase shift chip U1, the polar capacitor C14 of minus earth, one end is connected with the OUT pin of phase shift chip U1, the potentiometer R14 of the signal output of the other end, P pole is connected with the OFF1 pin of phase shift chip U1, the diode D6 that N pole is connected with the base stage of triode VT6, and P pole is connected with the OFF2 pin of phase shift chip U1, the diode D7 that N pole is connected with the emitter of triode VT7 forms, the IN1 pin of described phase shift chip U1 is connected with phase-locked loop circuit, VCC-pin ground connection, OUT pin are connected with the sliding end of potentiometer R14, the emitter of triode VT6 is connected with the base stage of triode VT7, collector electrode another output signal of triode VT7, the negative pole of polar capacitor C13 is connected with phase-locked loop circuit.
2. a kind of phase shift low noise frequency multiplier according to claim 1, is characterized in that: described buffer circuit comprises polar capacitor C1, polar capacitor C2, inductance L 1, inductance L 2; The negative pole of polar capacitor C1 is connected with Voltage-Controlled oscillation circuit after inductance L 2 through inductance L 1, positive pole is connected with Voltage-Controlled oscillation circuit, and the negative pole of polar capacitor C2 is connected with the tie point of inductance L 2 with inductance L 1, positive pole is connected with the positive pole of polar capacitor C1.
3. a kind of phase shift low noise frequency multiplier according to claim 2, it is characterized in that: described Voltage-Controlled oscillation circuit is by the chip U that vibrates, positive pole is connected with the VCC pin of vibration chip U after resistance R1 through resistance R2, the polar capacitor C3 of minus earth, positive pole is connected with the VCC pin of vibration chip U, the polar capacitor C5 of minus earth, the polar capacitor C6 that OUT pin is connected, negative pole is connected with microwave circuit of positive pole and vibration chip U, and positive pole is connected with the CONT pin of vibration chip U, the polar capacitor C4 of minus earth forms; The DISCH pin of described vibration chip U is connected with inductance L 2, RESET pin is connected with VCC pin, VCC pin is connected with external power source, GND pin ground connection, TRIG pin are connected with the positive pole of polar capacitor C1, THRES pin is connected with TRIG pin.
4. a kind of phase shift low noise frequency multiplier according to claim 3, is characterized in that: described microwave circuit is by diode D1, and diode D2, diode D3, polar capacitor C7, polar capacitor C8, polar capacitor C9 form; The P pole of diode D2 is connected with the negative pole of polar capacitor C6, N pole is connected with control circuit, the P pole of diode D1 is connected with the positive pole of polar capacitor C5, N pole is connected with the positive pole of polar capacitor C5 after diode D3 and polar capacitor C7 through polar capacitor C8, and the negative pole of polar capacitor C9 is connected with control circuit with the positive pole of polar capacitor C5 simultaneously, positive pole is connected with the tie point of polar capacitor C8 and diode D3 and control circuit simultaneously.
5. a kind of phase shift low noise frequency multiplier according to claim 4, it is characterized in that: described control circuit is by triode VT1, triode VT2, the voltage stabilizing didoe D4 that P pole is connected with the negative pole of polar capacitor C9, N pole is connected with the base stage of triode VT1, the resistance R3 that one end is connected with the P pole of voltage stabilizing didoe D4, the other end is connected with the emitter of triode VT1, and the diode D5 that P pole is connected with the collector electrode of triode VT1, N pole is connected with the positive pole of polar capacitor C9 forms; The emitter of described triode VT1 is connected with the base stage of triode VT2, base stage is connected with the N pole of diode D2, the grounded collector of triode VT2, emitter are connected with the positive pole of polar capacitor C9 and phase-locked loop circuit simultaneously, and the P pole of voltage stabilizing didoe D4 is also connected with phase-locked loop circuit.
6. a kind of phase shift low noise frequency multiplier according to claim 5, it is characterized in that: described phase-locked loop circuit is by triode VT3, triode VT4, triode VT5, positive pole is connected with the P pole of voltage stabilizing didoe D4, the polar capacitor C10 that negative pole is connected with the base stage of triode VT3, one end is connected with the collector electrode of triode VT3, the resistance R6 that the other end is connected with the collector electrode of triode VT3 after resistance R5 through resistance R4, negative pole is connected with the collector electrode of triode VT4 after resistance R7 through resistance R8, the polar capacitor C11 that positive pole is connected with the emitter of triode VT3, and the polar capacitor C12 that negative pole is connected with its positive pole after resistance R9 through resistance R10 forms, the collector electrode of described triode VT5 is connected with the negative pole of polar capacitor C12, emitter is connected with the emitter of triode VT4, base stage is connected with the negative pole of polar capacitor C11, the base stage of triode VT4 is connected with the positive pole of polar capacitor C12, emitter is connected with the collector electrode of triode VT3, the collector electrode of triode VT3 is connected with the emitter of triode VT2, resistance R4 is connected with the negative pole of polar capacitor C10 with the tie point of resistance R5, the tie point of resistance R10 and resistance R9 and the tie point of resistance R8 and resistance R7, and resistance R6 interconnective with the tie point of resistance R4 while be connected with the IN1 pin of phase shift chip U1, the emitter of triode VT5 is connected with the negative pole of polar capacitor C13.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420721149.4U CN204334481U (en) | 2014-11-26 | 2014-11-26 | A kind of phase shift low noise frequency multiplier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420721149.4U CN204334481U (en) | 2014-11-26 | 2014-11-26 | A kind of phase shift low noise frequency multiplier |
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| CN204334481U true CN204334481U (en) | 2015-05-13 |
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| CN201420721149.4U Expired - Fee Related CN204334481U (en) | 2014-11-26 | 2014-11-26 | A kind of phase shift low noise frequency multiplier |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104901626A (en) * | 2014-11-26 | 2015-09-09 | 成都冠深科技有限公司 | Phase-shifting low-noise frequency multiplier based on common-source amplifying circuit |
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2014
- 2014-11-26 CN CN201420721149.4U patent/CN204334481U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104901626A (en) * | 2014-11-26 | 2015-09-09 | 成都冠深科技有限公司 | Phase-shifting low-noise frequency multiplier based on common-source amplifying circuit |
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Granted publication date: 20150513 Termination date: 20151126 |