CN204315552U - Chip package structure - Google Patents
Chip package structure Download PDFInfo
- Publication number
- CN204315552U CN204315552U CN201420721229.XU CN201420721229U CN204315552U CN 204315552 U CN204315552 U CN 204315552U CN 201420721229 U CN201420721229 U CN 201420721229U CN 204315552 U CN204315552 U CN 204315552U
- Authority
- CN
- China
- Prior art keywords
- wafer
- package structure
- chip package
- support
- colloid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a kind of chip package structure.Described chip package structure comprises colloid, wafer, support, multiplely improves hole and scolding tin, the coated described wafer of described colloid, described support is connected with described wafer, and described support is located in multiple described hole of improving, described scolding tin connects described wafer and described support, and is coated in described colloid.The chip package structure that the utility model provides has the advantage not easily occurring fractureing, not easily occur dry joint, reduce wafer short circuit incidence and promote encapsulation qualification rate.
Description
Technical field
The utility model relates to technical field of electronic encapsulation, especially, relates to a kind of chip package structure.
Background technology
The mankind have the instinct pursuing high-quality life, and wherein, enjoyment is that the one of high-quality life embodies, but the mankind also pursue low price simultaneously.Electronic product is through the development of decades, and for human lives brings earth-shaking change, the demand of the mankind to electronic product is increasing and quality requirement is also more and more higher.
The core component of electronic product is chip, and chip is then made up of polylith wafer.Wafer package for the laying of wafer, fix, seal, protect wafer and strengthen electric heating property and have vital effect, will useful life and the serviceability of electronic product be affected.
The chip package structure of prior art is with the part encapsulation of colloid by the support of wafer and connecting wafer, is connected, realizes wafer to be connected with extraneous by an other part for support with other element.Described support was both also connected with the external world for wafer for supporting wafers simultaneously, but when cutting bent angle, when producing larger stress to described support, easily occur fractureing, easily there is dry joint when described support welds with described wafer simultaneously, after welding, even may occur the defect of wafer short circuit.
Utility model content
Need bear larger stress and frangibility in order to the chip package structure solving prior art exists, easily occur dry joint and occur the technical problem of wafer short circuit, the utility model provides a kind of meets with stresses more by force, not easily occurs dry joint and reduces the chip package structure of wafer short circuit incidence.
The chip package structure that the utility model provides, comprise colloid, wafer, support and multiplely improve hole, the coated described wafer of described colloid, described support is connected with described wafer, and described support is located in multiple described hole of improving, and is coated in described colloid.
In a kind of preferred embodiment of the chip package structure provided at the utility model, described chip package structure also comprises scolding tin, and described scolding tin connects described wafer and described support.
In a kind of preferred embodiment of the chip package structure provided at the utility model, described is set up in described wafer two opposite side.
In a kind of preferred embodiment of the chip package structure provided at the utility model, multiple described Kong Jun of improvement is coated on described colloid.
In a kind of preferred embodiment of the chip package structure provided at the utility model, described support and described wafer connecting place are located in described hole of improving.
In a kind of preferred embodiment of the chip package structure provided at the utility model, described colloid is epoxy resin or silica gel.
Compared to prior art, the chip package structure that the utility model provides has following beneficial effect:
One, improving multiple the design that support is located in hole by adopting, utilizing the buffering effect improving hole counter stress, effectively reduce the stress to support and wafer when cutting bent angle, avoid occurring fractureing and wearing and tearing, thus promote the qualification rate of encapsulation;
Two, by being located at support and wafer connecting place by improving hole, utilization improves hole and absorbs unnecessary scolding tin, effectively avoids wafer to occur short circuit;
Three, by multiple Kong Jun of improvement is coated in colloid, utilize colloid defencive function to a certain degree, avoid being provided with the corresponding support improving hole and easily fracture.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the utility model embodiment, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings, wherein:
Fig. 1 is the cutaway view of a kind of embodiment of the chip package structure that the utility model provides;
Fig. 2 is the cutaway view of a support of the chip package structure shown in Fig. 1.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only a part of embodiment of the present utility model, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making other embodiments all obtained under creative work prerequisite, all belong to the scope of the utility model protection.
See also Fig. 1 and Fig. 2, wherein, Fig. 1 is the cutaway view of a kind of embodiment of the chip package structure that the utility model provides, and Fig. 2 is the cutaway view of a support of the chip package structure shown in Fig. 1.Described chip package structure 1 comprises colloid 11, wafer 13, two support 151,153, three improves hole 171,173,175 and scolding tin 100.Hole 171,173,175 is improved described in the coated described wafer of described colloid 11 13 and three, described in two, support 151,153 is connected with described wafer 13 respectively, improve hole 171,173,175 described in three and be located at support 151,153 described in two, described scolding tin 100 connects support 151,153 described in described wafer 13 and two.
Described colloid 11 is for realizing encapsulation to described wafer 13.In the present embodiment, described colloid 11 is epoxy resin, in other cases, can also be silica gel.
Support 151,153 described in two is located at two opposite sides of described wafer 13 and coupled respectively, and described in two, a part for support 151,153 is coated on described colloid 11, and remainder extends from described colloid 11 2 opposite side.Namely described in two, one end of support 151,153 connects the positive and negative polarities of described wafer 13 respectively, and is connected with the external world by the other end of the two.
Improve hole 171,173,175 described in three to provide in support described in two 151,153.Improve hole 171,173 described in two and be located at described support 151, wherein, described support 151 and described wafer 13 connecting place are located in described hole 173 of improving, and described hole 173 of improving, for absorbing unnecessary described scolding tin 100 when welding described support 151 and described wafer 13, is avoided occurring wafer short circuit; Described hole 171 of improving is located at the edge near described colloid 11 but still is coated in described colloid 11, and the part of described support 151 outside described colloid 11 is for being subject to external force region, by the described design improving hole 171, be beneficial to the stress reducing and when described support 151 is subject to external force, described chip package structure 1 is produced.Describedly improve the edge that described colloid 11 is located in hole 175, but still be coated in described colloid 11, and the part of described support 153 outside described colloid 11 is for being subject to external force region, by the described design improving hole 175, be beneficial to the stress reducing and when described support 153 is subject to external force, described chip package structure 1 is produced.
The positive and negative polarities of described wafer 13 2 opposite side are located at by described scolding tin 100, be specifically located at support 151,153 described in two respectively with the junction of described wafer 13 2 opposite side.Described scolding tin 100 act as support 151,153 described in firm two respectively with the connection of described wafer 13, be beneficial to simultaneously support 151,153 described in enhancing two respectively with information transmission sensitivity and the success rate of described scolding tin 100.
The beneficial effect of the described chip package structure 1 that the utility model provides:
One, hole 171,175 will be improved described in two be located at the design of support 151,153 described in two by adopting, utilize the buffering effect improving hole 171,175 counter stress described in two, to the stress of support described in two 151,153 and described wafer 13 when bent angle is cut in effective reduction, avoid occurring fractureing and wearing and tearing, and promote the qualification rate of encapsulation;
Two, by described support 151 and described wafer 13 connecting place are located in described hole 173 of improving, utilize described hole 173 of improving to absorb unnecessary described scolding tin 100, effectively avoid described wafer 13 to occur short circuit;
Three, by being all coated on improving hole 171,173,175 described in three in described colloid 11, utilize described colloid 11 defencive function to a certain degree, avoid being provided with to improve described in corresponding three hole 171,173,175 two described in support 151,153 easily fracture;
Four, by being all located at improving hole 171,173 described in two near described colloid 11 edge but the design being coated on described colloid 11, be more conducive to improve hole 171,173 described in two to the reduction of external force generation to described chip package structure 1 stress acting on described two supports 151,153.
The foregoing is only embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every utilize the utility model specification and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical field, be all in like manner included in scope of patent protection of the present utility model.
Claims (6)
1. a chip package structure, is characterized in that: comprise colloid, wafer, support and multiplely improve hole, the coated described wafer of described colloid, described support is connected with described wafer, and described support is located in multiple described hole of improving, and is coated in described colloid.
2. chip package structure according to claim 1, is characterized in that: described chip package structure also comprises scolding tin, and described scolding tin connects described wafer and described support.
3. chip package structure according to claim 1, is characterized in that: described is set up in described wafer two opposite side.
4. chip package structure according to claim 1, is characterized in that: multiple described Kong Jun of improvement is coated on described colloid.
5. chip package structure according to claim 1, is characterized in that: described support and described wafer connecting place are located in described hole of improving.
6. chip package structure according to claim 1, is characterized in that: described colloid is epoxy resin or silica gel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420721229.XU CN204315552U (en) | 2014-11-26 | 2014-11-26 | Chip package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420721229.XU CN204315552U (en) | 2014-11-26 | 2014-11-26 | Chip package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204315552U true CN204315552U (en) | 2015-05-06 |
Family
ID=53137853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420721229.XU Expired - Fee Related CN204315552U (en) | 2014-11-26 | 2014-11-26 | Chip package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204315552U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114944375A (en) * | 2022-05-23 | 2022-08-26 | 山东中清智能科技股份有限公司 | Power device packaging structure and preparation method thereof |
-
2014
- 2014-11-26 CN CN201420721229.XU patent/CN204315552U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114944375A (en) * | 2022-05-23 | 2022-08-26 | 山东中清智能科技股份有限公司 | Power device packaging structure and preparation method thereof |
| CN114944375B (en) * | 2022-05-23 | 2022-10-28 | 山东中清智能科技股份有限公司 | Power device packaging structure and preparation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20171126 |