CN204272112U - Power line carrier, PLC voice compression coding device - Google Patents
Power line carrier, PLC voice compression coding device Download PDFInfo
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- CN204272112U CN204272112U CN201420784325.9U CN201420784325U CN204272112U CN 204272112 U CN204272112 U CN 204272112U CN 201420784325 U CN201420784325 U CN 201420784325U CN 204272112 U CN204272112 U CN 204272112U
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Abstract
The utility model relates to a kind of power line carrier, PLC voice compression coding device, encoding and decoding and the filtering of single pass pulse code modulation is carried out by MC145480 chip, have the feature of pre-sampling filter and reconfigurable filter concurrently, and there is one accurately at the 1.575V reference voltage of sheet, without the need to outer member, realize voice digitization required by pulse code modulated system and frequency band limits and smoothness requirements.Achieve and voice compression algorithm is cured in chip, by hardware handles, faster relative to software speed, and be convenient to real-time process, ensure the real-time of process.And can realize listening to and process of transmitting of voice, the effect of experiment is better simultaneously.
Description
Technical field
The utility model relates to technical field of data processing, in particular to a kind of power line carrier, PLC voice compression coding device.
Background technology
Power line carrier communication is the distinctive communication mode of electric power system, and it is transmission channel with power circuit, has the advantages such as channel reliability is high, small investment instant effect, equipment simple, synchronous with power grid construction.Digitize voice percentage constantly increases in a communications system, at ISDN (integrated service digital network), satellite communication, mobile communication, by employing digitize voice transmission without exception and storage in the system such as microwave radio-relay communication and information superhighway.Traditional analog telephone signal bandwidth is 300 ~ 3400Hz, after adopting digitizing technique, the PCM scheme transmission speed at initial stage is 64kbps, along with the development of speech coding technology, the PCM voice data of a road 64kbps can be compressed to 4.8kbps at present even lower, now advanced dropped to 2.4kbps is even lower.
Speech coding is with the process of as far as possible few digitized representation voice, also will ensure required quality and definition simultaneously, at present, three kinds speech bandwidth dropped to 64kbps as follows time keep the method for voice quality: 1) develop effective waveform encoding method; 2) a kind of voice digitization method of source code is adopted; 3) in conjunction with the hybrid coding of waveform coding and source code.
Waveform coding is that time-domain signal is directly converted to digital code, with reconstructed voice waveform as far as possible for principle carries out data compression, its general principle is sampled according to certain speed to analogue voice signal on a timeline, then by amplitude sample layered quantization, and uses code to represent.The Serial No. that decoding is about to receive returns to original analog signal through decoding and filtering.
Source code is also called parameter coding, and it extracts characteristic parameter to source signal at frequency domain or other orthogonal transform domain, and it is transformed into digital code transmits, and it focuses on the reproduction of voice itself from the angle of sense of hearing.This coding techniques can realize Low-ratespeech coding.
Hybrid coding is a kind of new voice coding technology proposed in recent years, it integrates the feature of waveform coding and source code, adopt and analyze and synthetic technology, utilize Speech time shape information simultaneously, enhance the naturalness of reconstructed speech, voice quality is significantly improved, reaches the advantage of the high-quality of waveform coding and the low rate of parameter coding, while breakthrough 16kbps obstacle, obtain the acceptable voice quality being low to moderate 2.4kbps.Thus better reflect the genuine property of original waveform.
Speech coding has both direction at present: a direction is the further low rate of speech coding, and what have breakthrough is variable rate speech coding, and this variable rate speech coding and packet network are very adaptive, is a kind of up-and-coming speech coding technology; Another one direction is that voice do not compress, this is because at present transmission bandwidth increases very fast, and transmission cost significantly declines, and the expense paid for speech coding becomes not conform to compared with saved transmission cost lets it pass.But under packet network environment, particularly under IP network environment, its packet loss phenomenon is inevitable, and voice must deal with and could adapt to this network environment, reduces the data volume of transmission, thus saves cost as far as possible.
Utility model content
Technical problem to be solved in the utility model is, how to improve the speed of Speech compression processing, and realizes the reception of voice and the duplexing process of transmission simultaneously, improves definition and the naturalness of voice, more preferably reproduces raw tone.
For this purpose, the utility model proposes a kind of power line carrier, PLC voice compression coding device, comprise: MC145480 chip, wherein, the RO+ pin of described chip is connected to the first end of the first resistance, second end of described first resistance is connected to the first end of the second resistance, the PI pin of described chip is connected to the first end of the second resistance, second end of described second resistance is connected to the first end of the 3rd resistance, the PO-pin of described chip is connected to the first end of described 3rd resistance, second end of described 3rd resistance is connected to the first end of transformer first coil, the PR+ pin of described chip is connected to the second end of described first coil, the VDD pin of described chip is connected to the first voltage source, described first voltage source is connected to ground by the first electric capacity, FSR pin and the FST pin of described chip are connected to the first clock signal, the DR pin of described chip is connected to pulse code modulation speech data input, the BCR pin of described chip, MCLK pin and BCLKT pin are connected to second clock signal, the PDI pin of described chip is connected to described first voltage source, the VAG pin of described chip and TI+ pin are connected to the first end of the second electric capacity, the TI-pin of described chip is connected to the first end of the 4th resistance, the TG pin of described chip is connected to the first end of the 5th resistance, second end of described 5th resistance is connected to the first end of described 4th resistance, second end of described 4th resistance is connected to the first end of the 3rd electric capacity, second end of described 3rd electric capacity is connected to the first end of described first coil, described chip M ū/A pin and VSS pin are connected to the second end of described second electric capacity, second end of described second electric capacity is connected to ground, the DT pin of described chip is connected to pulse code modulation speech data output, the two ends of relay are connected to the two ends of described transformer second coil respectively.
Preferably, the resistance of described first resistance is 10K Ω, and the resistance of described second resistance is 10K Ω, and the resistance of described 3rd resistance is 620 Ω, and the resistance of described 4th resistance is 10K Ω, and the resistance of described 5th resistance is 10K Ω.
Preferably, the capacitance of described first electric capacity is 0.1 μ F, and the capacitance of described second electric capacity is 0.1 μ F, and the capacitance of described 3rd electric capacity is 51 μ F.
Preferably, the frequency of described first clock signal is 8KHz, and the frequency of described second clock signal is 2048Hz.
Preferably, also comprise: clock signal generating circuit, generate described second clock signal by two MC74HC74A chips.
By technique scheme, achieve and voice compression algorithm is cured in chip, by hardware handles, faster relative to software speed, and be convenient to real-time process, ensure the real-time of process.And can realize listening to and process of transmitting of voice, the effect of experiment is better simultaneously.
Accompanying drawing explanation
Can understanding feature and advantage of the present utility model clearly by reference to accompanying drawing, accompanying drawing is schematic and should not be construed as and carry out any restriction to the utility model, in the accompanying drawings:
Fig. 1 shows the structural representation of the power line carrier, PLC voice compression coding device according to the utility model embodiment;
Fig. 2 shows the electrical block diagram of the clocking according to the utility model embodiment.
Drawing reference numeral illustrates:
1-first resistance; 2-second resistance; 3-the 3rd resistance; 4-the 4th resistance; 5-the 5th resistance; 6-first electric capacity; 7-second electric capacity; 8-the 3rd electric capacity; 9-transformer; 10-relay; VCC1-first voltage source; CLK1-first clock signal; CLK2-second clock signal; PCMI-pulse code modulation speech data input; PCMO-pulse code modulation speech data output.
Embodiment
In order to more clearly understand above-mentioned purpose of the present utility model, feature and advantage, below in conjunction with the drawings and specific embodiments, the utility model is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.
Set forth a lot of detail in the following description so that fully understand the utility model; but; the utility model can also adopt other to be different from other modes described here and implement, and therefore, protection range of the present utility model is not by the restriction of following public specific embodiment.
As shown in Figure 1, according to the power line carrier, PLC voice compression coding device of the utility model embodiment, comprise: MC145480 chip, wherein, the RO+ pin of chip is connected to the first end of the first resistance 1, second end of the first resistance 1 is connected to the first end of the second resistance 2, the PI pin of chip is connected to the first end of the second resistance 2, second end of the second resistance 2 is connected to the first end of the 3rd resistance 3, the PO-pin of chip is connected to the first end of the 3rd resistance 3, second end of the 3rd resistance 3 is connected to the first end of transformer 9 first coil, the PR+ pin of chip is connected to the second end of the first coil, the VDD pin of chip is connected to the first voltage source V CC1, first voltage source V CC1 is connected to ground by the first electric capacity 6, the FSR pin of chip and FST pin are connected to the first clock signal clk 1, the DR pin of chip is connected to pulse code modulation speech data input PCMI, the BCR pin of chip, MCLK pin and BCLKT pin are connected to second clock signal CLK2, the PDI pin of chip is connected to the first voltage source V CC1, the VAG pin of chip and TI+ pin are connected to the first end of the second electric capacity 7, the TI-pin of chip is connected to the first end of the 4th resistance 4, the TG pin of chip is connected to the first end of the 5th resistance 5, second end of the 5th resistance 5 is connected to the first end of the 4th resistance 4, second end of the 4th resistance 4 is connected to the first end of the 3rd electric capacity 8, second end of the 3rd electric capacity 8 is connected to the first end of the first coil, chip M ū/A pin and VSS pin are connected to the second end of the second electric capacity 7, second end of the second electric capacity 7 is connected to ground, the DT pin of chip is connected to pulse code modulation speech data output PCMO, the two ends of relay 10 are connected to the two ends of transformer 9 second coil respectively.
By adopting MC145480 chip, pre-sampling filter and reconfigurable filter can be taken into account, and there is one accurately at the 1.575V reference voltage of sheet, without the need to outer member, realize voice digitization required by PCM (pulse code modulation) system and frequency band limits (200 ~ 3400Hz) and smoothness requirements.And MC145480 chip can hold various block pattern, as digital chain interface (IDL) and General Circuit Interface (GCI) timing device etc. in short frame synchronization, long frame synchronization, chip.
By voice compression algorithm is cured in chip, adopts the relative software processing speed of hardware handles faster, be convenient to real-time process.And hardware circuit can complete the process of duplex, and namely realize listening to and process of transmitting of voice, achieved the transmitting-receiving overall process of two-way speech, the effect of experiment is better simultaneously.
Pass through the actual test of done hardware circuit board, the actual effect of compress speech is better, when voice signal has very high speech intelligibility and naturalness in the speed range of 4 ~ 9.6kbps, and substantially can true reappearance original speech, MOS value is higher, and antijamming capability is stronger.
Utilize distortion meter and signal generating source, measured in compress speech to distortion factor result during 4.8kbps, as shown in table 1:
| Frequency (Hz) | 3000 | 2000 | 1000 | 800 | 500 | 300 |
| The distortion factor (%) | 0.8 | 0.9 | 1 | 4 | 5 | 6 |
Table 1
Frequency distortion factor in the scope of 1 ~ 3kHz is less, and in the scope of 0.3 ~ 1kHz, the distortion factor is larger.
Single-chip microcomputer Main Function has been the control to vocoder, thus starts read strobe signal Enable Pin (RDN) or the write strobe signals Enable Pin (WRN) of vocoder, completes the transmission of a frame voice packets.
Preferably, the resistance of the first resistance 1 is 10K Ω, and the resistance of the second resistance 2 is 10K Ω, and the resistance of the 3rd resistance 3 is 620 Ω, and the resistance of the 4th resistance 4 is 10K Ω, and the resistance of the 5th resistance 5 is 10K Ω.
Preferably, the capacitance of the first electric capacity 6 is 0.1 μ F, and the capacitance of the second electric capacity 7 is 0.1 μ F, and the capacitance of the 3rd electric capacity 8 is 51 μ F.
Preferably, the frequency of the first clock signal clk 1 is 8KHz, and the frequency of second clock signal CLK2 is 2048Hz.
As shown in Figure 2, preferably, also comprise: clock signal generating circuit, generate described second clock signal by two MC74HC74A chips.VCC2 wherein can be identical voltage with the VCC1 in Fig. 1, also can be different voltage.
Needed for MC145480 chip, clock is as follows: RX_STRB, TX_STRB, FSK/FSR (frame synchronization sending/receiving) of 8kHz, RX_I_CLK, TX_O_CLK, BCLKT/BCLKR/MCLK of 2048Hz.Produce the circuit of clock needed for these and gating signal as shown in Figure 2.RX-STRB and TX-STRB is respectively receiving terminal data strobe signal and transmitting terminal data strobe signal.Clock needed for whole system all derives from the clock that same crystal oscillator produces, and namely results from same clock source.The signal that in two MC74HC74A chips, the non-end of the chip Q on right side exports inputs to MC145480 chip as second clock signal, BCR pin in MC145480 chip and BCLKT pin are respectively the reception pin of second clock signal and send pin, these two pins can the transfer rate of control impuls coding modulation data, and the long frame synchronization of 64Hz to 4096KHz and short frame synchronization frequency signal can be received respectively, be chosen for 2048Hz in the present embodiment and can realize preferably sound effect, wherein PCMI and PCMO is input and the output of pulse code modulation speech data.
Certainly, in the design of concrete clock generation circuit, also need the peripheral control unit considering to control compress speech chip, the interrupt clock namely needed for single-chip microcomputer work, as 28.8kHz, 19.2kHz, 9.6kHz, 4.8kHz, 3.6kHz, 2.4kHz, 1.2kHz.These clocks realize by frequency multiplication and frequency dividing circuit.
In the utility model, term " first ", " second ", " the 3rd ", " the 4th ", " the 5th " only for describing object, and can not be interpreted as instruction or hint relative importance.Term " multiple " refers to two or more, unless otherwise clear and definite restriction.
The foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, for a person skilled in the art, the utility model can have various modifications and variations.All within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.
Claims (5)
1. a power line carrier, PLC voice compression coding device, is characterized in that, comprising:
MC145480 chip,
Wherein, the RO+ pin of described chip is connected to the first end of the first resistance, and the second end of described first resistance is connected to the first end of the second resistance,
The PI pin of described chip is connected to the first end of the second resistance, and the second end of described second resistance is connected to the first end of the 3rd resistance,
The PO-pin of described chip is connected to the first end of described 3rd resistance, and the second end of described 3rd resistance is connected to the first end of transformer first coil,
The PR+ pin of described chip is connected to the second end of described first coil,
The VDD pin of described chip is connected to the first voltage source, and described first voltage source is connected to ground by the first electric capacity,
FSR pin and the FST pin of described chip are connected to the first clock signal,
The DR pin of described chip is connected to pulse code modulation speech data input,
The BCR pin of described chip, MCLK pin and BCLKT pin are connected to second clock signal,
The PDI non-pinned of described chip is connected to described first voltage source,
The VAG pin of described chip and TI+ pin are connected to the first end of the second electric capacity,
The TI-pin of described chip is connected to the first end of the 4th resistance,
The TG pin of described chip is connected to the first end of the 5th resistance, second end of described 5th resistance is connected to the first end of described 4th resistance, second end of described 4th resistance is connected to the first end of the 3rd electric capacity, and the second end of described 3rd electric capacity is connected to the first end of described first coil
Described chip M ū/A pin and VSS pin are connected to the second end of described second electric capacity, and the second end of described second electric capacity is connected to ground,
The DT pin of described chip is connected to pulse code modulation speech data output,
The two ends of relay are connected to the two ends of described transformer second coil respectively.
2. power line carrier, PLC voice compression coding device according to claim 1, it is characterized in that, the resistance of described first resistance is 10K Ω, the resistance of described second resistance is 10K Ω, the resistance of described 3rd resistance is 620 Ω, the resistance of described 4th resistance is 10K Ω, and the resistance of described 5th resistance is 10K Ω.
3. power line carrier, PLC voice compression coding device according to claim 1, is characterized in that, the capacitance of described first electric capacity is 0.1 μ F, and the capacitance of described second electric capacity is 0.1 μ F, and the capacitance of described 3rd electric capacity is 51 μ F.
4. power line carrier, PLC voice compression coding device according to claim 1, is characterized in that, the frequency of described first clock signal is 8KHz, and the frequency of described second clock signal is 2048Hz.
5. power line carrier, PLC voice compression coding device according to claim 1, is characterized in that, also comprise:
Clock signal generating circuit, generates described second clock signal by two MC74HC74A chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201420784325.9U CN204272112U (en) | 2014-12-11 | 2014-12-11 | Power line carrier, PLC voice compression coding device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420784325.9U CN204272112U (en) | 2014-12-11 | 2014-12-11 | Power line carrier, PLC voice compression coding device |
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| CN204272112U true CN204272112U (en) | 2015-04-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111884659A (en) * | 2020-07-28 | 2020-11-03 | 广州智品网络科技有限公司 | Compression method and device of FST data |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111884659A (en) * | 2020-07-28 | 2020-11-03 | 广州智品网络科技有限公司 | Compression method and device of FST data |
| CN111884659B (en) * | 2020-07-28 | 2021-09-10 | 广州智品网络科技有限公司 | Compression method and device of FST data |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150415 Termination date: 20171211 |