CN204257629U - For the multichip packaging structure of power inverter - Google Patents
For the multichip packaging structure of power inverter Download PDFInfo
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- CN204257629U CN204257629U CN201420363871.5U CN201420363871U CN204257629U CN 204257629 U CN204257629 U CN 204257629U CN 201420363871 U CN201420363871 U CN 201420363871U CN 204257629 U CN204257629 U CN 204257629U
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 54
- 230000002093 peripheral effect Effects 0.000 claims description 24
- 239000011810 insulating material Substances 0.000 claims description 6
- 239000006185 dispersion Substances 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000001514 detection method Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 238000001914 filtration Methods 0.000 description 4
- 238000004146 energy storage Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Inverter Devices (AREA)
Abstract
The utility model discloses a kind of multichip packaging structure that can be applicable to power inverter, comprise the lead frame be made up of first kind pin and Second Type pin, power device die and power diode wafer.In this multichip packaging structure, by the intermediate contact pads that power device die and power diode wafer is directly positioned over large-area first kind pin, and form with it direct electrical connection, obtain good heat dispersion; Further, between each wafer, specific electric connection can be completed in encapsulating structure inside, instead of outside at encapsulating structure, therefore interference free performance strengthens, thus also improves the reliability and stability of system.
Description
Technical field
The utility model relates to electronic technology field, particularly relates to the physical layer encapsulating structure for power inverter.
Background technology
Power inverter, such as DC-DC power converter device or AC-DC power converter, for providing stable voltage source or current source for various electronic system, such as, the battery management of low-voltage equipment (as notebook computer, mobile phone etc.) and the driving etc. of LED load.
Switch type regulator converts high frequency chopping voltage to the direct voltage of input, then high-frequency output voltage is carried out filtering and then converts VD or average anode current to.Specifically, switch type regulator comprises a power device, and described power device is connected with input voltage is alternating and disconnects with powering load.An energy-storage travelling wave tube, in order to store and to release energy.A power diode, has no progeny in order to close at power device, the energy storage of energy-storage travelling wave tube is released into load.An output filter be made up of inductance and electric capacity be connected between input voltage and load, carries out filtering for exporting power device and then provides VD.Controller (such as pulse-width modulator or frequency pulse modulator an etc.) control switch obtains substantially invariable VD or average anode current.
In semiconductor industry, the production of integrated circuit mainly can be divided into three phases: the encapsulation of the design of integrated circuit, the making of integrated circuit and integrated circuit.In the making of integrated circuit, chip by wafer manufacturing, form the step such as integrated circuit and cutting crystal wafer and complete.After the integrated circuit of inside wafer completes, then on wafer, be configured with multiple weld pad, to make finally, cutting formed chip by wafer can outwards be electrically connected on a carrier via these weld pads.Carrier is such as a lead frame or a base plate for packaging.Chip can to engage or the mode of chip bonding is connected on carrier by routing, makes these weld pads of chip can be electrically connected on the contact of carrier, to form a chip-packaging structure.
Take lead frame as the semiconductor package part of chip bearing member, such as quad flat formula semiconductor package part or quad flat non-pin semiconductor package part etc., its production method is all stickyly on a lead frame with slide holder and multiple pin put this semiconductor chip, and be electrically connected contact pad on described chip surface and the multiple pins corresponding with it by many bonding wires, then form semiconductor packaging part with the coated described chip of packing colloid (plastic casing) and bonding wire.
In a kind of implementation, power device, controller and power diode are separately fabricated and are packaged into single chip.Controller, power switch and power diode are three independently discrete devices.This system configuration needs to use very large PCB surface to amass.In addition, because three devices are discrete, for system developer, the difficulty of debugging is increased.
In another kind of implementation, in order to reduce package area, power device and control circuit are integrated in a single chip 202.But such encapsulating structure is very strict and high standard to the requirement of manufacturing process.The manufacturing process of chip is very complicated, and also very high to the designing requirement of chip, cost is corresponding also very high.In addition, in AC-DC power converter, the requirement of withstand voltage of power device and power diode is higher, such as more than 500V, therefore needs larger isolation distance, and area is increased accordingly.Further, multiple power device is integrated on same silicon substrate, makes heat dispersion poor.In order to make the temperature of chip can not be too high, needing to increase area further, reducing the thermal losses of power device.
Summary of the invention
In view of this, the purpose of this utility model is to provide a kind of multichip packaging structure that can be used for power inverter, large to solve area in prior art, the problems such as heat dispersion difference.
According to the multichip packaging structure for power inverter of the utility model one embodiment, comprise, a lead frame, a power device die and a power diode wafer; Wherein,
Described lead frame comprises first kind pin and Second Type pin;
Described first kind pin comprise the intermediate contact pads that is positioned at described lead frame zone line and be connected with described intermediate contact pads and be positioned at the peripheral pin of the outer peripheral areas of described lead frame;
Described Second Type pin is positioned at the outer peripheral areas of described lead frame, mutually isolated between described Second Type pin and described first kind pin;
Described power device die is positioned on the intermediate contact pads of first kind pin described in, and the bottom of described power device die becomes to be electrically connected with corresponding described intermediate contact pads;
Described power diode wafer electrical is connected on the intermediate contact pads of first kind pin described in another, has the electric polarity corresponding with an electrode of described power diode wafer to make described first kind pin;
One power electrode at described power device die top is connected to the electrode corresponding to described power diode wafer by bonding wire.
According to the multichip packaging structure of the utility model one embodiment, also comprise the controller wafer on the intermediate contact pads being positioned at first kind pin described in another; The bottom of described controller wafer is bonded to corresponding described intermediate contact pads by insulating material.
According to the multichip packaging structure of the utility model another embodiment, also comprise be bonded to described power device die by insulating material top on controller wafer.
Preferably, an electrode of described controller wafer is connected to the electrode of a correspondence at described power device die top by a bonding wire.
Preferably, the bottom of described power diode wafer is negative electrode, and top is anode.
Preferably, described power device die is N-type mosfet transistor, and drain electrode is positioned at the bottom of described power device die, and grid and source electrode are positioned at the top of described power device die.
Preferably, described power diode wafer is just being loaded on the intermediate contact pads of described first kind pin.
Preferably, described power diode flip-chip is on the intermediate contact pads of described first kind pin.
Preferably, the described power electrode at described power device die top is connected to the intermediate contact pads of the described first kind pin that described power diode wafer is positioned at by bonding wire.
Preferably, the described power electrode at described power device die top is connected to the electrode of a correspondence at described power diode wafer top by bonding wire.
Preferably, the electrode of described power device die, described power diode wafer and described controller wafer is connected to corresponding Second Type pin by bonding wire.
Preferably, also comprise plastic packaging shell, with by described lead frame, described power device die, described power diode wafer and described controller wafer carry out plastic packaging, and make described peripheral pin and described Second Type pin portions exposed.
The just multiple wafer package of multichip packaging structure of foundation the utility model embodiment, in an encapsulating structure, improves the heat dispersion of power device and power diode by the intermediate contact pads of large-area first kind pin; Further, between each wafer, specific electric connection can be completed in encapsulating structure inside, instead of outside at encapsulating structure, therefore interference free performance strengthens, thus also improves the reliability and stability of system.On the other hand, for different application, directly change power switch and the power diode of relevant parameter, do not need more changer controller, system is more flexible.Meanwhile, for system developer, faced by be chip piece instead of three chip blocks before, the debugging cycle of system shortens.
Accompanying drawing explanation
Figure 1 shows that the theory diagram of a voltage-dropping type AC-DC power converter;
Figure 2 shows that the schematic diagram being applied to the multichip packaging structure 200 of the AC/DC voltage-dropping type power inverter shown in Fig. 1 be depicted as according to the utility model one embodiment;
Figure 3 shows that the schematic diagram being applied to the multichip packaging structure 200 of the AC/DC voltage-dropping type power inverter shown in Fig. 1 be depicted as according to another embodiment of the utility model;
Fig. 4, is depicted as the schematic block circuit diagram of the voltage-dropping type power inverter of the multichip packaging structure of criteria in application the utility model embodiment.
Embodiment
Below in conjunction with accompanying drawing, several preferred embodiment of the present utility model is described in detail, but the utility model is not restricted to these embodiments.The utility model contain any make on marrow of the present utility model and scope substitute, amendment, equivalent method and scheme.To have the utility model to make the public and understand thoroughly, in following the utility model preferred embodiment, describe concrete details in detail, and do not have the description of these details also can understand the utility model completely for a person skilled in the art.
With reference to figure 1, be depicted as the theory diagram of an AC/DC voltage-dropping type power inverter 100.In this embodiment, AC/DC voltage-dropping type power inverter 100 comprises rectification circuit 101, filter capacitor C
in, voltage-dropping type power stage circuit and controller 103.
Rectification circuit 101 and filter capacitor C
inbe connected in alternating-current voltage source V successively in parallel respectively
aCtwo ends, with to alternating-current voltage source V
aCcarry out rectification and filtering, thus at filter capacitor C
intwo ends generate direct voltage V
iN.
By power device S
w, power diode D
rwith outputting inductance L
pthe voltage-dropping type power stage circuit of composition receives direct voltage V
iNusing as input voltage.Here with power device S
wfor N-type MOSFET is example, power device S
wdrain electrode be connected to filter capacitor C
inanode IN+ to receive direct voltage V
iN, source electrode is connected to power diode D
rnegative electrode, power diode D
ranode be connected to filter capacitor C
innegative terminal IN-, i.e. direct voltage V
iNnegative terminal.Outputting inductance L
pbe coupled to power device S
wwith power diode D
rshared tie point and the anode of load 103 between; The negative terminal of load 103 is connected to filter capacitor C
innegative terminal.
Controller 103 according to the real time information of output current flowing through load 103, by feedback to produce corresponding control signal V
gcontrol the on off state of power device, be maintained consistent with desired value to make the output current flowing through load 103.
In order to obtain the real time information of the output current flowing through load 103, the implementation taked at the present embodiment is in output current loop, Series detectors resistance R
sense.Detect resistance R
sensethe pressure drop at two ends and output current direct proportionality, thus obtain the real time information of output current.
When realizing this AC/DC voltage-dropping type power inverter with IC regime, different integration modes can be selected.But because this voltage-dropping type power inverter directly receives alternating-current voltage source, therefore, the requirement of withstand voltage of power device and power diode is very high, such as, can be 500V or more than 600V.Such requirement of withstand voltage is when needing to adopt very strict manufacturing process just can carry out many power devices or integrated between power device and controller.And if each power device and controller can be individually integrated, then integrated technique is relatively simple, also relative maturity some.When controller 103 is a single controller wafer, power device S
wbe a single power device die, and power diode D
rwhen being a single power diode wafer, controller wafer has the first earth terminal GNDS using as signal ground.Filter capacitor C
innegative terminal IN-be used as Power Groud as the second earth terminal.In order to control signal V
gcan Direct driver power device S
w, i.e. control signal V
gcan Direct driver power device S
wgrid control its turn-on and turn-off state, by power device S
wsource electrode be coupled to the first earth terminal, make power device S
wwith controller wafer, there is common ground reference, thus control signal V
gcan directly as power device S
wdrive singal.Now, resistance R is detected
senseone end be connected to power device S
wsource electrode and power diode D
rpoints of common connection A, the other end is connected to outputting inductance L
pone end, and be connected to the first power end GNDS.The detection signal V at points of common connection A place
sensecontroller wafer (controller 103) is inputed to as feedback signal.
With reference to figure 2, be depicted as the schematic diagram being applied to the multichip packaging structure 200 of the AC/DC voltage-dropping type power inverter shown in Fig. 1 according to the utility model one embodiment.
In this embodiment, multichip packaging structure 200 comprises the lead frame be made up of multiple pin, controller wafer 201, power device die 202 and power diode wafer 203.
Existing standard type lead frame has the slide holder being positioned at the orthogonal of lead frame central area or foursquare rule usually, since support the wafer laid thereon, and be positioned at lead frame outer peripheral areas and the finger-like pin of the multiple orthogonal or foursquare rule be separated with this slide holder, electrode on wafer is connected to corresponding finger-like pin by bonding wire, thus is outwards drawn by current potential.
And in the present embodiment, the lead frame be made up of multiple pin is not identical with existing general standard type lead frame, it comprises first kind pin and Second Type pin.
Wherein, first kind pin comprise the central area being positioned at lead frame in a rectangular shape intermediate contact pads and be connected with intermediate contact pads and be positioned at the peripheral pin of the outer peripheral areas of lead frame.Here, in order to lay wafer above intermediate contact pads, to support wafer, and according to actual circuit structure, whether select directly to be electrically connected between wafer.
Concrete, first kind pin 204 comprises intermediate contact pads 204-1 and peripheral pin 204-2.Controller wafer 201 is positioned on intermediate contact pads 204-1.According to circuit structure as shown in Figure 1, because the bottom of controller wafer 201 and intermediate contact pads 204-1 can not need to be electrically connected, therefore, controller wafer 201 can be bonded to the upper surface of intermediate contact pads 204-1 by insulating material.Intermediate contact pads 204-1 only plays the mechanical support effect to controller wafer 201.
First kind pin 205 comprises intermediate contact pads 205-1 and peripheral pin 205-2.Power device die 202 is positioned on intermediate contact pads 205-1.For N-type mosfet transistor, according to manufacturing process, the bottom of power device die 202 is drain potential, and top comprises grid potential and source potential.The circuit structure diagram of the voltage-dropping type power inverter according to Fig. 1, power device S
wthe higher direct voltage V of drain electrode receiver voltage
iNusing as input voltage.Therefore, be directly electrically connected in the bottom of power device die 202 and intermediate contact pads 205-1, the peripheral pin 205-2 be connected with intermediate contact pads accordingly has drain potential, using as input pin IN+.Due to power device S
wdrain electrode need bear higher voltage, intermediate contact pads has larger area, therefore has better heat dispersion, prevents the temperature rise of power device too high, and damages its service behaviour.
First kind pin 206 comprises intermediate contact pads 206-1 and peripheral pin 206-2.Power diode wafer 203 is positioned on intermediate contact pads 206-1.Different manufacturing process, the polar sites of power diode wafer 203 is not identical.When the bottom of power diode wafer 203 is cathode potential, when top is anode potential, power diode wafer 203 formal dress is positioned on intermediate contact pads 206-1, and, directly be electrically connected between the bottom of power diode wafer 203 and intermediate contact pads 206-1, the peripheral pin 206-2 be connected with intermediate contact pads 206-1 accordingly has cathode potential.The circuit structure diagram of the voltage-dropping type power inverter according to Fig. 1, power diode D
rnegative electrode be connected to power device S
wsource electrode, and be connected to and detect resistance R
senseone end, and be connected to controller 103.Power diode D
rnegative electrode need to bear good voltage and current, therefore, the negative electrode of power diode wafer 203 is directly placed with on the surface of intermediate contact pads 206-1, better heat dispersion can be realized, prevent temperature too high and the phenomenon such as damage of the device caused.
According to the difference of manufacturing process, when the bottom of power diode wafer 203 is anode potential, when top is cathode potential, power diode wafer 203 also can be positioned on the intermediate contact pads 206-1 of first kind pin 206 in upside-down mounting.The mode of being flip-chip mounted can be existing upside-down mounting implementation, is no longer described in detail at this.
On the other hand, directly controller wafer 201 can be realized in encapsulating structure 200 inside by bonding wire, the electric connection between the corresponding electrode between power device die 202 and power diode wafer 203.Concrete, the source S of power device die 202 is connected to intermediate contact pads 206-1 by bonding wire 207, namely the negative electrode C of power diode wafer 203.The detection signal electrode SEN of controller wafer 203 is connected to intermediate contact pads 206-1 by bonding wire 208, so that detection signal is passed to controller wafer 203, to produce corresponding control signal according to this.The control signal electrode ctrl of controller wafer 203 is connected to the gate electrode of power device die 202 by bonding wire 209, to control the turn-on and turn-off state of power device, thus regulate the output current of buck convertor to remain constant.
Compared with the implementation of carrying out being electrically connected in encapsulating structure outside, the modes such as the wiring of such as PCB, by this implementation, less by external interference, systematic function is more stable; Further, for system developer, the debugging of system also can be convenient, and regulating cycle shortens.
Meanwhile, in order to by controller wafer 201, power device die 202 and power diode wafer 203 need the extraction of the electrode externally carrying out exposed electrical connection, corresponding electrode can be connected to corresponding Second Type pin by bonding wire.Such as, the anode electrode A at the top of power diode wafer 203 is connected to Second Type pin IN-by bonding wire 210.The power electrode VC of controller wafer 201 is connected to Second Type pin VCC by bonding wire 211, and signal ground electrode GND is connected to Second Type pin GNDS by bonding wire 212.In order to ensure that bonding wire can bear larger electric current, bonding wire also can be more than two or two, carrys out the electric current that shared is larger.
Multichip packaging structure 200 also comprises plastic packaging shell 213, in order to by lead frame, power device die 202, power diode wafer 203 and controller wafer 201 carries out plastic packaging, and make the peripheral pin of lead frame and Second Type pin portions exposed, realize chip and outside electric connection.
In order to realize the regularly arranged of the external pin of chip-packaging structure, Second Type pin also can be vacant, such as Second Type pin 214.
Not identical according to the manufacturing process of power device die and power diode wafer, the position of its electrode may not be identical.According to the position distribution of electrode, and the circuit connecting relation of power inverter, the position between each wafer and annexation can be set.
With reference to figure 3, be depicted as the schematic diagram being applied to the multichip packaging structure 300 of the AC/DC voltage-dropping type power inverter shown in Fig. 1 according to another embodiment of the utility model.
In this embodiment, multichip packaging structure 300 comprises the lead frame be made up of multiple pin, controller wafer 201, power device die 202 and power diode wafer 203.
Lead frame comprises multiple first kind pin and multiple Second Type pin.First kind pin comprise the central area being positioned at lead frame in a rectangular shape intermediate contact pads and be connected with intermediate contact pads and be positioned at the peripheral pin of the outer peripheral areas of lead frame.Here, in order to lay wafer above intermediate contact pads, with the direct electric connection supported wafer and between wafer and lead frame.
With the embodiment of the multichip packaging structure shown in Fig. 2 unlike, controller wafer 201 is not be positioned on another independent first kind pin, but be directly bonded to the upper surface of power device die 202 by insulating material, further to reduce the size of chip-packaging structure.
The lower surface of power device die 202 is directly electrically connected to the intermediate contact pads 304-1 of first kind pin 304, make the peripheral pin 304-2 connected with intermediate contact pads 304-1 have the electric polarity identical with the lower surface of power device die 202, and then with the peripheral pin 304-2 that intermediate contact pads 304-1 connects, also there is the electric polarity identical with the lower surface of power device die 202.Here, the number of the peripheral pin of first kind pin can be 1, also can be more than 2 or 2.With reference to the circuit theory diagrams of the voltage-dropping type power inverter shown in figure 1, be N-type mosfet transistor for power device die 202, drain electrode is positioned at the lower surface of power device die 202, source electrode and grid are positioned at the upper surface of power device die 202, drain electrode needs to bear larger voltage and current, therefore, by controller wafer is placed on power device wafer, make under identical package dimension, the area shared by first kind pin placing power device die 202 can be large as much as possible, ensure that there is good heat dispersion, the reliability and stability of raising system.
When the bottom of power diode wafer 203 is cathode potential, when top is anode potential, power diode wafer 203 formal dress is positioned on the intermediate contact pads 305-1 of first kind pin 305, and, directly be electrically connected between the bottom of power diode wafer 203 and intermediate contact pads 305-1, the peripheral pin 305-2 be connected with intermediate contact pads 305-1 accordingly has cathode potential.
With reference to the circuit theory diagrams of the voltage-dropping type power inverter shown in figure 1, controller, has specific electrical connection between power device and power diode.If directly the electric connection between each device can be realized in encapsulating structure inside, compared to the electric connection in encapsulating structure outside, can be less by extraneous interference, stability and the reliability of system are better.The annexation of encapsulating structure inside includes but not limited to following connected mode:
The source electrode S of the upper surface of power device die 201 is connected to intermediate contact pads 305-1 by bonding wire 307, because intermediate contact pads has the electric polarity identical with the negative electrode of power diode wafer 203, therefore, the electric connection between the source electrode of power device and the negative electrode of power diode is achieved by bonding wire 307.
According to detection resistance R
sensethe detection signal V produced
senseneed to input to controller wafer 201 as feedback signal.The source electrode of power device and the points of common connection of power diode, namely the negative electrode of power diode wafer 203 needs to be connected to controller wafer 201.Therefore, by bonding wire 308, the intermediate contact pads 305-1 with the negative electrode of power diode can be connected to the detection signal electrode SEN of controller wafer 203, to receive this detection signal and to produce corresponding control signal according to this.
The control signal electrode ctrl of the upper surface of controller wafer 201 is connected to the gate electrode G of power device die 201 by bonding wire 306, to control the turn-on and turn-off state of power device, thus regulate the output current of buck convertor to remain constant.
Meanwhile, in order to by controller wafer 201, power device die 202 and power diode wafer 203 need the extraction of the electrode externally carrying out exposed electrical connection, corresponding electrode can be connected to corresponding Second Type pin by bonding wire.Such as, the anode electrode A at the top of power diode wafer 203 is connected to Second Type pin IN-by bonding wire 309.The power electrode VC of controller wafer 201 is connected to Second Type pin VCC by bonding wire 310, and signal ground electrode GND is connected to Second Type pin GNDS by bonding wire 311.In order to ensure that bonding wire can bear larger electric current, bonding wire also can be more than two or two, carrys out the electric current that shared is larger.
Multichip packaging structure 300 also comprises plastic packaging shell 312, in order to by lead frame, power device die 202, power diode wafer 203 and controller wafer 201 carries out plastic packaging, and make the peripheral pin of lead frame and Second Type pin portions exposed, realize chip and outside electric connection.
In order to realize the regularly arranged of the external pin of chip-packaging structure, Second Type pin also can be vacant, such as Second Type pin 313.
Described in detail the different implementation of multichip packaging structure above by specific embodiment.The type of power device is not limited to N-type mosfet transistor, also can be the power device of other suitable type, such as P type mosfet transistor, BJT bipolar junction transistor etc.The topological structure of power inverter can be voltage-dropping type, or other types, such as booster type, buck-boost type.According to the selection of the type of circuit topology and power device, power device die in multichip packaging structure, the arrangement of power diode wafer and controller wafer, the electric connection of encapsulating structure inside can change accordingly.
With reference to figure 4, be depicted as the schematic block circuit diagram of the voltage-dropping type power inverter of the multichip packaging structure of criteria in application the utility model embodiment.
Multichip packaging structure 402 comprises controller wafer, power device die and power diode wafer, and has input voltage pin IN+, ground pin IN-, power pins VCC, signal ground pin GNDS and detection pin ISEN.
In actual applications, AC power V
aCsuccessively through arranging bridge 401, input capacitance C
iN, filter inductance L
fwith filter capacitor C
frectification and filtering process after, at filter capacitor C
ftwo ends produce direct voltage V
iN.
Two input voltage pin IN+ of multichip packaging structure 402 are connected to filter capacitor C
fanode, low pin IN-is connected to filter capacitor C
fnegative terminal, to receive direct voltage V
iN.
Detect resistance R
sensebe connected to signal ground pin GNDS and detect between pin ISEN, to input to controller wafer, to produce corresponding control signal according to this by characterizing the detection signal flowing through the electric current of LED load.Again because a power end of power device is also connected to signal ground GNDS, therefore, control signal can the control end of Direct driver power device.
Outputting inductance L
pwith output capacitance C
oUTbe sequentially connected in series between signal ground pin GNDS and ground pin IN-, to form a voltage-dropping type power stage circuit with the power device die and power diode wafer of encapsulating structure inside.This voltage-dropping type power stage circuit receives direct voltage V
iN, and control the conducting duty ratio of power device according to control signal, thus produce constant output current at output and carry out driving LED load.
Resistance RB and electric capacity CB is sequentially connected in series between input voltage pin IN+ and signal ground pin GNDS, and the points of common connection of resistance RB and electric capacity CB is connected to power pins VCC, provides power supply supply to give controller wafer.
Described in detail the different implementation of multichip packaging structure above by specific embodiment, and the embody rule circuit of multichip packaging structure.The instruction of above-described embodiment disclosed in the utility model, those skilled in the art can know other circuit frame, the implementation of multichip packaging structure, and embody rule circuit by inference.According to the multichip packaging structure of the utility model embodiment, because power switch and power diode all dispel the heat by the intermediate contact pads of the larger first kind pin of area, there is good heat dispersion, thus improve the power integrated level of unit package area; And the stability of system and reliability have also been obtained raising.
According to embodiment of the present utility model as described above, these embodiments do not have all details of detailed descriptionthe, do not limit the specific embodiment that this utility model is only described yet.Obviously, according to above description, can make many modifications and variations.This specification is chosen and is specifically described these embodiments, is to explain principle of the present utility model and practical application better, thus makes art technical staff that the utility model and the amendment on the utility model basis can be utilized well to use.The utility model is only subject to the restriction of claims and four corner and equivalent.
Claims (12)
1. for a multichip packaging structure for power inverter, it is characterized in that, comprise, lead frame, power device die and power diode wafer; Wherein,
Described lead frame comprises first kind pin and Second Type pin;
Described first kind pin comprise the intermediate contact pads that is positioned at described lead frame zone line and be connected with described intermediate contact pads and be positioned at the peripheral pin of the outer peripheral areas of described lead frame;
Described Second Type pin is positioned at the outer peripheral areas of described lead frame, mutually isolated between described Second Type pin and described first kind pin;
Described power device die is positioned on the intermediate contact pads of first kind pin described in, and the bottom of described power device die becomes to be electrically connected with corresponding described intermediate contact pads;
Described power diode wafer electrical is connected on the intermediate contact pads of first kind pin described in another, has the electric polarity corresponding with an electrode of described power diode wafer to make described first kind pin;
One power electrode at described power device die top is connected to the electrode corresponding to described power diode wafer by bonding wire.
2. multichip packaging structure according to claim 1, is characterized in that, also comprises the controller wafer on the intermediate contact pads being positioned at first kind pin described in another; The bottom of described controller wafer is bonded to corresponding described intermediate contact pads by insulating material.
3. multichip packaging structure according to claim 1, is characterized in that, also comprise be bonded to described power device die by insulating material top on controller wafer.
4. the multichip packaging structure according to Claims 2 or 3, is characterized in that, an electrode of described controller wafer is connected to the electrode of a correspondence at described power device die top by a bonding wire.
5. multichip packaging structure according to claim 1, is characterized in that, the bottom of described power diode wafer is negative electrode, and top is anode.
6. multichip packaging structure according to claim 1, is characterized in that, described power device comprises a N-type mosfet transistor, and drain electrode is positioned at the bottom of described power device die, and grid and source electrode are positioned at the top of described power device die.
7. multichip packaging structure according to claim 1, is characterized in that, described power diode wafer is just being loaded on the intermediate contact pads of described first kind pin.
8. multichip packaging structure according to claim 1, is characterized in that, described power diode flip-chip is on the intermediate contact pads of described first kind pin.
9. multichip packaging structure according to claim 1, is characterized in that, the described power electrode at described power device die top is connected to the intermediate contact pads of the described first kind pin that described power diode wafer is positioned at by bonding wire.
10. multichip packaging structure according to claim 1, is characterized in that, the described power electrode at described power device die top is connected to the electrode of a correspondence at described power diode wafer top by bonding wire.
11. multichip packaging structures according to Claims 2 or 3, is characterized in that, the electrode of described power device die, described power diode wafer and described controller wafer is connected to corresponding described Second Type pin by bonding wire.
12. multichip packaging structures according to Claims 2 or 3, it is characterized in that, also comprise plastic packaging shell, with by described lead frame, described power device die, described power diode wafer and described controller wafer carry out plastic packaging, and make described peripheral pin and described Second Type pin portions exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420363871.5U CN204257629U (en) | 2014-07-02 | 2014-07-02 | For the multichip packaging structure of power inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420363871.5U CN204257629U (en) | 2014-07-02 | 2014-07-02 | For the multichip packaging structure of power inverter |
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|---|---|
| CN204257629U true CN204257629U (en) | 2015-04-08 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104167401A (en) * | 2014-07-02 | 2014-11-26 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure used for power converter |
| WO2017107548A1 (en) * | 2015-12-21 | 2017-06-29 | 深圳市中兴微电子技术有限公司 | Heat dissipating multi-chip frame package structure and preparation method therefor |
| US9837898B2 (en) | 2015-11-26 | 2017-12-05 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Peak-value current mode control for power converters |
-
2014
- 2014-07-02 CN CN201420363871.5U patent/CN204257629U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104167401A (en) * | 2014-07-02 | 2014-11-26 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure used for power converter |
| US9837898B2 (en) | 2015-11-26 | 2017-12-05 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Peak-value current mode control for power converters |
| WO2017107548A1 (en) * | 2015-12-21 | 2017-06-29 | 深圳市中兴微电子技术有限公司 | Heat dissipating multi-chip frame package structure and preparation method therefor |
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Address after: 310051 No. 6 Lianhui Street, Xixing Street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Silergy Semiconductor Technology (Hangzhou ) Co., Ltd. Address before: 310012 Wensanlu Road, Hangzhou Province, No. 90 East Software Park, science and technology building A1501 Patentee before: Silergy Semiconductor Technology (Hangzhou ) Co., Ltd. |