CN204244067U - A kind of sluggish soft starting circuit - Google Patents
A kind of sluggish soft starting circuit Download PDFInfo
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- CN204244067U CN204244067U CN201420587130.5U CN201420587130U CN204244067U CN 204244067 U CN204244067 U CN 204244067U CN 201420587130 U CN201420587130 U CN 201420587130U CN 204244067 U CN204244067 U CN 204244067U
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Abstract
The utility model discloses a kind of sluggish soft starting circuit.Sluggish soft starting circuit comprises bleeder circuit, biasing circuit, hysteresis comparator circuit and capacitor charge and discharge circuit: described bleeder circuit carries out the reference voltage of dividing potential drop as described biasing circuit and described hysteresis comparator circuit and described capacitor charge and discharge circuit to reference voltage; Described biasing circuit is available to described hysteresis comparator circuit bias current; Described hysteresis comparator circuit divides the reference voltage pressed out to compare to the voltage on the electric capacity of described capacitor charge and discharge circuit and described bleeder circuit; Described capacitor charge and discharge circuit is that the electric capacity to described charge-discharge circuit carries out discharge and recharge.The sluggish soft starting circuit utilizing the utility model to provide can prevent current over pulse from damaging power-supply system well.
Description
Technical field
The utility model relates to integrated circuit technique, refers more particularly to sluggish soft starting circuit.
Background technology
In switch power supply system, in order to prevent larger overshoot current from making system injury, being provided with soft starting circuit, output voltage can be made slowly to increase.
Summary of the invention
The utility model is intended to solve the deficiencies in the prior art, provides a kind of sluggish soft starting circuit preventing overshoot current from damaging power-supply system.
Sluggish soft starting circuit, comprises bleeder circuit, biasing circuit, hysteresis comparator circuit and capacitor charge and discharge circuit:
Described bleeder circuit carries out the reference voltage of dividing potential drop as described biasing circuit and described hysteresis comparator circuit and described capacitor charge and discharge circuit to reference voltage;
Described biasing circuit is available to described hysteresis comparator circuit bias current;
Described hysteresis comparator circuit divides the reference voltage pressed out to compare to the voltage on the electric capacity of described capacitor charge and discharge circuit and described bleeder circuit;
Described capacitor charge and discharge circuit is that the electric capacity to described charge-discharge circuit carries out discharge and recharge.
Described bleeder circuit comprises the first resistance, the second resistance and the 3rd resistance:
One termination reference voltage V REF of described first resistance, one end of the second resistance described in another termination and described hysteresis comparator circuit and described capacitor charge and discharge circuit;
One end of first resistance described in one termination of described second resistance and described hysteresis comparator circuit and described capacitor charge and discharge circuit, biasing circuit described in another termination;
One end of second resistance described in one termination of described 3rd resistance and described biasing circuit, other end ground connection.
Described biasing circuit comprises the first amplifier, the first PMOS, the first NMOS tube, the 4th resistance and the second PMOS:
One end of second resistance described in the positive termination of described first amplifier and one end of described 3rd resistance, negative terminal connects the source electrode of described first NMOS tube and one end of described 4th resistance, exports the grid of the first NMOS tube described in termination;
The grid of described first PMOS connects drain electrode and the drain electrode of described first NMOS tube and the grid of described second PMOS, and source electrode meets power supply VCC;
The grid of described first NMOS tube connects the output of described first amplifier, and drain electrode connects the drain and gate of described first PMOS and the grid of described second PMOS, and source electrode connects one end of the 4th resistance and the negative terminal of described first amplifier;
The negative terminal of the first amplifier described in one termination of described 4th resistance and the source electrode of described first NMOS tube, other end ground connection;
The grid of described second PMOS connects the grid of described first PMOS and the drain electrode of drain electrode and described first NMOS tube, and drain electrode connects described hysteresis comparator circuit, and source electrode meets power supply VCC.
Described hysteresis comparator circuit comprises the 3rd PMOS, the second NMOS tube, the 4th PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 5th PMOS and the 6th PMOS:
The grid of described 3rd PMOS connects drain electrode and the grid of described 6th PMOS and the drain electrode of described second NMOS tube, and source electrode meets power supply VCC;
The grid of described second NMOS tube connects the grid of the drain electrode of described 4th PMOS and the grid of described 3rd NMOS tube and drain electrode and described 4th NMOS tube, and drain electrode connects the grid of described 3rd PMOS and the grid of drain electrode and described 6th PMOS, source ground;
The grid of described 4th PMOS connects one end of described first resistance and one end of described second resistance and described capacitor charge and discharge circuit, drain electrode connects the grid of the grid of described second NMOS tube and the grid of described 3rd NMOS tube and drain electrode and described 4th NMOS tube, and source electrode connects the drain electrode of described second PMOS and the source electrode of described 5th PMOS;
The grid of described 3rd NMOS tube connects drain electrode and the drain electrode of the grid of described second NMOS tube and the drain electrode of described 4th PMOS and described 5th NMOS tube and the grid of described 4th NMOS tube, source ground;
The grid of described 4th NMOS tube connects the grid of described 3rd NMOS tube and the drain electrode of drain electrode and the grid of described second NMOS tube and the drain electrode of described 4th PMOS and described 5th NMOS tube, drain electrode connects the grid of the grid of described 5th NMOS tube and described 6th NMOS tube and drain electrode and the grid of described 7th NMOS tube and the drain electrode of described 5th PMOS, source ground;
The grid of described 5th NMOS tube connects the grid of described 6th NMOS tube and the grid of drain electrode and the drain electrode of described 4th NMOS tube and the drain electrode of described 5th PMOS and described 7th NMOS tube, drain electrode connects the grid of the grid of described second NMOS tube and described 3rd NMOS tube and drain electrode and the grid of described 4th NMOS tube and the drain electrode of described 4th PMOS, source ground;
The grid of described 6th NMOS tube connects drain electrode and the grid of the grid of described 5th NMOS tube and the drain electrode of described 4th NMOS tube and described 7th NMOS tube and the drain electrode of described 5th PMOS, source ground;
The grid of described 7th NMOS tube connects the grid of described 5th NMOS tube and the grid of described 6th NMOS tube and drain electrode and the drain electrode of described 4th NMOS tube and the drain electrode of described 5th PMOS, drain electrode connects the drain electrode of described 6th PMOS and described capacitor charge and discharge circuit, source ground;
The grid of described 5th PMOS connects described capacitor charge and discharge circuit, drain electrode connects the grid of the drain electrode of described 4th NMOS tube and the grid of described 5th NMOS tube and described 6th NMOS tube and the grid of drain electrode and described 7th NMOS tube, and source electrode connects the drain electrode of described second PMOS and the source electrode of described 4th PMOS;
The grid of described 6th PMOS connects the grid of described 3rd PMOS and the drain electrode of drain electrode and described second NMOS tube, and drain electrode connects the drain electrode of described 7th NMOS tube and described capacitor charge and discharge circuit, and source electrode meets power supply VCC.
Described capacitor charge and discharge circuit comprises the first inverter, the second inverter, the 7th PMOS, the 8th PMOS, the 8th NMOS tube, the 3rd inverter, the first electric capacity, the 9th NMOS tube and the tenth NMOS tube:
The drain electrode of the 7th NMOS tube described in the input termination of described first inverter and the drain electrode of described 6th PMOS, export the grid of the input of the 3rd inverter and the grid of described 7th PMOS and described tenth NMOS tube described in termination;
The input termination power VCC of described second inverter, exports the grid of the 8th PMOS and the grid of described 8th NMOS tube described in termination;
The grid of described 7th PMOS connects the grid of the output of described first inverter and the input of described 3rd inverter and described tenth NMOS tube, and drain electrode connects the source electrode of described 8th PMOS, and source electrode meets power supply VCC;
The grid of described 8th PMOS connects the output of described second inverter and the grid of described 8th NMOS tube, drain electrode connects the grid of the drain electrode of described 8th NMOS tube and one end of described first electric capacity and described 5th PMOS and the drain electrode of described tenth NMOS tube, and source electrode connects the drain electrode of described 7th PMOS;
The grid of described 8th NMOS tube connects the output of described second inverter and the grid of described 8th PMOS, and drain electrode connects the drain electrode of one end of described first electric capacity and the grid of described 5th PMOS and described tenth NMOS tube, source ground;
The grid of the output of input termination first inverter of described 3rd inverter and the grid of described 7th PMOS and described tenth NMOS tube, exports the grid of the 9th NMOS tube described in termination;
The drain electrode of the grid of the 5th PMOS described in one termination of described first electric capacity and the drain electrode of described tenth NMOS tube and described 8th PMOS and the drain electrode of described 8th NMOS tube, other end ground connection;
The grid of described 9th NMOS tube connects the output of described 3rd inverter, and drain electrode connects the grid of one end of described first resistance and one end of described second resistance and described 4th PMOS, and source electrode connects source electrode and the soft-start signal output of described tenth NMOS tube;
The grid of described tenth NMOS tube connects the input of the grid of described 7th PMOS and the output of described first inverter and described 3rd inverter, drain electrode connects the drain electrode of the grid of described 5th PMOS and one end of described first electric capacity and described 8th PMOS and the drain electrode of described 8th NMOS tube, and source electrode connects source electrode and the soft-start signal output of described 9th NMOS tube.
Supply voltage powers on beginning, voltage on described first electric capacity does not reach and divides through described bleeder circuit the grid voltage being input to described 4th PMOS pressed out, described hysteresis comparator exports as low level, output control level after described first inverter is high, and the grid voltage controlling described 9th NMOS tube after secondary inverter is low level, now described 9th NMOS tube is closed, described tenth NMOS tube is opened, the voltage of the output SS_OUT of soft starting circuit changes along with the grid voltage of described 4th PMOS of described hysteresis comparator circuit.
When the voltage on described first electric capacity be greater than through described bleeder circuit divide press out be input to the grid voltage of described 4th PMOS after, described hysteresis comparator circuit exports as high level, output control level after described first inverter is low, and the grid voltage controlling described 9th NMOS tube after secondary inverter is high level, now described 7th PMOS and described 8th PMOS all conductings, described first electric capacity is charged, described 9th NMOS tube is opened simultaneously, described tenth NMOS tube is closed, the voltage of the output SS_OUT of soft starting circuit slowly rises until equal described bleeder circuit to divide the grid voltage being input to described 4th PMOS pressed out.
In the power supply system, the current maxima of transformer is determined by comparison point VREF1; By controlling comparison point VREF1, the current value of primary coil just can be controlled; Comparison point VREF1 meets the output SS_OUT of described capacitor charge and discharge circuit and is determined by internal circuit, in power up, because SS_OUT slowly rises, so VREF1 is also slow increase, thus control the current value of primary coil, reduce the stress of transformer in power up, prevent magnetic core of transformer saturated.
The sluggish soft starting circuit utilizing the utility model to provide can prevent current over pulse from damaging power-supply system well.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of sluggish soft starting circuit of the present utility model.
Fig. 2 is the circuit diagram of the current value controlling primary coil in power-supply system.
Fig. 3 is power-supply system soft start uphill process figure.
Embodiment
Below in conjunction with accompanying drawing, the utility model content is further illustrated.
Sluggish soft starting circuit, as shown in Figure 1, comprises bleeder circuit 100, biasing circuit 200, hysteresis comparator circuit 300 and capacitor charge and discharge circuit 400:
Described bleeder circuit 100 carries out the reference voltage of dividing potential drop as described biasing circuit 200 and described hysteresis comparator circuit 300 and described capacitor charge and discharge circuit 400 to reference voltage;
Described biasing circuit 200 is available to described hysteresis comparator circuit 300 bias current;
Described hysteresis comparator circuit 300 compares the voltage on the electric capacity of described capacitor charge and discharge circuit 400 and described bleeder circuit 100 points of reference voltages pressed out;
Described capacitor charge and discharge circuit 400 carries out discharge and recharge on the electric capacity of described charge-discharge circuit 400.
Described bleeder circuit 100 comprises the first resistance 101, second resistance 102 and the 3rd resistance 103:
One termination reference voltage V REF of described first resistance 101, one end of the second resistance 102 described in another termination and described hysteresis comparator circuit 300 and described capacitor charge and discharge circuit 400;
One end of first resistance 101 described in one termination of described second resistance 102 and described hysteresis comparator circuit 300 and described capacitor charge and discharge circuit 400, biasing circuit 200 described in another termination;
One end of second resistance 102 described in one termination of described 3rd resistance 103 and described biasing circuit 200, other end ground connection.
Described biasing circuit 200 comprises the first amplifier 201, first PMOS 202, first NMOS tube 203, the 4th resistance 204 and the second PMOS 205:
One end of second resistance 102 described in the positive termination of described first amplifier 201 and one end of described 3rd resistance 103, negative terminal connects the source electrode of described first NMOS tube 203 and one end of described 4th resistance 204, exports the grid of the first NMOS tube 203 described in termination;
The grid of described first PMOS 202 connects drain electrode and the drain electrode of described first NMOS tube 203 and the grid of described second PMOS 205, and source electrode meets power supply VCC;
The grid of described first NMOS tube 203 connects the output of described first amplifier 201, and drain electrode connects the drain and gate of described first PMOS 202 and the grid of described second PMOS 205, and source electrode connects one end of the 4th resistance 204 and the negative terminal of described first amplifier 201;
The negative terminal of the first amplifier 201 described in one termination of described 4th resistance 204 and the source electrode of described first NMOS tube 203, other end ground connection;
The grid of described second PMOS 205 connects the grid of described first PMOS 202 and the drain electrode of drain electrode and described first NMOS tube 203, and drain electrode connects described hysteresis comparator circuit 300, and source electrode meets power supply VCC.
Described hysteresis comparator circuit 300 comprises the 3rd PMOS 301, second NMOS tube 302, the 4th PMOS 303, the 3rd NMOS tube 304, the 4th NMOS tube 305, the 5th NMOS tube 306, the 6th NMOS tube 307, the 7th NMOS tube 308, the 5th PMOS 309 and the 6th PMOS 310:
The grid of described 3rd PMOS 301 connects drain electrode and the grid of described 6th PMOS 310 and the drain electrode of described second NMOS tube 302, and source electrode meets power supply VCC;
The grid of described second NMOS tube 302 connects the grid of the drain electrode of described 4th PMOS 303 and the grid of described 3rd NMOS tube 304 and drain electrode and described 4th NMOS tube 305, drain electrode connects the grid of described 3rd PMOS 301 and the grid of drain electrode and described 6th PMOS 310, source ground;
The grid of described 4th PMOS 303 connects one end of described first resistance 101 and one end of described second resistance 102 and described capacitor charge and discharge circuit 400, drain electrode connects the grid of the grid of described second NMOS tube 302 and the grid of described 3rd NMOS tube 304 and drain electrode and described 4th NMOS tube 305, and source electrode connects the drain electrode of described second PMOS 205 and the source electrode of described 5th PMOS 309;
The grid of described 3rd NMOS tube 304 connects drain electrode and the drain electrode of the grid of described second NMOS tube 302 and the drain electrode of described 4th PMOS 303 and described 5th NMOS tube 306 and the grid of described 4th NMOS tube 305, source ground;
The grid of described 4th NMOS tube 305 connects the grid of described 3rd NMOS tube 304 and the drain electrode of drain electrode and the grid of described second NMOS tube 302 and the drain electrode of described 4th PMOS 303 and described 5th NMOS tube 306, drain electrode connects the grid of the grid of described 5th NMOS tube 306 and described 6th NMOS tube 307 and drain electrode and the grid of described 7th NMOS tube 308 and the drain electrode of described 5th PMOS 309, source ground;
The grid of described 5th NMOS tube 306 connects the grid of described 6th NMOS tube 307 and the grid of drain electrode and the drain electrode of described 4th NMOS tube 305 and the drain electrode of described 5th PMOS 309 and described 7th NMOS tube 308, drain electrode connects the grid of the grid of described second NMOS tube 302 and described 3rd NMOS tube 304 and drain electrode and the grid of described 4th NMOS tube 305 and the drain electrode of described 4th PMOS 303, source ground;
The grid of described 6th NMOS tube 307 connects drain electrode and the grid of the grid of described 5th NMOS tube 306 and the drain electrode of described 4th NMOS tube 305 and described 7th NMOS tube 308 and the drain electrode of described 5th PMOS 309, source ground;
The grid of described 7th NMOS tube 308 connects the grid of described 5th NMOS tube 306 and the grid of described 6th NMOS tube 307 and drain electrode and the drain electrode of described 4th NMOS tube 305 and the drain electrode of described 5th PMOS 309, drain electrode connects drain electrode and the described capacitor charge and discharge circuit 400 of described 6th PMOS 310, source ground;
The grid of described 5th PMOS 309 connects described capacitor charge and discharge circuit 400, drain electrode connects the grid of the drain electrode of described 4th NMOS tube 305 and the grid of described 5th NMOS tube 306 and described 6th NMOS tube 307 and the grid of drain electrode and described 7th NMOS tube 308, and source electrode connects the drain electrode of described second PMOS 205 and the source electrode of described 4th PMOS 303;
The grid of described 6th PMOS 310 connects the grid of described 3rd PMOS 301 and the drain electrode of drain electrode and described second NMOS tube 302, and drain electrode connects drain electrode and the described capacitor charge and discharge circuit 400 of described 7th NMOS tube 308, and source electrode meets power supply VCC.
Described capacitor charge and discharge circuit 400 comprises the first inverter 401, second inverter 402, the 7th PMOS 403, the 8th PMOS 404, the 8th NMOS tube 405, the 3rd inverter 406, first electric capacity 407, the 9th NMOS tube 408 and the tenth NMOS tube 409:
The drain electrode of the 7th NMOS tube 308 described in the input termination of described first inverter 401 and the drain electrode of described 6th PMOS 310, export the grid of the input of the 3rd inverter 406 and the grid of described 7th PMOS 403 and described tenth NMOS tube 409 described in termination;
The input termination power VCC of described second inverter 402, exports the grid of the 8th PMOS 404 and the grid of described 8th NMOS tube 405 described in termination;
The grid of described 7th PMOS 403 connects the grid of the output of described first inverter 401 and the input of described 3rd inverter 406 and described tenth NMOS tube 409, and drain electrode connects the source electrode of described 8th PMOS 404, and source electrode meets power supply VCC;
The grid of described 8th PMOS 404 connects the output of described second inverter 402 and the grid of described 8th NMOS tube 405, drain electrode connects the grid of the drain electrode of described 8th NMOS tube 405 and one end of described first electric capacity 407 and described 5th PMOS 309 and the drain electrode of described tenth NMOS tube 409, and source electrode connects the drain electrode of described 7th PMOS 403;
The grid of described 8th NMOS tube 405 connects the output of described second inverter 402 and the grid of described 8th PMOS 404, drain electrode connects the drain electrode of one end of described first electric capacity 407 and the grid of described 5th PMOS 309 and described tenth NMOS tube 409, source ground;
The grid of the output of input termination first inverter 401 of described 3rd inverter 406 and the grid of described 7th PMOS 403 and described tenth NMOS tube 409, exports the grid of the 9th NMOS tube 408 described in termination;
The drain electrode of the grid of the 5th PMOS 309 described in one termination of described first electric capacity 407 and the drain electrode of described tenth NMOS tube 409 and described 8th PMOS 404 and the drain electrode of described 8th NMOS tube 405, other end ground connection;
The grid of described 9th NMOS tube 408 connects the output of described 3rd inverter 406, drain electrode connects the grid of one end of described first resistance 101 and one end of described second resistance 102 and described 4th PMOS 303, and source electrode connects source electrode and the soft-start signal output of described tenth NMOS tube 409;
The grid of described tenth NMOS tube 409 connects the input of the grid of described 7th PMOS 403 and the output of described first inverter 401 and described 3rd inverter 406, drain electrode connects the drain electrode of the grid of described 5th PMOS 309 and one end of described first electric capacity 407 and described 8th PMOS 404 and the drain electrode of described 8th NMOS tube 405, and source electrode connects source electrode and the soft-start signal output of described 9th NMOS tube 408.
Supply voltage powers on beginning, voltage on described first electric capacity 407 does not reach the grid voltage being input to described 4th PMOS 303 pressed out through described bleeder circuit 100 points, described hysteresis comparator circuit 300 exports as low level, output control level after described first inverter is high, and the grid voltage controlling described 9th NMOS tube 408 after secondary inverter 406 is low level, now described 9th NMOS tube 408 is closed, described tenth NMOS tube 409 is opened, the voltage of the output SS_OUT of soft starting circuit changes along with the grid voltage of described 4th PMOS 303 of described hysteresis comparator circuit 300.
When the voltage on described first electric capacity 407 be greater than through described bleeder circuit 100 points press out be input to the grid voltage of described 4th PMOS 303 after, described hysteresis comparator 300 exports as high level, output control level after described first inverter is low, and the grid voltage controlling described 9th NMOS tube 408 after secondary inverter 406 is high level, now described 7th PMOS 403 and described 8th PMOS 404 all conductings, described first electric capacity 407 is charged, described 9th NMOS tube 408 is opened simultaneously, described tenth NMOS tube 409 is closed, the voltage of the output SS_OUT of soft starting circuit slowly rises until equal the grid voltage being input to described 4th PMOS 303 that described bleeder circuit 100 points presses out.
Be illustrated in figure 2 in power-supply system the circuit diagram of the current value controlling primary coil, in the power supply system, the current maxima of transformer is determined by comparison point VREF1; By controlling comparison point VREF1, the current value of primary coil just can be controlled; Comparison point VREF1 meets the output SS_OUT of described capacitor charge and discharge circuit 400 and is determined by internal circuit, in power up, because SS_OUT slowly rises, so VREF1 is also slow increase, thus control the current value of primary coil, reduce the stress of transformer in power up, prevent magnetic core of transformer saturated.
Be illustrated in figure 3 power-supply system soft start uphill process figure.
Claims (5)
1. sluggish soft starting circuit, is characterized in that comprising bleeder circuit, biasing circuit, hysteresis comparator circuit and capacitor charge and discharge circuit:
Described bleeder circuit carries out the reference voltage of dividing potential drop as described biasing circuit and described hysteresis comparator circuit and described capacitor charge and discharge circuit to reference voltage;
Described biasing circuit is available to described hysteresis comparator circuit bias current;
Described hysteresis comparator circuit divides the reference voltage pressed out to compare to the voltage on the electric capacity of described capacitor charge and discharge circuit and described bleeder circuit;
Described capacitor charge and discharge circuit is that the electric capacity to described charge-discharge circuit carries out discharge and recharge.
2. sluggish soft starting circuit as claimed in claim 1, is characterized in that described bleeder circuit comprises the first resistance, the second resistance and the 3rd resistance:
One termination reference voltage V REF of described first resistance, one end of the second resistance described in another termination and described hysteresis comparator circuit and described capacitor charge and discharge circuit;
One end of first resistance described in one termination of described second resistance and described hysteresis comparator circuit and described capacitor charge and discharge circuit, biasing circuit described in another termination;
One end of second resistance described in one termination of described 3rd resistance and described biasing circuit, other end ground connection.
3. sluggish soft starting circuit as claimed in claim 1, is characterized in that described biasing circuit comprises the first amplifier, the first PMOS, the first NMOS tube, the 4th resistance and the second PMOS:
One end of positive termination second resistance of described first amplifier and one end of the 3rd resistance, negative terminal connects the source electrode of described first NMOS tube and one end of described 4th resistance, exports the grid of the first NMOS tube described in termination;
The grid of described first PMOS connects drain electrode and the drain electrode of described first NMOS tube and the grid of described second PMOS, and source electrode meets power supply VCC;
The grid of described first NMOS tube connects the output of described first amplifier, and drain electrode connects the drain and gate of described first PMOS and the grid of described second PMOS, and source electrode connects one end of the 4th resistance and the negative terminal of described first amplifier;
The negative terminal of the first amplifier described in one termination of described 4th resistance and the source electrode of described first NMOS tube, other end ground connection;
The grid of described second PMOS connects the grid of described first PMOS and the drain electrode of drain electrode and described first NMOS tube, and drain electrode connects described hysteresis comparator circuit, and source electrode meets power supply VCC.
4. sluggish soft starting circuit as claimed in claim 1, is characterized in that described hysteresis comparator circuit comprises the 3rd PMOS, the second NMOS tube, the 4th PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 5th PMOS and the 6th PMOS:
The grid of described 3rd PMOS connects drain electrode and the grid of described 6th PMOS and the drain electrode of described second NMOS tube, and source electrode meets power supply VCC;
The grid of described second NMOS tube connects the grid of the drain electrode of described 4th PMOS and the grid of described 3rd NMOS tube and drain electrode and described 4th NMOS tube, and drain electrode connects the grid of described 3rd PMOS and the grid of drain electrode and described 6th PMOS, source ground;
The grid of described 4th PMOS connects one end of the first resistance and one end of the second resistance and capacitor charge and discharge circuit, drain electrode connects the grid of the grid of described second NMOS tube and the grid of described 3rd NMOS tube and drain electrode and described 4th NMOS tube, and source electrode connects the drain electrode of the second PMOS and the source electrode of the 5th PMOS;
The grid of described 3rd NMOS tube connects drain electrode and the drain electrode of the grid of described second NMOS tube and the drain electrode of the 4th PMOS and the 5th NMOS tube and the grid of the 4th NMOS tube, source ground;
The grid of described 4th NMOS tube connects the grid of described 3rd NMOS tube and the drain electrode of drain electrode and the grid of described second NMOS tube and the drain electrode of described 4th PMOS and described 5th NMOS tube, drain electrode connects the grid of the grid of described 5th NMOS tube and described 6th NMOS tube and drain electrode and the grid of described 7th NMOS tube and the drain electrode of described 5th PMOS, source ground;
The grid of described 5th NMOS tube connects the grid of described 6th NMOS tube and the grid of drain electrode and the drain electrode of described 4th NMOS tube and the drain electrode of described 5th PMOS and described 7th NMOS tube, drain electrode connects the grid of the grid of described second NMOS tube and described 3rd NMOS tube and drain electrode and the grid of described 4th NMOS tube and the drain electrode of described 4th PMOS, source ground;
The grid of described 6th NMOS tube connects drain electrode and the grid of the grid of described 5th NMOS tube and the drain electrode of described 4th NMOS tube and described 7th NMOS tube and the drain electrode of described 5th PMOS, source ground;
The grid of described 7th NMOS tube connects the grid of described 5th NMOS tube and the grid of described 6th NMOS tube and drain electrode and the drain electrode of described 4th NMOS tube and the drain electrode of described 5th PMOS, drain electrode connects the drain electrode of described 6th PMOS and described capacitor charge and discharge circuit, source ground;
The grid of described 5th PMOS connects described capacitor charge and discharge circuit, drain electrode connects the grid of the drain electrode of described 4th NMOS tube and the grid of described 5th NMOS tube and described 6th NMOS tube and the grid of drain electrode and described 7th NMOS tube, and source electrode connects the drain electrode of described second PMOS and the source electrode of described 4th PMOS;
The grid of described 6th PMOS connects the grid of described 3rd PMOS and the drain electrode of drain electrode and described second NMOS tube, and drain electrode connects the drain electrode of described 7th NMOS tube and described capacitor charge and discharge circuit, and source electrode meets power supply VCC.
5. sluggish soft starting circuit as claimed in claim 1, is characterized in that described capacitor charge and discharge circuit comprises the first inverter, the second inverter, the 7th PMOS, the 8th PMOS, the 8th NMOS tube, the 3rd inverter, the first electric capacity, the 9th NMOS tube and the tenth NMOS tube:
The drain electrode of input termination the 7th NMOS tube of described first inverter and the drain electrode of the 6th PMOS, export the grid of the input of the 3rd inverter and the grid of described 7th PMOS and described tenth NMOS tube described in termination;
The input termination power VCC of described second inverter, exports the grid of the 8th PMOS and the grid of described 8th NMOS tube described in termination;
The grid of described 7th PMOS connects the grid of the output of described first inverter and the input of described 3rd inverter and described tenth NMOS tube, and drain electrode connects the source electrode of described 8th PMOS, and source electrode meets power supply VCC;
The grid of described 8th PMOS connects the output of described second inverter and the grid of described 8th NMOS tube, drain electrode connects the grid of the drain electrode of described 8th NMOS tube and one end of described first electric capacity and the 5th PMOS and the drain electrode of the tenth NMOS tube, and source electrode connects the drain electrode of described 7th PMOS;
The grid of described 8th NMOS tube connects the output of described second inverter and the grid of described 8th PMOS, and drain electrode connects the drain electrode of one end of described first electric capacity and the grid of described 5th PMOS and described tenth NMOS tube, source ground;
The grid of the output of input termination first inverter of described 3rd inverter and the grid of described 7th PMOS and described tenth NMOS tube, exports the grid of the 9th NMOS tube described in termination;
The drain electrode of the grid of the 5th PMOS described in one termination of described first electric capacity and the drain electrode of described tenth NMOS tube and described 8th PMOS and the drain electrode of described 8th NMOS tube, other end ground connection;
The grid of described 9th NMOS tube connects the output of described 3rd inverter, and drain electrode connects the grid of one end of the first resistance and one end of the second resistance and the 4th PMOS, and source electrode connects source electrode and the soft-start signal output of described tenth NMOS tube;
The grid of described tenth NMOS tube connects the input of the grid of described 7th PMOS and the output of described first inverter and described 3rd inverter, drain electrode connects the drain electrode of the grid of described 5th PMOS and one end of described first electric capacity and described 8th PMOS and the drain electrode of described 8th NMOS tube, and source electrode connects source electrode and the soft-start signal output of described 9th NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420587130.5U CN204244067U (en) | 2014-10-08 | 2014-10-08 | A kind of sluggish soft starting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420587130.5U CN204244067U (en) | 2014-10-08 | 2014-10-08 | A kind of sluggish soft starting circuit |
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| CN204244067U true CN204244067U (en) | 2015-04-01 |
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| CN201420587130.5U Expired - Fee Related CN204244067U (en) | 2014-10-08 | 2014-10-08 | A kind of sluggish soft starting circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106354189A (en) * | 2016-10-27 | 2017-01-25 | 厦门新页微电子技术有限公司 | Low-threshold-value enable circuit with hysteresis function |
| CN108897366A (en) * | 2018-07-13 | 2018-11-27 | 上海东软载波微电子有限公司 | Offset start-up circuit, integrated high voltage circuit and integrated low-voltage circuit |
-
2014
- 2014-10-08 CN CN201420587130.5U patent/CN204244067U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106354189A (en) * | 2016-10-27 | 2017-01-25 | 厦门新页微电子技术有限公司 | Low-threshold-value enable circuit with hysteresis function |
| CN106354189B (en) * | 2016-10-27 | 2017-09-29 | 厦门新页微电子技术有限公司 | A kind of Low threshold with lag function enables circuit |
| CN108897366A (en) * | 2018-07-13 | 2018-11-27 | 上海东软载波微电子有限公司 | Offset start-up circuit, integrated high voltage circuit and integrated low-voltage circuit |
| CN108897366B (en) * | 2018-07-13 | 2020-04-28 | 上海东软载波微电子有限公司 | Bias starting circuit, integrated high-voltage circuit and integrated low-voltage circuit |
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