CN204216886U - A kind of dynamic bias superregeneration receiver - Google Patents
A kind of dynamic bias superregeneration receiver Download PDFInfo
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- CN204216886U CN204216886U CN201420698202.3U CN201420698202U CN204216886U CN 204216886 U CN204216886 U CN 204216886U CN 201420698202 U CN201420698202 U CN 201420698202U CN 204216886 U CN204216886 U CN 204216886U
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Abstract
The utility model provides a kind of dynamic bias superregeneration receiver, on traditional superregenerative wireless receiver basis, increases peakvalue's checking and auxiliary tail Current Feedback Control mechanism.By the output amplitude that sogicon in receiver in detection initialize signal " 1 " situation exports, take out the comparative level as rear class comparator by certain percentage, then judgement is compared to the output amplitude of oscillator.When signal is " 1 ", the auxiliary tail current source of superregenerator is opened, and now Induction Peried is accelerated, and when signal is " 0 ", auxiliary current source is closed.Therefore by Autonomous test and feedback control mechanism, strengthen the biased tail current of the superregenerator under " 1 " input signal, thus increase oscillator data-signal be " 1 " and for " 0 " time Induction Peried poor, and then increase signal " 1 ", the envelope difference between " 0 ".This technology is conducive to the demodulation of rear class envelope detection circuit, effectively improves the antijamming capability of receiver.
Description
Technical field
The utility model belongs to analog circuit, relates to a kind of dynamic bias superregenerative radio receiver technology with FEEDBACK CONTROL.
Background technology
Superregeneration receiver a kind ofly relies on the change of internal oscillator Induction Peried to identify the device of input signal power, typical superregeneration receiver is primarily of reception antenna, low noise amplifier (Low Noise Amplifier, LNA), superregenerator (Super Regeneration Oscillator, SRO), envelope detection demodulator circuit and black out signal produce the formations such as circuit, as shown in Figure 1.
The core of superregeneration receiver is superregenerator.And superregenerator is actually the oscillator that is operated in intermittent oscillation state, chopper frequency is determined (controlling by low frequency black out signal generator or extinguishing oscillator) by black out signal.When not receiving signal, the Induction Peried of oscillator within each resting period is a metastable value; Upon receipt of the signal, the Induction Peried of oscillator within each resting period will shorten, therefore, the envelope of oscillator output signal having, no signal time there will be difference, the modulation signal of input can by rear class envelope detection circuit according to envelope difference demodulation out.The key of superregeneration receiver be exactly utilize superregenerator having, no signal time Induction Peried difference receive and judge signal, therefore, the difference of Induction Peried also determines the sensitivity of receiver to a great extent.
In addition, the oscillator in superregeneration receiver is generally LC-VCO.As shown in Figure 2, its equivalent analysis circuit as shown in Figure 3 for the LC-VCO of a typical CMOS technology realization.In figure 3, L and C is inductance in frequency selective network and electric capacity, forms shunt-resonant circuit, G
0be the equivalent conductance of LC resonant tank, characterize the energy dissipation in loop self ,-G
ait is the negative conductance that the differential coupling amplifier formed by active device M1, M2, M3, the M4 in Fig. 2 provides.Work as G
0-G
afor time negative, active device consumed energy provides negative conductance to be enough to make up the energy dissipation in LC loop self, makes this loop can starting of oscillation.-Ga is determined by the size of M1-M4 transistor and tail current source size.In LC-VCO, tail current is larger in fig. 2 ,-the G that the differential coupling amplifier that M1, M2, M3, M4 are formed provides
aabsolute value is larger, and loop is easier starting of oscillation also.
In tradition superregenerative wireless receiver, the tail current of LC-VCO is biased to " 1 ", and " 0 " input signal is fixing, and Induction Peried depends primarily on the intensity difference of input signal.This time difference determines sensitivity and the antijamming capability of receiver.
Utility model content
Technical problem to be solved:
The purpose of this utility model is for the problems referred to above, designs a kind of dynamic bias superregeneration receiver with Autonomous test acceleration starting of oscillation function.
Technical scheme:
In order to realize above function, the utility model provides a kind of dynamic bias superregeneration receiver, it is characterized in that: this superregeneration receiver have employed a kind of Autonomous test and accelerates starting of oscillation superregenerative oscillator, and described superregenerator adds peak detector, comparator and auxiliary tail current source circuit on the basis of conventional superregenerator; The output of described superregenerator connects peak detector and connects comparator, and the output of comparator is as the control signal of auxiliary tail current source circuit.
Described conventional superregenerator comprises electric capacity, inductance, resistance and some metal-oxide-semiconductors, and wherein, NMOS tube M5 and NMOS tube M6 forms current mirror load, shunt capacitance, inductance and PMOS M7; NMOS tube M5 branch road connects the drain electrode of input signal end Vin1, NMOS tube M6 branch road connects the drain electrode of input signal end Vin2, the source electrode of PMOS M7 connects NMOS tube M6 branch road, the source electrode that drain electrode connects NMOS tube M5 branch input signal end Vin1, Vin2 is connected, and connects the drain electrode of PMOS M3; External power source series resistance and PMOS M1, PMOS M1 Mirroring of tributary obtains PMOS M3 branch road.
As improvement of the present utility model, the superregenerator of described routine and auxiliary tail current source circuit constitute the Autonomous test dynamic bias pierce circuit with auxiliary tail current source, wherein auxiliary current source comprises PMOS M2 branch road, it is made up of to PMOS M2 branch road PMOS M1 Mirroring of tributary, transmission gate and M4 switching tube form control switch, and the defeated control signal CON of comparator controls the unlatching of this branch road; Concrete, transmission gate is composed in parallel by a PMOS M8 and NMOS tube M9, the drain electrode of NMOS tube M9 and the source electrode of PMOS M8 connect the grid of PMOS M1, the drain electrode of PMOS M8 and the source electrode of NMOS tube M9 connect the grid of PMOS M2 and the source electrode of PMOS M4, the grid of NMOS tube M9 connects the grid of PMOS M4, and the grid of PMOS M8 connects the grid that the defeated control signal CON of comparator connects PMOS M4 again; The drain electrode of PMOS M2 connects input signal end, source ground; PMOS M4 grounded drain.
As improvement of the present utility model, described peak detector comprises diode, resistance, electric capacity, and the positive pole of described diode connects input signal, negative pole parallel resistance and inductance, the other end ground connection of resistance and inductance; The negative pole of described diode is as output signal end; When the diode conducts, input signal is by diode to capacitor charging, and the current potential on electric capacity raises; When diode ends, electric capacity is by conductive discharge, and current potential reduces.
As improvement of the present utility model, described comparator currents comprises the single metal-oxide-semiconductor of M1 to M7, and wherein the drain electrode of NMOS tube M3, NMOS tube M4, NMOS tube M6 connects the source ground of outside high level VDD, PMOS M5, PMOS M7; The grid of NMOS tube M3 connects its source electrode, and connects the grid of NMOS tube M4; The source electrode of NMOS tube M3 connects the drain electrode of PMOS M1, and the source electrode of NMOS tube M4 connects the drain electrode of PMOS M2; The grid of PMOS M1 connects input signal Vin, and the grid of PMOS M2 connects reference voltage Vref, and the source electrode of PMOS M1 and PMOS M2 connects the drain electrode of PMOS M5; The source electrode of NMOS tube M4 connects the grid of NMOS tube M6, and the source electrode of NMOS tube M6 connects PMOS M7 drain electrode, and as output signal end Vout; Bias voltage source V
bIASconnect the grid of PMOS M7.
Beneficial effect:
The dynamic bias superregeneration receiver that the utility model proposes is detected by peak detector and keeps the output peak value of oscillator, pass through bleeder circuit, take out the certain percentage of peak value, as the benchmark of comparator below, compare with the output peak value of oscillator again with this benchmark.So, tail current when data-signal is " 1 " is larger time comparatively data-signal is " 0 ", therefore Autonomous test dynamic bias mechanism further increase oscillator data-signal be " 1 " and for " 0 " time Induction Peried poor, more be conducive to rear class demodulation, effectively improve the antijamming capability of superregeneration receiver.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the utility model is further illustrated:
Fig. 1 is traditional superregenerative wireless receiver;
Fig. 2, Fig. 3 are typical LC oscillator;
The dynamic bias superregeneration receiver syndeton schematic diagram that Fig. 4 provides for the utility model;
Peak detector (PKD) circuit that Fig. 5 provides for the utility model;
The comparator circuit that Fig. 6 provides for the utility model;
Fig. 7 is conventional tail current offset LC-VCO circuit realiration;
Autonomous test dynamic bias LC-VCO circuit realiration in the dynamic bias superregeneration receiver that Fig. 8 provides for the utility model.
Embodiment
The utility model provides a kind of dynamic bias superregeneration receiver, and for making the purpose of this utility model, technical scheme and effect clearly, clearly, and further describe the utility model with reference to accompanying drawing examples.Should be appreciated that concrete enforcement described herein is only in order to explain the utility model, and be not used in restriction the utility model.
The dynamic bias superregeneration receiver that the utility model proposes has Autonomous test and accelerates starting of oscillation function, as shown in Figure 4, this superregeneration receiver have employed a kind of Autonomous test and accelerates starting of oscillation superregenerative oscillator, and described superregenerator adds peak detector, comparator and auxiliary tail current source circuit on the basis of conventional superregenerator; The output of described superregenerator connects peak detector and connects comparator, and the output of comparator is as the control signal of auxiliary tail current source circuit.Tradition superregeneration receiver is by low noise amplifier, and superregenerator, black out signal generator, envelope detection demodulator circuit is formed.Autonomous test accelerates starting of oscillation dynamic bias circuit by peak detector PKD, and comparator and auxiliary tail current source are formed.
First, due to sogicon compare when " 1 " signal inputs " 0 " signal input time starting of oscillation faster, therefore when first time " 1 " signal input, detected by peak detector and keep the output peak value of oscillator, pass through bleeder circuit, take out the certain percentage of peak value, as the benchmark of comparator below, compare with the output peak value of oscillator again with this benchmark.When the input of " 1 " signal, comparator Output rusults is 1, and when the input of " 0 " signal, comparator Output rusults is 0.This control signal feeds back to auxiliary tail current source circuit again.When input signal is " 0 ", because oscillator signal input peak value is less than reference level, now feedback signal does not open auxiliary current source.When input signal is " 1 ", oscillator signal input peak value is greater than reference level, and now feedback signal opens accessory power supply.So, tail current when data-signal is " 1 " is larger time comparatively data-signal is " 0 ", therefore Autonomous test dynamic bias mechanism further increase oscillator data-signal be " 1 " and for " 0 " time Induction Peried poor, more be conducive to rear class demodulation, effectively improve the antijamming capability of superregeneration receiver.This circuit can make of standard CMOS process.
Conventional superregenerator described in the utility model as shown in Figure 7, includes electric capacity, inductance, resistance and some metal-oxide-semiconductors, and wherein, NMOS tube M5 and NMOS tube M6 forms current mirror load, shunt capacitance, inductance and PMOS M7; NMOS tube M5 branch road connects the drain electrode of input signal end Vin1, NMOS tube M6 branch road connects the drain electrode of input signal end Vin2, the source electrode of PMOS M7 connects NMOS tube M6 branch road, the source electrode that drain electrode connects NMOS tube M5 branch input signal end Vin1, Vin2 is connected, and connects the drain electrode of PMOS M3; External power source series resistance and PMOS M1, PMOS M1 Mirroring of tributary obtains PMOS M3 branch road.
As improvement of the present utility model, Fig. 7 gives the complete realization that the Autonomous test dynamic bias realized by CMOS technology accelerates start-oscillation circuit.The superregenerator of described routine and auxiliary tail current source circuit constitute the Autonomous test dynamic bias pierce circuit with auxiliary tail current source, wherein auxiliary current source comprises PMOS M2 branch road, it is made up of to PMOS M2 branch road PMOS M1 Mirroring of tributary, transmission gate and M4 switching tube form control switch, and the defeated control signal CON of comparator controls the unlatching of this branch road; Concrete, transmission gate is composed in parallel by a PMOS M8 and NMOS tube M9, the drain electrode of NMOS tube M9 and the source electrode of PMOS M8 connect the grid of PMOS M1, the drain electrode of PMOS M8 and the source electrode of NMOS tube M9 connect the grid of PMOS M2 and the source electrode of PMOS M4, the grid of NMOS tube M9 connects the grid of PMOS M4, and the grid of PMOS M8 connects the grid that the defeated control signal CON of comparator connects PMOS M4 again; The drain electrode of PMOS M2 connects input signal end, source ground; PMOS M4 grounded drain.When input signal is " 0 ", now feedback signal closing transmission door, and the grid potential of the M2 of auxiliary tail current mirror is moved to ground, auxiliary current source is not opened.When input signal is " 1 ", oscillator signal exports peak value and is greater than reference level, and now feedback signal opens transmission gate, and then starts auxiliary current source.Therefore, this circuit, when input signal is " 1 ", can strengthens LV-VCO tail current and be biased, by
be increased to
.Thus increase oscillator data-signal be " 1 " and for " 0 " time Induction Peried poor, be more conducive to rear class demodulation, improve antijamming capability.
As improvement of the present utility model, the peak detector PKD(peak detector provided) can circuit realiration as shown in Figure 5, diode D, resistance R and electric capacity C constitute low pass filter.If under being operated in large-scale condition, when the diode conducts, input signal is charged to C by diode, and the current potential on electric capacity C raises; When diode ends, electric capacity C is discharged by R, and current potential reduces.Usually, R>>R
d, wherein R
dfor the equivalent conducting resistance of diode, so charging process is fast and discharge process is slow.Its output voltage size follows the peak value of input signal always, and remains on the peak-peak of input signal.Concrete method of attachment is as follows, and the positive pole of described diode connects input signal, negative pole parallel resistance and inductance, the other end ground connection of resistance and inductance; The negative pole of described diode is as output signal end; When the diode conducts, input signal is by diode to capacitor charging, and the current potential on electric capacity raises; When diode ends, electric capacity is by conductive discharge, and current potential reduces.
As improvement of the present utility model, comparator circuit realizes can see Fig. 6, this circuit be one be operated in open loop situations under amplifier.Amplifier is made up of two-stage amplifying unit.The first order is the differential amplifier of a current mirror load (M3, M4 form), M1 and M2 is input amplifier tube, and M5 is tail current offset.The common-source amplifier that M6 and M7 is formed is second level amplifying circuit.When peak detection exports the reference voltage V being greater than setting
reftime, it exports control signal is high level, otherwise is low level.Specifically, comparator circuit comprises the single metal-oxide-semiconductor of M1 to M7, and wherein the drain electrode of NMOS tube M3, NMOS tube M4, NMOS tube M6 connects the source ground of outside high level VDD, PMOS M5, PMOS M7; The grid of NMOS tube M3 connects its source electrode, and connects the grid of NMOS tube M4; The source electrode of NMOS tube M3 connects the drain electrode of PMOS M1, and the source electrode of NMOS tube M4 connects the drain electrode of PMOS M2; The grid of PMOS M1 connects input signal Vin, and the grid of PMOS M2 connects reference voltage Vref, and the source electrode of PMOS M1 and PMOS M2 connects the drain electrode of PMOS M5; The source electrode of NMOS tube M4 connects the grid of NMOS tube M6, and the source electrode of NMOS tube M6 connects PMOS M7 drain electrode, and as output signal end Vout; Bias voltage source V
bIASconnect the grid of PMOS M7.
Be understandable that; for those of ordinary skills; can be equal to according to the technical solution of the utility model and utility model design thereof and replace or change, and all these change or replace the protection range that all should belong to the claim appended by the utility model.
Claims (5)
1. a dynamic bias superregeneration receiver, it is characterized in that: this superregeneration receiver have employed a kind of Autonomous test and accelerates starting of oscillation superregenerative oscillator, and described superregenerator adds peak detector, comparator and auxiliary tail current source circuit on the basis of conventional superregenerator; The output of described superregenerator connects peak detector and connects comparator, and the output of comparator is as the control signal of auxiliary tail current source circuit.
2. a kind of dynamic bias superregeneration receiver according to claim 1, it is characterized in that: described conventional superregenerator comprises electric capacity, inductance, resistance and some metal-oxide-semiconductors, wherein, NMOS tube M5 and NMOS tube M6 forms current mirror load, shunt capacitance, inductance and PMOS M7; NMOS tube M5 branch road connects the drain electrode of input signal end Vin1, NMOS tube M6 branch road connects the drain electrode of input signal end Vin2, the source electrode of PMOS M7 connects NMOS tube M6 branch road, the source electrode that drain electrode connects NMOS tube M5 branch input signal end Vin1, Vin2 is connected, and connects the drain electrode of PMOS M3; External power source series resistance and PMOS M1, PMOS M1 Mirroring of tributary obtains PMOS M3 branch road.
3. a kind of dynamic bias superregeneration receiver according to claim 2, it is characterized in that: the superregenerator of described routine and auxiliary tail current source circuit constitute the Autonomous test dynamic bias pierce circuit with auxiliary tail current source, wherein auxiliary current source comprises PMOS M2 branch road, it is made up of to PMOS M2 branch road PMOS M1 Mirroring of tributary, transmission gate and M4 switching tube form control switch, and the defeated control signal CON of comparator controls the unlatching of this branch road; Concrete, transmission gate is composed in parallel by a PMOS M8 and NMOS tube M9, the drain electrode of NMOS tube M9 and the source electrode of PMOS M8 connect the grid of PMOS M1, the drain electrode of PMOS M8 and the source electrode of NMOS tube M9 connect the grid of PMOS M2 and the source electrode of PMOS M4, the grid of NMOS tube M9 connects the grid of PMOS M4, and the grid of PMOS M8 connects the grid that the defeated control signal CON of comparator connects PMOS M4 again; The drain electrode of PMOS M2 connects input signal end, source ground; PMOS M4 grounded drain.
4. a kind of dynamic bias superregeneration receiver according to claim 2, it is characterized in that: described peak detector comprises diode, resistance, electric capacity, the positive pole of described diode connects input signal, negative pole parallel resistance and inductance, the other end ground connection of resistance and inductance; The negative pole of described diode is as output signal end; When the diode conducts, input signal is by diode to capacitor charging, and the current potential on electric capacity raises; When diode ends, electric capacity is by conductive discharge, and current potential reduces.
5. a kind of dynamic bias superregeneration receiver according to claim 2, it is characterized in that: described comparator currents comprises the single metal-oxide-semiconductor of M1 to M7, wherein the drain electrode of NMOS tube M3, NMOS tube M4, NMOS tube M6 connects the source ground of outside high level VDD, PMOS M5, PMOS M7; The grid of NMOS tube M3 connects its source electrode, and connects the grid of NMOS tube M4; The source electrode of NMOS tube M3 connects the drain electrode of PMOS M1, and the source electrode of NMOS tube M4 connects the drain electrode of PMOS M2; The grid of PMOS M1 connects input signal Vin, and the grid of PMOS M2 connects reference voltage Vref, and the source electrode of PMOS M1 and PMOS M2 connects the drain electrode of PMOS M5; The source electrode of NMOS tube M4 connects the grid of NMOS tube M6, and the source electrode of NMOS tube M6 connects PMOS M7 drain electrode, and as output signal end Vout; Bias voltage source V
bIASconnect the grid of PMOS M7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420698202.3U CN204216886U (en) | 2014-11-20 | 2014-11-20 | A kind of dynamic bias superregeneration receiver |
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| CN201420698202.3U CN204216886U (en) | 2014-11-20 | 2014-11-20 | A kind of dynamic bias superregeneration receiver |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467887A (en) * | 2014-11-20 | 2015-03-25 | 东南大学 | Dynamic offset superregenerative receiver |
| CN113572490A (en) * | 2021-07-23 | 2021-10-29 | 东南大学 | Super-regenerative receiver with automatic frequency search |
| CN114039548A (en) * | 2021-11-12 | 2022-02-11 | 江苏稻源科技集团有限公司 | LC oscillator for accelerating oscillation starting |
-
2014
- 2014-11-20 CN CN201420698202.3U patent/CN204216886U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467887A (en) * | 2014-11-20 | 2015-03-25 | 东南大学 | Dynamic offset superregenerative receiver |
| CN104467887B (en) * | 2014-11-20 | 2017-12-12 | 东南大学 | A kind of dynamic bias superregenerative receiver |
| CN113572490A (en) * | 2021-07-23 | 2021-10-29 | 东南大学 | Super-regenerative receiver with automatic frequency search |
| CN114039548A (en) * | 2021-11-12 | 2022-02-11 | 江苏稻源科技集团有限公司 | LC oscillator for accelerating oscillation starting |
| CN114039548B (en) * | 2021-11-12 | 2022-07-19 | 江苏稻源科技集团有限公司 | LC oscillator for accelerating oscillation starting |
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Granted publication date: 20150318 Termination date: 20171120 |
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| CF01 | Termination of patent right due to non-payment of annual fee |