CN204216882U - A kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip - Google Patents
A kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip Download PDFInfo
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Abstract
The utility model discloses a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip, comprise main flow PC, data acquisition module, PCI-e module, high performance signal source, band-pass filter group, DUT test carrier plate, two-way digital power and far-end remote control device, DUT test carrier plate is connected with mother baby plate form with high-Speed Data-Acquisition Module, then is connected with high performance signal source by radio frequency cable; Two-way digital power by supply socket be high-Speed Data-Acquisition Module, DUT test carrier plate powers; PCI-e module is inserted in the PCI-e slot of PC as subcard; High Speed High Precision ADC chip to be measured, by Fiber connection, is loaded the high density SOCKET slot on DUT test carrier plate by PCI-e module and high-Speed Data-Acquisition Module; Far-end remote control device is used for Long-distance Control main flow PC.The utility model input cost is low, and measuring accuracy is high, and Long-distance Control increases flexibility, is specially adapted to the performance test before the production in enormous quantities of High Speed High Precision ADC chip, small lot batch manufacture test.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly related to a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip, be suitable for the small lot batch manufacture before the production of ADC chip batch and prototype test.
Background technology
Digital receiver is widely used in the fields such as communication, digital TV in high resolution, radar, electronic countermeasures, sonar and Medical Instruments, for traditional receivers, digital receiver tool has great advantage, its core component is high-end analog to digital converter (ADC) chip, and the performance index of such chip directly limit the characteristic such as frequency, bandwidth, power consumption, volume of digital receiver.The machine system implementations such as next generation communication base station, radar are intermediate frequency (IF) Direct Sampling, single receiver supports channel transmission, this scheme requires harsher than conventional architectures a lot to ADC chip performance, consider that multiple radio frequency is planned simultaneously, system requirements bandwidth will reach more than 100MHz, therefore develop High Speed High Precision ADC chip to enforcement high-end integrated circuit strategy of industrial development, seize the commanding elevation of high-end core integrated circuit (IC) design, there is positive effect.
High Speed High Precision ADC chip is developed flow process and is comprised design, manufacture, laboratory test, batch link such as product test and reliability testing, wherein criticizes product test and comprises middle survey, becomes to survey.Become to survey and occupy extremely important status in chip research and development, batch product testing expense of high-end ADC chip product occupies most of cost of chip research and development, its main cause is that a set of High Speed High Precision ADC chip testing environment (the comprising software restraint) expense for ATE board of exploitation is very expensive, if becoming the design defect finding chip product in survey process, that becomes the R&D work before survey to need closed loop again, and such caused time cost and Financial cost are unaffordable concerning a company.
Summary of the invention
For the deficiency that prior art exists, object of the present invention just there are provided a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip, design team can not only be helped to carry out fast to it before ADC chip is produced in enormous quantities, comprehensive function and performance test, find the problem and blemish relating to the stage, design problem and defect are positioned, feed back to designer again to revise, simultaneously for batch ATE board test program development that product test team carries out provides guidance, to reach optimal inspection parameter, reduce the testing time, reduce batch target of producing testing cost, also possesses the ability for client provides the small lot print through test of knowing the real situation to produce, thus reach the help chip enterprise shortening research and development of products cycle, accelerate Time To Market, more rapid and better obtain the target of economic benefit.
To achieve these goals, the technical solution used in the present invention is such: a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip, be made up of main flow PC, data acquisition module, PCI-e module, high performance signal source, band-pass filter group, DUT test carrier plate, two-way digital power and far-end remote control device, described main flow PC is connected with data acquisition module, PCI-e module, high performance signal source respectively, and data acquisition module is connected by optical fiber with PCI-e module; Described high performance signal source has three, and its output signal is first through band-pass filter group, and band-pass filter group output signal is connected with DUT test carrier plate through radio frequency cable again; Described data acquisition module is connected with DUT test carrier plate, two-way digital power respectively, described data acquisition module is connected in mother baby plate mode by high speed receptacle with DUT test carrier plate, described two-way digital power is that data acquisition module is powered by high-speed high-density electric connector socket, and is that DUT test carrier plate is powered by high-speed high-density electric connector socket; Described far-end remote control device comprises sensing cell and radio-cell, and sends wireless signal to main flow PC; Wherein, sensing cell comprises physical button and touch control screen, for sensing the action of main flow PC; Radio-cell comprises WLAN, bluetooth, infrared ray, for transmitting/receiving wireless signal.
During system works, High Speed High Precision ADC chip to be measured is loaded in DUT test carrier plate, High Speed High Precision ADC chip converts digital signal to analog signal and delivers to data acquisition module, digital collection module is sent to PCI-e module by optical fiber data, PCI-e module is stored in the data received on the hard disk of main flow PC, last performance evaluation program carries out performance evaluation to these data, and whole testing process full automation, does not need manual intervention.
As a kind of preferred version, described PCI-e module is be data acquisition module based on fpga chip based on the PCI-e module of fpga chip, data acquisition module, the described PCI-e module based on fpga chip, the model of fpga chip all adopted based on the data acquisition module of fpga chip are XC5VLX110T, wherein the logic that realizes of fpga chip inside all realizes based on the IP CORE of XILINX company, this implementation not only contributes to the stability of raising system, and can accelerate the construction cycle of whole project.Fpga chip based on the PCI-e module of fpga chip, the fpga chip based on the data acquisition module of fpga chip are all connected with Flash configuring chip, Flash data storage chip, DDR3 memory chip, clock driver circuit, optical interface module, jtag interface, LED light, reset circuit, AccessPort circuit, and described clock driver circuit includes crystal oscillator; Described reset circuit is made up of reset chip and reset button, and reset chip is connected with reset button; Described AccessPort circuit is by serial port chip and nine cores point connector, and AccessPort circuit is connected with nine core point connectors by serial port chip; The described PCI-e module based on fpga chip also includes digital power module group and PCI-e bus golden finger, and PCI-e bus golden finger is connected with the fpga chip of the PCI-e module based on fpga chip; Described digital power module group is connected to PCI-e bus golden finger; The described data acquisition module based on fpga chip also includes power circuit and high-speed high-density electric connector socket, and high-speed high-density electric connector socket is connected with the fpga chip of the data acquisition module based on fpga chip; Described power electric route power socket and digital power module, the external two-way digital power of supply socket and being connected with digital power module.
Described PCI-e module is inserted in the PCI-e slot of main flow PC, for receiving the digital signal converted to by ADC chip of data acquisition module block movement, again these data are stored in main flow PC hard disk with the form of dat form and carry out performance evaluation for Performance Analysis Software, test analysis software carries out fft analysis to these data, counting as 16K/32K/64K/1M/2M/4M of intercepting.The core devices of PCI-e module adopts Xilinx company model to be the fpga chip of XC5VLX110T, achieves RS232 protocol communication, the Aurora fiber optic protocols communication of XILINX company, PCI-e protocol communication and controlling functions.PCI-e module external interface has RS232 serial ports, optical communication interface, PCI-e interface, LED light, reseting interface, various interface circuit is all connected with fpga chip, its panel has four openings, LED light, reset circuit, AccessPort circuit and optical interface module are exposed from opening portion, for debugging, with other model calling and data communication.
Described data acquisition module is connected with mother baby plate form with DUT test carrier plate as motherboard, the digital signal that ADC chip converts to is stored in the inner FIFO of FPGA, then by optical fiber, data is sent to PCI-e module.Data acquisition module core devices adopts Xilinx company model to be the fpga chip of XC5VLX110T, achieves RS232 protocol communication, SPI communication protocol, the Aurora fiber optic protocols communication of XILINX company, the communication Protocol Conversion of RS232 to SPI, logic control function.Data acquisition module external interface has RS232 serial ports, optical communication interface, LED light, reseting interface, high-speed high-density electric connector socket, and total interface circuit is all connected with fpga chip.Wherein the high-speed high-density electric connector socket of data acquisition module docks mutually with the high-speed high-density electric connector socket on DUT test carrier plate, is connected with the I/O pin of fpga chip for the pin such as data, clock, configuration, control ADC chip to be measured.
Simultaneously, after data acquisition module is connected with DUT test carrier plate, can be placed in high-low temperature test chamber, by power line, data acquisition module is powered, by optical fiber, data are sent to PCI-e module, namely the present invention supports the performance test of High Speed High Precision ADC chip under high and low temperature environment.
As a kind of preferred version, described DUT test carrier plate comprises high density SOCKET slot, high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit, IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3, LED light, analog power module, digital power module, and described high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit are all connected with high density SOCKET slot; Described IMD index test input circuit, common dynamic indicator input SMA connector SMA3 is connected to analog input signal commutation circuit; Described analog power module, digital power module are all connected with high-speed high-density electric connector socket.
Described DUT test carrier plate, dock with mother baby plate form with data acquisition module as daughter board, for loading High Speed High Precision ADC chip to be measured, and by high density SOCKET slot, the pin such as output data, clock, control of ADC chip is connected with the fpga chip I/O pin on data acquisition module.During system works, the digital signal of ADC chip conversion can be stored in the inner FIFO of FPGA.
As a kind of preferred version, by 5 constant virtues, described ADC chip reset circuit is shown in that dynamic indicator inputs SMA connector SMA5 and differential driving chip forms, and 5 constant virtues sees that dynamic indicator input SMA connector SMA5 is connected with differential driving chip; Described ADC chip clock circuit inputs SMA connector SMA4 by the 4th common dynamic indicator and the first differential transformers forms, and the 4th common dynamic indicator input SMA connector SMA4 is connected with the first differential transformers; Described analog input signal commutation circuit is made up of radio frequency converting switch and the second differential transformers, and radio frequency converting switch is connected with the second differential transformers; Described IMD index test input circuit inputs SMA connector SMA1 by the first common dynamic indicator, the second common dynamic indicator inputs SMA connector SMA2 and power combiner forms, first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 are all connected with power combiner, and power combiner is connected to radio frequency converting switch.
As a kind of preferred version, described band-pass filter group comprises the first band pass filter, second band pass filter and the 3rd band pass filter, high performance signal source comprises the first high performance signal source, second high performance signal source and third high performance signals source, described first external first band pass filter in high performance signal source is as clock signal, second external second band pass filter in high performance signal source is as the first analog input signal, external 3rd band pass filter in third high performance signals source is as the second analog input signal, and clock signal, first analog input signal, second analog input signal all transfers to DUT test carrier plate.
Described clock signal, the first analog input signal, the second analog input signal all transfer to the ADC chip on DUT test carrier plate, wherein enter the data-signal amplitude peak of ADC chip for-1dBFS, and the frequency of the first analog input signal, the second analog input signal and amplitude can adjust.
Compared with prior art, beneficial effect of the present invention:
1. can evaluate and test LVDS(supporting rate 800MHz) high-speed, high precision, the super high-speed A/D C chip performance index of interface or LVCMOS interface;
2. can evaluate and test the dynamic indicator of ADC chip: SNR, SFDR, SINAD, IMD, ENOB, THD, harmonic wave; The static parameter of ADC chip can be evaluated and tested: INL, DNL;
3. support the frequency-domain analysis of time domain, 32K/64K/1M/2M/4M sampled point;
4. support light mouth, general SPI interface, GPIO Interface Controller;
5. ADC chip data interface optional (LVDS or LVCMOS);
6. supporting signal incoming frequency Lookup protocol (GPIO control);
7., as long as change DUT test carrier plate and performance test analysis software, the present invention just can be applicable to the testing performance index of the chips such as DAC, receiving system integrated monolithic, base band signal process;
8. be provided with remote control device, add flexibility, test more easily;
9. cost of the present invention is low, efficiency is high, flexible, help ADC chip R&D team proofing chip function and performance rapidly and accurately, avoid expensive automatic test equipment simultaneously and bring heavy cost burden to chip development; Not only help finished product test team develops efficiently as early as possible, the ADC chip product test vector of high precision; And do not increasing under development cost prerequisite, can provide for client the small lot print tested through high and low temperature, help the rapid completion system checking of client, accelerate the Time To Market of consumer product, thus obtain faster and better economic benefit.
Accompanying drawing explanation
Fig. 1 is the system configuration schematic diagram of the embodiment of the present invention;
Fig. 2 is the circuit structure diagram of PCI-e module in the embodiment of the present invention;
Fig. 3 is the circuit structure diagram of data acquisition module in the embodiment of the present invention;
Fig. 4 is the DUT test carrier plate circuit structure diagram in the embodiment of the present invention.
Embodiment
Below with reference to specific embodiment, technical scheme provided by the invention is described in detail, following embodiment should be understood and be only not used in for illustration of the present invention and limit the scope of the invention.
Embodiment:
As shown in Figure 1, a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip, be made up of main flow PC, data acquisition module, PCI-e module, high performance signal source, band-pass filter group, DUT test carrier plate, two-way digital power and far-end remote control device, described main flow PC is connected with data acquisition module, PCI-e module, high performance signal source respectively, and data acquisition module is connected by optical fiber with PCI-e module; Described high performance signal source has three, and its output signal is first through band-pass filter group, and band-pass filter group output signal is connected with DUT test carrier plate through radio frequency cable again; Described data acquisition module is connected with DUT test carrier plate, two-way digital power respectively, described data acquisition module is connected in mother baby plate mode by high-speed high-density electric connector socket with DUT test carrier plate, described two-way digital power is that data acquisition module is powered by supply socket, and is that DUT test carrier plate is powered by high-speed high-density electric connector socket; Described far-end remote control device comprises sensing cell and radio-cell, and sends wireless signal to main flow PC; Described high performance signal source is high frequency, Low phase noise signal source.
As shown in Figure 2, described PCI-e module is the PCI-e module based on fpga chip, the model of its fpga chip is XC5VLX110T, fpga chip based on the PCI-e module of fpga chip is connected with Flash configuring chip, Flash data storage chip, DDR3 memory chip, clock driver circuit, optical interface module, jtag interface, LED light, reset circuit, AccessPort circuit, and described clock driver circuit includes crystal oscillator; Described reset circuit is made up of reset chip and reset button, and reset chip is connected with reset button; Described AccessPort circuit is by serial port chip and nine cores point connector, and AccessPort circuit is connected with nine core point connectors by serial port chip; The described PCI-e module based on fpga chip also includes digital power module group and PCI-e bus golden finger, and PCI-e bus golden finger is connected with the fpga chip of the PCI-e module based on fpga chip; Described digital power module group is connected to PCI-e bus golden finger.Described Flash configuring chip loads the configuration data of FPGA when system electrification; Flash data memory chip stores the data message that FPGA design is wanted, and these information can not be lost because of system power failure; DDR3 memory chip is used for the data in enormous quantities that buffered optical fibers interface is sent here, then through PCI-e interface, data is write hard disc of computer; Clock driver circuit produces two-way clock, and a road is used for fpga logic clock, the HSSI High-Speed Serial Interface special clock that a road uses as PCI-E, optical interface module.Optical interface module is used for the communication between PCI-e module and data acquisition module, and in the present invention, optical communications protocols adopts the Aurora agreement of XILINX company, transmission rate 3.125GSPS; Reset circuit provides reset signal for FPGA design logic, and it is controlled by two kinds of modes, and the first is by reset button by manual reset, and after the second is loaded by fpga chip completion logic, " DONE " signal realizes automatically reseting; AccessPort circuit is used for debugging and the condition monitoring of fpga chip; Digital power module group provides various direct voltage for the various chips that PCI-e module uses, and kind has 3.3V, 1.8V, 1.2V and 1V.
As shown in Figure 3, described data acquisition module is the data acquisition module based on fpga chip, the model of its fpga chip adopted is XC5VLX110T, fpga chip based on the data acquisition module of fpga chip is all connected with Flash configuring chip, Flash data storage chip, DDR3 memory chip, clock driver circuit, optical interface module, jtag interface, LED light, reset circuit, AccessPort circuit, and described clock driver circuit includes crystal oscillator; Described reset circuit is made up of reset chip and reset button, and reset chip is connected with reset button; Described AccessPort circuit is by serial port chip and nine cores point connector, and AccessPort circuit is connected with nine core point connectors by serial port chip; The described data acquisition module based on fpga chip also includes power circuit and high-speed high-density electric connector socket, and high-speed high-density electric connector socket is connected with the fpga chip of the data acquisition module based on fpga chip; Described power electric route power socket and digital power module, the external two-way digital power of supply socket and being connected with digital power module.Described optical interface module is for realizing the optical fiber communication of data acquisition module and PCI-e module, and communication protocol adopts the Aurora agreement of XILINX company, transmission rate 3.125GSPS; Power electric route power socket and digital power module composition, the external two-way digital power of supply socket, input voltage 7.5 volts, digital power module converts 3.3V, 1.8V, 1.2V and 1V to 7.5 volts, in addition, input voltage 7.5 volts also receives the power pin of high-speed high-density electric connector socket, for powering for DUT test carrier plate; The signal pin of high-speed high-density electric connector socket is corresponding with fpga chip I/O pin to be connected, and that is the clock of ADC chip to be measured, data, control and configuration pin are connected with the I/O pin of fpga chip by this connector.DDR3 memory chip is used for the translation data of buffer memory high-speed ADC chip, improves the throughput of system; Flash data memory chip, Flash configuring chip, clock driver circuit, reset circuit are the same with the function of corresponding circuits in PCI-e module.
As shown in Figure 4, described DUT test carrier plate comprises high density SOCKET slot, high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit, IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3, LED light, analog power module, digital power module, and described high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit are all connected with high density SOCKET slot; Described IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3 are connected to analog input signal commutation circuit; Described analog power module, digital power module are all connected with high-speed high-density electric connector socket; By 5 constant virtues, described ADC chip reset circuit is shown in that dynamic indicator inputs SMA connector SMA5 and differential driving chip forms, and 5 constant virtues sees that dynamic indicator input SMA connector SMA5 is connected with differential driving chip; Described ADC chip clock circuit inputs SMA connector SMA4 by the 4th common dynamic indicator and the first differential transformers forms, and the 4th common dynamic indicator input SMA connector SMA4 is connected with the first differential transformers; Described analog input signal commutation circuit is made up of radio frequency converting switch and the second differential transformers, and radio frequency converting switch is connected with the second differential transformers; Described IMD index test input circuit inputs SMA connector SMA1 by the first common dynamic indicator, the second common dynamic indicator inputs SMA connector SMA2 and power combiner forms, first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 are all connected with power combiner, and power combiner is connected to radio frequency converting switch.Described high density SOCKET slot loads High Speed High Precision ADC chip to be measured, and the pin such as output clock, data, control, configuration of ADC chip to be measured is connected with the corresponding pin of high-speed high-density electric connector socket through it.DUT test carrier plate is connected with mother baby plate form with data acquisition module by high-speed high-density electric connector socket, and this just equals ADC chip correlation output pin to be measured to be connected in the I/O pin of fpga chip on data acquisition module.ADC chip reset circuit converts differential reset signal single side reset signal to by differential driving chip, then completes the reset to ADC chip to be measured; ADC chip clock circuit converts differential clock signal single-ended clock signal to by the first differential transformers and is input to ADC chip to be measured by the corresponding pin of high density SOCKET slot again; Analog input signal commutation circuit, according to the Different Dynamic performance of test ADC chip, is selected different analog input signal modes, when test I MD index, selects double-tone input signal, when testing other dynamic indicator, selects single-tone input signal.IMD index test input circuit produces the double-tone input signal required for test ADC chip I MD performance index, two single-ended single-tone analog signals become double-tone single-ended signal after power combiner synthesis, convert through the second differential transformers the signal input part that differential analog signal delivers to ADC chip to be measured to again, the second differential transformers solves the problem of signalling channel impedance matching simultaneously; 3rd common dynamic indicator input SMA connector SMA3 is used for providing single-tone single-ended analog input signal for ADC chip, this signal converts through the second differential transformers the signal input part that differential analog signal delivers to ADC chip to be measured to again, and the second differential transformers also solves the problem of signalling channel impedance matching simultaneously; LED light is the information such as fpga chip running status on monitoring power supply, data acquisition module; Analog power module and digital power module are used for voltage transitions, their power supply input is 7.5 volts of voltages that high-speed high-density electric connector socket provides, output voltage kind comprise simulation 1.8 volts, digital 1.8 volts, simulate 3.3 volts, digital 3.3 volts, these kind power supplys are for being the chip on DUT test carrier plate, ADC chip power supply to be measured.
Embodiment 1: when specifically implementing, comprises the steps:
(1) High Speed High Precision ADC chip to be measured is loaded the high-speed and high-density SOCKET slot on DUT test carrier plate;
(2) external two-way digital power is opened, for data acquisition module and DUT test carrier plate provide 7.5 volts of power supplys;
(3) the first high performance signal source is used to provide clock signal for ADC chip to be measured, the clock signal that described first high performance signal source provides requires to possess extremely low phase noise, as far as possible for ADC chip to be measured provides desired clock source, in order to promote clock source quality further, the centre frequency of the first band pass filter of described first high performance signal source output terminal serial connection is 1 ~ 2MHz;
(4) analog input signal commutation circuit is set on DUT test carrier plate, analog channel is chosen as the 3rd common dynamic indicator input SMA connector SMA3, the second high performance signal source is used to provide analog input signal for ADC chip to be measured, the analog input signal that described second high performance signal source provides requires to possess extremely low phase noise, such ability accurately tests out the performance index of ADC chip to be measured, and the performance not so tested out is likely just the index of input signal; In order to promote analog input signal quality, meet the needs of ADC chip index test to be measured to phase noise or shake, the centre frequency of the second band pass filter of described second high performance signal source output terminal serial connection is 1 ~ 2MHz, test ADC chip performance index at different frequencies, need the band pass filter corresponding to this frequency, therefore, high performance band-pass filter group is needed;
(5) on main flow PC, " ADC chip performance analysis software " is run, open human-computer interaction interface, arranging sampling number is one in 16K/32K/64K/1M/2M/4M, usual dynamic indicator test selection 16K/32K/64K, Static State Index test selection 1M/2M/4M, the then dynamic performance index of analysis of running performance process analysis ADC chip to be measured; When Long-distance Control, start remote control device, arrange sampling number by the physical button of sensing cell and touch control screen, sensing controls the action of main flow PC, and with the WLAN of radio-cell or bluetooth or infrared ray transceiving wireless signal, realize the Long-distance Control of main flow PC.
The dynamic indicator that described step (1) ~ (5) can be analyzed has SNR, SFDR, SINAD, ENOB, THD, harmonic wave.
Embodiment 2: when specifically implementing, comprises the steps:
(1) High Speed High Precision ADC chip to be measured is loaded the high-speed and high-density SOCKET slot on DUT test carrier plate;
(2) external two-way digital power is opened, for data acquisition module and DUT test carrier plate provide 7.5 volts of power supplys;
(3) the first high performance signal source is used to provide clock signal for ADC chip to be measured, the clock signal that described first high performance signal source provides requires to possess extremely low phase noise, as far as possible for ADC chip to be measured provides desired clock source, in order to promote clock source quality further, the centre frequency of the first band pass filter of described first high performance signal source output terminal serial connection is 1 ~ 2MHz;
(4) analog input signal commutation circuit is set on DUT test carrier plate, analog channel is chosen as IMD index test input circuit, use the second high performance signal source and third high performance signals source to simulate double-tone input signal for ADC chip to be measured provides;
(5) main flow PC testing software is run, open human-computer interaction interface, arranging sampling number is one in 16K/32K/64K/1M/2M/4M, usual dynamic indicator test selection 16K/32K/64K, Static State Index test selection 1M/2M/4M, the then dynamic performance index of analysis of running performance process analysis ADC chip to be measured; When Long-distance Control, start remote control device, arrange sampling number by the physical button of sensing cell and touch control screen, sensing controls the action of main flow PC, and with the WLAN of radio-cell or bluetooth or infrared ray transceiving wireless signal, realize the Long-distance Control of main flow PC.
The dynamic indicator that described step (1) ~ (5) can be analyzed is IMD index.
Embodiment 3: when specifically implementing, comprises the steps:
(1) High Speed High Precision ADC chip to be measured is loaded the high-speed and high-density SOCKET slot on DUT test carrier plate;
(2) external two-way digital power is opened, for data acquisition module and DUT test carrier plate provide 7.5 volts of power supplys;
(3) the first high performance signal source is used to provide clock signal for ADC chip to be measured, the clock signal that described first high performance signal source provides requires to possess extremely low phase noise, as far as possible for ADC chip to be measured provides desired clock source, in order to promote clock source quality further, the centre frequency of the first band pass filter of described first high performance signal source output terminal serial connection is 1 ~ 2MHz;
(4) analog input signal commutation circuit is set on DUT test carrier plate, analog channel is chosen as the 3rd common dynamic indicator input SMA connector SMA3, the second high performance signal source is used to provide analog input signal for ADC chip to be measured, the analog input signal that described second high performance signal source provides requires to possess extremely low phase noise, such ability accurately tests out the performance index of ADC chip to be measured, and the performance not so tested out is likely just the index of input signal; In order to promote analog input signal quality, meet the needs of ADC chip index test to be measured to phase noise or shake, the centre frequency of the second band pass filter of described second high performance signal source output terminal serial connection is 1 ~ 2MHz, test ADC chip performance index at different frequencies, need the band pass filter corresponding to this frequency, therefore, high performance band-pass filter group is needed; Second differential transformers of described DUT test carrier plate is replaced by low-frequency transformer simultaneously;
(5) main flow PC testing software is run, open human-computer interaction interface, arranging sampling number is one in 16K/32K/64K/1M/2M/4M, usual dynamic indicator test selection 16K/32K/64K, Static State Index test selection 1M/2M/4M, the then dynamic performance index of analysis of running performance process analysis ADC chip to be measured; When Long-distance Control, start remote control device, arrange sampling number by the physical button of sensing cell and touch control screen, sensing controls the action of main flow PC, and with the WLAN of radio-cell or bluetooth or infrared ray transceiving wireless signal, realize the Long-distance Control of main flow PC.
The Static State Index that described step (1) ~ (5) can be analyzed has INL, DNL.
Embodiment 4: to carry out the testing performance index under high and low temperature condition to ADC chip to be measured, first use hot-fluid cover that the high density SOCKET slot (301) loading ADC chip to be measured is heated up (technical grade product high temperature 85 DEG C) or cooling (technical grade product low temperature is-40 DEG C), then adopt the step of embodiment 1, embodiment 2, embodiment 3 to test needing the index of test.
Embodiment 5: after completing one piece of ADC chip performance test, turn off two-way digital power, ADC chip is taken out from high-speed and high-density SOCKET slot, put into integrated circuit purpose-made pallet, and then adopt the step of embodiment 1, embodiment 2, embodiment 3, embodiment 4 to retest new ADC chip to be measured.
Finally it should be noted that, above embodiment is only in order to illustrate technical scheme of the present invention and non-limiting technical scheme, those of ordinary skill in the art is to be understood that, those are modified to technical scheme of the present invention or equivalent replacement, and do not depart from aim and the scope of the technical program, all should be encompassed in the middle of right of the present invention.
Claims (5)
1. the test macro for the small lot batch manufacture of High Speed High Precision ADC chip, it is characterized in that: described test macro is made up of main flow PC, data acquisition module, PCI-e module, high performance signal source, band-pass filter group, DUT test carrier plate, two-way digital power and far-end remote control device, described main flow PC is connected with data acquisition module, PCI-e module, high performance signal source respectively, and data acquisition module is connected by optical fiber with PCI-e module; Described high performance signal source has three, and its output signal is first through band-pass filter group, and band-pass filter group output signal is connected with DUT test carrier plate through radio frequency cable again; Described data acquisition module is connected with DUT test carrier plate, two-way digital power respectively, described data acquisition module is connected in mother baby plate mode by high-speed high-density electric connector socket with DUT test carrier plate, described two-way digital power is that data acquisition module is powered by supply socket, and is that DUT test carrier plate is powered by high-speed high-density electric connector socket; Described far-end remote control device comprises sensing cell and radio-cell, and sends wireless signal to main flow PC.
2. a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip according to claim 1, it is characterized in that: described PCI-e module is the PCI-e module based on fpga chip, data acquisition module is the data acquisition module based on fpga chip, the described PCI-e module based on fpga chip, the model of the fpga chip all adopted based on the data acquisition module of fpga chip is XC5VLX110T, based on the fpga chip of the PCI-e module of fpga chip, fpga chip based on the data acquisition module of fpga chip is all connected with Flash configuring chip, Flash data storage chip, DDR3 memory chip, clock driver circuit, optical interface module, jtag interface, LED light, reset circuit, AccessPort circuit, described clock driver circuit includes crystal oscillator, described reset circuit is made up of reset chip and reset button, and reset chip is connected with reset button, described AccessPort circuit is by serial port chip and nine cores point connector, and AccessPort circuit is connected with nine core point connectors by serial port chip, the described PCI-e module based on fpga chip also includes digital power module group and PCI-e bus golden finger, and PCI-e bus golden finger is connected with the fpga chip of the PCI-e module based on fpga chip, described digital power module group is connected to PCI-e bus golden finger, the described data acquisition module based on fpga chip also includes power circuit and high-speed high-density electric connector socket, and high-speed high-density electric connector socket is connected with the fpga chip of the data acquisition module based on fpga chip, described power electric route power socket and digital power module, the external two-way digital power of supply socket and being connected with digital power module.
3. a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip according to claim 1, it is characterized in that: described DUT test carrier plate comprises high density SOCKET slot, high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit, IMD index test input circuit, 3rd common dynamic indicator input SMA connector SMA3, LED light, analog power module, digital power module, described high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit is all connected with high density SOCKET slot, described IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3 are connected to analog input signal commutation circuit, described analog power module, digital power module are all connected with high-speed high-density electric connector socket.
4. a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip according to claim 3, it is characterized in that: by 5 constant virtues, described ADC chip reset circuit is shown in that dynamic indicator inputs SMA connector SMA5 and differential driving chip forms, and 5 constant virtues sees that dynamic indicator input SMA connector SMA5 is connected with differential driving chip; Described ADC chip clock circuit inputs SMA connector SMA4 by the 4th common dynamic indicator and the first differential transformers forms, and the 4th common dynamic indicator input SMA connector SMA4 is connected with the first differential transformers; Described analog input signal commutation circuit is made up of radio frequency converting switch and the second differential transformers, and radio frequency converting switch is connected with the second differential transformers; Described IMD index test input circuit inputs SMA connector SMA1 by the first common dynamic indicator, the second common dynamic indicator inputs SMA connector SMA2 and power combiner forms, first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 are all connected with power combiner, and power combiner is connected to radio frequency converting switch.
5. a kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip according to claim 1, it is characterized in that: described band-pass filter group comprises the first band pass filter, second band pass filter and the 3rd band pass filter, high performance signal source comprises the first high performance signal source, second high performance signal source and third high performance signals source, described first external first band pass filter in high performance signal source is as clock signal, second external second band pass filter in high performance signal source is as the first analog input signal, external 3rd band pass filter in third high performance signals source is as the second analog input signal, and clock signal, first analog input signal, second analog input signal all transfers to DUT test carrier plate.
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CN106054058A (en) * | 2016-04-28 | 2016-10-26 | 芯海科技(深圳)股份有限公司 | System and method capable of performing testing and temperature control on multiple Sigma-Delta ADC chips |
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