CN204166255U - 一种显示面板及显示装置 - Google Patents
一种显示面板及显示装置 Download PDFInfo
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Abstract
本实用新型属于显示技术领域,具体涉及一种显示面板及显示装置。一种显示面板,划分为多个亚像素区,所述显示面板包括对盒设置的彩膜基板和阵列基板以及设置于所述彩膜基板和所述阵列基板之间的液晶层,其中,所述阵列基板对应着每一所述亚像素区的区域内均设置有第一亚像素电极和第二亚像素电极,所述显示面板在对应着不同所述亚像素区的相邻所述第一亚像素电极和所述第二亚像素电极的间隙区设置有凸起物,所述凸起物的投影至少部分覆盖对应所述间隙区对应的区域。该显示面板通过在彩膜基板对应不同的亚像素区的相邻两个亚像素电极之间的间隙区的区域设置凸起物,从而减小间隙区液晶分子排列造成的像素暗区,提高显示质量。
Description
技术领域
本实用新型属于显示技术领域,具体涉及一种显示面板及显示装置。
背景技术
液晶显示技术广泛应用于电视、手机以及公共信息显示,液晶显示主要可以分为扭曲向列相(Twisted Nematic,简称TN)模式、垂直排列(Vertical-Aligned,简称VA)模式、面内开关(In-PlaneSwitching,简称IPS)模式。其中,垂直排列模式的液晶显示技术具有高对比度,容易获得宽视角,因此在大尺寸液晶显示装置产品方面得到了广泛应用。
随着显示技术的发展,目前垂直排列模式术出现了多畴显示技术。多畴显示技术即将一个亚像素区内的液晶在电场作用下的取向分成多个畴(Multi-domain),不同畴的液晶亮度在角度方面的差异互相补偿或平均,即可在一个亚像素区内实现多畴液晶排列,从而实现广视角化。但是,在现有技术中,由于不同亚像素区的相邻两个亚像素电极间隙区的液晶排列方向的差异,例如图1所示的8畴液晶排列,在相邻两个亚像素电极间隙区位置处的液晶排列出现位错,在显示效果上表现为暗区,图1中,152(i)为第i行栅线对应的第二亚像素电极,151(i+1)为第i+1行栅线对应的第一亚像素电极。
因此,设计一种在相邻两个亚像素区之间位置处的液晶排列不会出现位错,显示上无暗区的显示装置成为目前液晶显示技术领域的一个重点。
实用新型内容
本实用新型所要解决的技术问题是针对现有技术中存在的上述不足,提供一种显示面板及显示装置,通过在彩膜基板对应不同的亚像素区的相邻两个亚像素电极之间的间隙区的区域设置凸起物,从而减小间隙区液晶排列造成的像素暗区,提高显示质量。
解决本实用新型技术问题所采用的技术方案是该显示面板,划分为多个亚像素区,所述显示面板包括对盒设置的彩膜基板和阵列基板以及设置于所述彩膜基板和所述阵列基板之间的液晶层,所述阵列基板对应着每一所述亚像素区的区域内均设置有第一亚像素电极和第二亚像素电极,所述显示面板在对应着不同所述亚像素区的相邻所述第一亚像素电极和所述第二亚像素电极的间隙区设置有凸起物,所述凸起物的投影至少部分覆盖对应所述间隙区对应的区域。
优选的是,所述阵列基板还包括垂直交叉设置的多条栅线和多条数据线,每一所述亚像素区内设置的所述第一亚像素电极和所述第二亚像素电极沿所述数据线的延伸方向交替排列,所述栅线穿过所述亚像素区、且每一所述亚像素区内的第一亚像素电极和第二亚像素电极对应位于该所述栅线的两侧。
优选的是,所述第一亚像素电极和所述第二亚像素电极中均开设有狭缝,所述狭缝与所述栅线所成角度的绝对值范围为30°-60°。
优选的是,所述凸起物为体对称形状,所述凸起物设置于不同所述亚像素区的相邻所述第一亚像素电极和所述第二亚像素电极的所述间隙区的中心,且所述凸起物垂直于所述显示面板的投影的中心点与所述间隙区的中心点重合。
优选的是,所述彩膜基板包括衬底以及依次设置于所述衬底上方的彩膜层、保护层、公共电极层和取向层,所述凸起物设置于衬底上方,所述彩膜层覆盖所述凸起物;
或者,所述凸起物设置于所述彩膜层上方,所述保护层覆盖所述凸起物;
或者,所述凸起物设置于所述保护层上方,所述公共电极层覆盖所述凸起物;
或者,所述凸起物设置于所述公共电极层上方,所述取向层覆盖所述凸起物。
优选的是,所述凸起物的投影至少覆盖相邻的所述第一亚像素电极和所述第二亚像素电极之间的所述间隙区的中心宽度区域,相邻的所述第一亚像素电极和所述第二亚像素电极之间的所述间隙区的宽度范围为3μm-10μm,所述凸起物在所述衬底上的最大投影尺寸为15μm-30μm。
优选的是,所述凸起物的形状包括长方体、斜方体、立方体、圆柱体或半球体中的任一种。
优选的是,所述液晶层的厚度范围为3μm-6μm,所述凸起物的高度范围为1μm-2μm。
优选的是,所述凸起物采用感光树脂材料,并通过构图工艺形成。
一种显示装置,包括上述的显示面板。
本实用新型的有益效果是:该显示面板中,在形成8畴液晶显示的同时,通过在彩膜基板对应不同的亚像素区的相邻两个亚像素电极之间的间隙区的区域设置凸起物,从而改善相邻两个亚像素电极之间的间隙区位置处的液晶分子排列,可以减小间隙区液晶分子排列造成的像素暗区,提高显示质量。
附图说明
图1为现有技术中显示面板8畴液晶显示模式的液晶分子的排列示意图;
图2为本实用新型实施例1中显示面板的只包括阵列基板的平面图;
图3为图2中显示面板沿A1A2剖切线的剖面图;
图4为图2中显示面板沿B1B2剖切线的剖面图;
图5为图2中显示面板的电路原理图;
图6为图2中显示面板8畴液晶显示模式的液晶分子的排列示意图;
附图标记中:
1-阵列基板;
10-第一衬底;
11-栅线;11(i)-第i行栅线;11(i+1)-第i+1行栅线;
121-第一数据线;122-第二数据线;
131-第一公共电极线;132-第二公共电极线;
131(i)-第i行第一公共电极线;132(i)-第i行第二公共电极线;
131(i+1)-第i+1行第一公共电极线;132(i+1)-第i+1行第二公共电极线;
T1(i)-第i行第一薄膜晶体管;T2(i)-第i行第二薄膜晶体管;
T1(i+1)-第i+1行第一薄膜晶体管;T2(i+1)-第i+1行第二薄膜晶体管;
141-栅极;142-栅极绝缘层;143-有源层;144-源极;145-漏极;146-钝化层;
151-第一亚像素电极;152-第二亚像素电极;
151(i)-第i行第一亚像素电极;152(i)-第i行第二亚像素电极;
151(i+1)-第i+1行第一亚像素电极;152(i+1)-第i+1行第二亚像素电极;
2-彩膜基板;20-第二衬底;21-彩膜层;22-保护层;23-公共电极层;24-凸起物;
3-液晶层;30-液晶分子。
具体实施方式
为使本领域技术人员更好地理解本实用新型的技术方案,下面结合附图和具体实施方式对本实用新型显示面板及显示装置作进一步详细描述。
实施例1:
本实施例提供一种显示面板,该显示面板划分为多个亚像素区。如图2-图4所示,显示面板包括对盒设置的彩膜基板2和阵列基板1以及设置于彩膜基板2和阵列基板1之间的液晶层3,阵列基板1对应着每一亚像素区的区域内均设置有第一亚像素电极151和第二亚像素电极152;如图4所示,显示面板在对应着不同亚像素区的相邻的第一亚像素电极151和第二亚像素电极152的间隙区设置有凸起物24,凸起物24的投影至少部分覆盖对应间隙区对应的区域。该显示面板中,通过设置凸起物24,从而改善相邻两个亚像素电极之间的间隙区位置处的液晶分子30排列,从而减小间隙区液晶分子30的位错,减弱或消除像素暗区。
如图2所示,阵列基板1还包括垂直交叉设置的多条栅线11和多条数据线,每一亚像素区内设置的第一亚像素电极151和第二亚像素电极152沿数据线的延伸方向交替排列,栅线11穿过亚像素区、且每一亚像素区内的第一亚像素电极151和第二亚像素电极152对应位于该栅线11的两侧。其中,第一亚像素电极151和第二亚像素电极152中均开设有狭缝,如图2所示,狭缝与栅线11所成角度的绝对值范围为30°~60°。其中,定义狭缝与栅线11所成角度逆时针方向为正,反时针方向为负。
在图2中,与第i行栅线11(i)对应的亚像素电极包括第一亚像素电极151(i)和第二亚像素电极152(i);第一亚像素电极151(i)和第二亚像素电极152(i)分别位于第i行栅线11(i)两侧;与第i+1行栅线11(i+1)对应的亚像素电极包括第一亚像素电极151(i+1)和第二亚像素电极152(i),第一亚像素电极151(i+1)和第二亚像素电极152(i+1)分别位于第i+1行栅线11(i+1)的两侧。其中,作为示例,与第i行栅线11(i)对应的第二亚像素电极152(i)与第i+1行栅线11(i+1)对应的第一亚像素电极151(i+1)相邻,该两个亚像素电极即称为相邻的两个亚像素电极。
在本实施例的显示面板中,液晶分子30可以为负性液晶。位于同一亚像素区内的第一亚像素电极151和第二亚像素电极152使得对应亚像素区内的液晶分子30形成2n个具有不同取向的液晶畴,其中,n为自然数,且2≤n≤4。即多畴液晶显示可以为4畴液晶显示模式、8畴液晶显示模式甚至16畴液晶显示模式。在该多畴液晶显示模式的显示面板中,凸起物24设置于彩膜基板2中,凸起物24使得不同亚像素区的相邻第一亚像素电极和第二亚像素电极的间隙区的液晶分子30的排列得到改善,从而减小间隙区液晶分子30的位错,减弱或消除像素暗区。
作为一种示例,当n=3时,该显示面板为8畴液晶显示模式,每一亚像素区形成两个区域,该两个区域分别设置第一亚像素电极151和第二亚像素电极152,第一亚像素电极151和第二亚像素电极152使得该亚像素区中的液晶层3形成8个不同的取向,即形成8畴液晶显示效果。
在本实施例的显示面板中,凸起物24为体对称形状,凸起物24设置于不同亚像素区的相邻第一亚像素电极151和第二亚像素电极152的间隙区的中心,且凸起物24垂直于显示面板的投影的中心点与间隙区的中心点重合。其中,彩膜基板2包括第二衬底20以及依次设置于第二衬底20上方的彩膜层21、保护层22、公共电极层23和取向层(图3和图4中均未示出),凸起物24的投影至少覆盖相邻的第一亚像素电极151和第二亚像素电极152之间的间隙区的中心宽度区域,宽度区域即指该第一亚像素电极151和第二亚像素电极152沿数据线延伸方向形成的间隙区的尺寸,而中心宽度区域即指该宽度区域在对应该间隙区在栅线延伸方向(栅线延伸方向垂直于数据线延伸方向)的中间位置。例如,相邻的第一亚像素电极151和第二亚像素电极152之间的间隙区的宽度范围为3μm-10μm,凸起物24在第二衬底20上的最大投影尺寸为15μm-30μm。
该显示面板对凸起物24的位置不做限定,在实际显示面板的制备过程中可根据客户需求或显示精度进行灵活选择。例如:凸起物24可以设置于第二衬底20上方,彩膜层21覆盖凸起物24;或者,凸起物24设置于彩膜层21上方,保护层22覆盖凸起物24;或者,凸起物24设置于保护层22上方,公共电极层23覆盖凸起物24;或者,凸起物24设置于公共电极层23上方,取向层覆盖凸起物24。
同时应该理解的是,本实施例显示面板对凸起物24的形状不做限制,凸起物24的形状包括长方体、斜方体、立方体、圆柱体或半球体中的任一种。优选的是,凸起物24在第一衬底10上的投影形状为圆形,即上述凸起物24的形状至少具有一个圆形或弧形的部分,便于凸起物24的制备工艺。
为了保证凸起物24具有较佳的均衡液晶层3中的液晶分子30排列的效果,使得凸起物24的高度与液晶层3的厚度保持一定的关系,液晶层3的厚度越大,凸起物23的高度越高。例如,液晶层3的厚度范围为3μm-6μm,凸起物24的高度范围为1μm-2μm。
凸起物24可以采用感光树脂材料制备,并通过构图工艺形成,其中,构图工艺可以采用曝光、显影工艺,或,凸起物24还可以采用打印、喷墨等其他用于形成预定图形的工艺形成;可根据本实用新型中所形成的凸起物24结构选择相应的构图工艺。本实施例显示面板中的凸起物24的制备过程,具体为涂覆感光树脂材料,通过曝光、显影工艺,得到包括凸起物24的图形。
在本实施例的显示面板中,每一栅线11设置在同一亚像素区的第一亚像素电极151和第二亚像素电极152之间,并分别与第一薄膜晶体管T1的栅极和第二薄膜晶体管的栅极连接,使得第一亚像素电极151和第二亚像素电极152同时扫描驱动。具体的,与第i行栅线11(i)对应的第一亚像素电极151(i)通过与第i行栅线11(i)对应的第一薄膜晶体管T1(i)连接第一数据线121,与第i行栅线11(i)对应的第二亚像素电极152(i)通过与第i行栅线11(i)对应的第二薄膜晶体管T2(i)连接第二数据线122;与第i+1行栅线11(i+1)对应的第一亚像素电极151(i+1)通过与第i+1行栅线11(i+1)对应的第一薄膜晶体管T1(i+1)连接第一数据线121,与第i+1行栅线11(i+1)对应的第二亚像素电极152(i+1)通过与第i+1行栅线11(i+1)对应的第二薄膜晶体管T2(i+1)连接第二数据线122;第一数据线121上的数据信号Va(i)通过与第i行栅线11(i)对应的第一薄膜晶体管T1(i)写入与第i行栅线11(i)对应的第一亚像素电极151(i),第二数据线122上的数据信号Vb(i)通过与第i行栅线11(i)对应的第二薄膜晶体管T2(i)写入与第i行栅线11(i)对应的第二亚像素电极152(i);第i行栅线11(i)对应的第一亚像素电极上的电压Va(i)与第i行栅线11(i)对应的第二亚像素电极上的电压Vb(i)大小有一定差异,使第i行栅线11(i)对应的第一亚像素电极上的液晶分子的倾角不同于第i行栅线11(i)对应的第二亚像素电极上的液晶分子的倾角;在本实施例中,如图2所示,第i行栅线11(i)对应的第一亚像素电极上的液晶分子形成4畴排列,第i行栅线11(i)对应的第二亚像素电极上的液晶分子形成另一个倾角不同的4畴排列,第i行栅线11(i)对应的亚像素区总共形成了8畴的液晶排列;第一数据线121上的数据信号Va(i+1)通过与第i+1行栅线11(i+1)对应的第一薄膜晶体管T1(i+1)写入与第i+1行栅线11(i+1)对应的第一亚像素电极151(i+1),第二数据线122上的数据信号Vb(i+1)通过与第i+1行栅线11(i+1)对应的第二薄膜晶体管T2(i+1)写入与第i+1行栅线11(i+1)对应的第二亚像素电极152(i+1);同样地,可以在第i+1行栅线11(i+1)对应的亚像素区形成8畴的液晶排列。
以顶栅型薄膜晶体管为例,如图3所示,薄膜晶体管包括栅极141(连接图2中与栅极141同层形成的栅线11)、栅极141上方的栅极绝缘层142、栅极绝缘层142上方的有源层143、有源层143上方同层设置的源极144和漏极145、源极144和漏极145上方的钝化层146,钝化层146中开设有钝化层过孔(图3中,钝化层过孔中已填充亚像素电极,因此未具体标识),亚像素电极通过钝化层过孔与漏极145连接。
本实施例的显示面板中,阵列基板1还包括公共电极线(与栅极141同层形成),如图2所示,该公共电极线包括与第i行第一亚像素电极151(i)对应的第一公共电极线131(i)和与第i行第二亚像素电极152(i)对应的第二公共电极线132(i),第一公共电极线131(i)和第二公共电极线132(i)分别位于第i行栅线11(i)的两侧。其中,第一公共电极线131(i)包括朝向第一亚像素电极151(i)、且沿第一数据线121和第二数据线122方向延伸并与第一亚像素电极151(i)的投影至少部分重叠,第一公共电极线131(i)与第i行对应的第一亚像素电极151(i)形成存储电容Csta(i);第二公共电极线132(i)包括朝向第二亚像素电极152(i)、且沿第一数据线121和第二数据线122方向延伸并与第二亚像素电极152(i)的投影至少部分重叠,第二公共电极线132(i)与第i行对应的第二亚像素电极152(i)形成存储电容Cstb(i)。以此类推,与第i+1行第一亚像素电极151(i+1)对应的第一公共电极线131(i+1)与第i+1行对应的第一亚像素电极151(i+1)形成存储电容Csta(i+1),与第i+1行第二亚像素电极152(i+1)对应的公共电极线132(i+1)与第i+1行对应的第二亚像素电极152(i+1)形成存储电容Cstb(i+1)。
本实施例中显示面板的电路原理图如图5所示,当栅线141扫描时,第一数据线121上的数据信号Va(i)通过与第i行栅线11(i)对应的第一薄膜晶体管T1(i)写入存储电容Csta(i)、通过与第i+1行栅线11(i+1)对应的第一薄膜晶体管T1(i+1)写入存储电容Csta(i+1),第二数据线122上的数据信号Vb(i)通过与第i行栅线11(i)对应的第二薄膜晶体管T2(i)写入存储电容Cstb(i)、通过与第i+1行栅线11(i+1)对应的第二薄膜晶体管T2(i+1)写入存储电容Cstb(i+1),从而实现图像显示。
这里应该理解的是,在图5中,CLCa(i)和CLCb(i)分别为第i行第一亚像素电极151(i)和第i行第二亚像素电极152(i)与彩膜基板上的公共电极线形成的液晶电容,CLCa(i+1)和CLCb(i+1)为第i+1行第一亚像素电极151(i+1)和第二亚像素电极152(i+1)与彩膜基板上的公共电极线形成的液晶电容,液晶电容与存储电容相比要小很多,因此在讨论显示原理的时候,液晶电容通常可以忽略不计。
参考图1中彩膜基板上未设置凸起物24时,液晶分子30在相邻两个亚像素电极之间的间隙区位置处的排列示意图,将会出现较大的暗区(如图1中黑线包围的区域),会严重影响显示质量,并造成对亮度均匀度劣化、对比度下降、亮度降低;如图6所示,在彩膜基板上设置凸起物24后,液晶分子30在相邻两个亚像素电极之间的间隙区位置处的液晶分子排列得到改善,从而减小间隙区液晶分子30的位错,将减弱或消除像素暗区。
本实施例的显示面板中,通过在彩膜基板对应不同的亚像素区的相邻两个亚像素电极之间的间隙区的区域设置凸起物,从而改善相邻两个亚像素电极之间的间隙区位置处的液晶分子排列,可以减小间隙区液晶分子排列造成的像素暗区,提高显示质量。
实施例2:
本实施例提供一种显示装置,该显示装置包括实施例1中的显示面板。
该显示装置可以为:液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于该显示装置中采用的显示面板中,采用广视角的多畴液晶显示技术,并通过在彩膜基板对应不同的亚像素区的相邻两个亚像素电极之间的间隙区的区域设置凸起物,从而改善相邻两个亚像素电极之间的间隙区位置处的液晶分子排列,可以减小间隙区液晶分子排列造成的像素暗区,因此具有较佳的视角范围和较好的显示效果。
可以理解的是,以上实施方式仅仅是为了说明本实用新型的原理而采用的示例性实施方式,然而本实用新型并不局限于此。对于本领域内的普通技术人员而言,在不脱离本实用新型的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本实用新型的保护范围。
Claims (10)
1.一种显示面板,划分为多个亚像素区,所述显示面板包括对盒设置的彩膜基板和阵列基板以及设置于所述彩膜基板和所述阵列基板之间的液晶层,其特征在于,所述阵列基板对应着每一所述亚像素区的区域内均设置有第一亚像素电极和第二亚像素电极,所述显示面板在对应着不同所述亚像素区的相邻所述第一亚像素电极和所述第二亚像素电极的间隙区设置有凸起物,所述凸起物的投影至少部分覆盖对应所述间隙区对应的区域。
2.根据权利要求1所述的显示面板,其特征在于,所述阵列基板还包括垂直交叉设置的多条栅线和多条数据线,每一所述亚像素区内设置的所述第一亚像素电极和所述第二亚像素电极沿所述数据线的延伸方向交替排列,所述栅线穿过所述亚像素区、且每一所述亚像素区内的第一亚像素电极和第二亚像素电极对应位于该所述栅线的两侧。
3.根据权利要求2所述的显示面板,其特征在于,所述第一亚像素电极和所述第二亚像素电极中均开设有狭缝,所述狭缝与所述栅线所成角度的绝对值范围为30°-60°。
4.根据权利要求2所述的显示面板,其特征在于,所述凸起物为体对称形状,所述凸起物设置于不同所述亚像素区的相邻所述第一亚像素电极和所述第二亚像素电极的所述间隙区的中心,且所述凸起物垂直于所述显示面板的投影的中心点与所述间隙区的中心点重合。
5.根据权利要求4所述的显示面板,其特征在于,所述彩膜基板包括衬底以及依次设置于所述衬底上方的彩膜层、保护层、公共电极层和取向层,所述凸起物设置于衬底上方,所述彩膜层 覆盖所述凸起物;
或者,所述凸起物设置于所述彩膜层上方,所述保护层覆盖所述凸起物;
或者,所述凸起物设置于所述保护层上方,所述公共电极层覆盖所述凸起物;
或者,所述凸起物设置于所述公共电极层上方,所述取向层覆盖所述凸起物。
6.根据权利要求5所述的显示面板,其特征在于,所述凸起物的投影至少覆盖相邻的所述第一亚像素电极和所述第二亚像素电极之间的所述间隙区的中心宽度区域,相邻的所述第一亚像素电极和所述第二亚像素电极之间的所述间隙区的宽度范围为3μm-10μm,所述凸起物在所述衬底上的最大投影尺寸为15μm-30μm。
7.根据权利要求4所述的显示面板,其特征在于,所述凸起物的形状包括斜方体、立方体、圆柱体或半球体中的任一种。
8.根据权利要求4所述的显示面板,其特征在于,所述液晶层的厚度范围为3μm-6μm,所述凸起物的高度范围为1μm-2μm。
9.根据权利要求1-8任一项所述的显示面板,其特征在于,所述凸起物采用感光树脂材料,并通过构图工艺形成。
10.一种显示装置,其特征在于,包括权利要求1-9任一项所述的显示面板。
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US20160370616A1 (en) | 2016-12-22 |
US9958729B2 (en) | 2018-05-01 |
EP3211473A4 (en) | 2018-07-04 |
WO2016058349A1 (zh) | 2016-04-21 |
KR101814062B1 (ko) | 2018-01-02 |
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