CN204156832U - A kind of narrow pulse peak - Google Patents
A kind of narrow pulse peak Download PDFInfo
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- CN204156832U CN204156832U CN201420546017.2U CN201420546017U CN204156832U CN 204156832 U CN204156832 U CN 204156832U CN 201420546017 U CN201420546017 U CN 201420546017U CN 204156832 U CN204156832 U CN 204156832U
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Abstract
The utility model relates to a kind of narrow pulse peak.The block isolating circuit that input is made up of electric capacity C1 and resistance R1, by the DC component filtering of pulse input signal, comparison circuit N1 after block isolating circuit, the voltage of pulse input signal and holding capacitor C2 is compared, the output of comparison circuit N1 is passed through by resistance R2, the clamp circuit that diode V1 forms, be connected with field effect transistor Q1, and by field effect transistor Q1, holding capacitor C2 is charged, peakvalue's checking output connects a buffer N2, holding capacitor C2 and next stage circuit keep apart by buffer, pulse input signal is connected with high-speed comparator N3 by after block isolating circuit, the output of high-speed comparator N3 is connected with CPLD, CPLD carries out logical process to the output of high-speed comparator N3, the electric discharge of holding capacitor C2 is controlled.
Description
Technical field
The utility model relates to a kind of circuit nanosecond narrow-pulse laser signal being carried out to peak value maintenance.
Background technology
Laser guidance, laser ranging, laser communication etc. are all based on laser pulse signal detection, realize Signal transmissions, detection and process etc.In narrow-pulse laser Signal Measurement System, measured laser signal pulsewidth is nanosecond order, directly uses high-speed AD acquisition circuit to be difficult to the amplitude capturing burst pulse, therefore needs to design the peak holding circuit being applicable to narrow-pulse laser signal.The effect of this circuit is that the narrow-pulse laser signal that laser detector exports is carried out to broadening and keeps a period of time, to adopt conventional low-speed a/d converter to carry out acquisition process.Non-linear comparatively large, dynamic range and the passband of traditional voltage-type peak holding circuit are less, and are not suitable for processing fast signal; And adopt transconductance type peak holding circuit, there is the features such as Circuit responce speed is fast, dynamic range is large, be suitable for process fast narrow pulse signal.And the peak holding circuit nonlinearity erron be made up of general transconductance type amplifier, diode and electric capacity is large, be difficult to meet the requirement of high-precision application scenario.
Summary of the invention
In order to overcome the shortcoming of prior art, the utility model provides a kind of narrow pulse peak.The maintenance of narrow-pulse laser signal peak can be realized, can the pulse that pulsewidth is nanosecond be detected.
The technical scheme in the invention for solving the technical problem is: the block isolating circuit that input is made up of electric capacity C1 and resistance R1, by the DC component filtering of pulse input signal, comparison circuit N1 after block isolating circuit, the voltage of pulse input signal and holding capacitor C2 is compared, the output of comparison circuit N1 is passed through by resistance R2, the clamp circuit that diode V1 forms, be connected with field effect transistor Q1, and by field effect transistor Q1, holding capacitor C2 is charged, peakvalue's checking output connects a buffer N2, holding capacitor C2 and next stage circuit keep apart by buffer, pulse input signal is connected with high-speed comparator N3 by after block isolating circuit, the output of high-speed comparator N3 is connected with CPLD, CPLD carries out logical process to the output of high-speed comparator N3, the electric discharge of holding capacitor C2 is controlled.
The utility model has following advantages: the logic control that 1) resets adopts CPLD, has and simplifies little, the different control mode of hardware designs difficulty, system bulk by software simulating.Amendment is convenient.Improve the integrated level of circuit.2) circuit structure simple, keep that precision is high, stability is strong, the linearity is high and the feature such as cost is low.
Accompanying drawing explanation
Fig. 1 is the utility model circuit theory diagrams.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further illustrated.
As shown in Figure 1, when narrow pulse signal arrives, the block isolating circuit of pulse input signal Ui by being made up of electric capacity C1, resistance R1, by the DC component filtering of pulse input signal Ui, then be input in the reverse input end of comparison circuit N1, the positive input of comparison circuit N1 is connected with one end of holding capacitor C2, and the output of comparison circuit N1 is the difference △ U of positive input and reverse input end.The clamp circuit of △ U through being made up of resistance R2, diode V1, be connected with the grid of field effect transistor Q1, the drain electrode of field effect transistor Q1 is connected with holding capacitor C2, and to its charging, charging current i is directly proportional to △ U.When the difference △ U that the output of comparison circuit N1 is positive input and reverse input end is 0V, charging current is also 0.Now, the voltage U c=Ui of holding capacitor C2, Uc are exported by buffer N2, the output Uo=Uc of buffer N2.Described comparison circuit N1 is ultrahigh speed difference single ended line receiver.Described field effect transistor Q1 is P-channel enhancement type field effect transistor.
Described comparison circuit N1 is ultrahigh speed difference single ended line receiver.
Described field effect transistor Q1 is P-channel enhancement type field effect transistor.
When pulse input signal Ui is less than Uc, comparison circuit N1 exports forward voltage, and Q1 stops holding capacitor C2 charging, and Uc remains unchanged until next pulse arrives.The peak value that circuit completes pulse input signal Ui keeps.
The reset of holding capacitor is controlled by switch S 1.Paired pulses input correct peak value maintenance could be carried out after the reset of holding capacitor.The control of switch S 1 is completed by CPLD (CPLD).
Pulse input signal Ui enters the positive input of high-speed comparator N3 after passing through the block isolating circuit be made up of C1, R1, after comparing with the threshold voltage of reverse input end, and N3 output logic signal Q1, the input pin of Q2 to CPLD.CPLD, to logical signal Q1, Q2 process, realizes the logic control to switch S1.
Claims (3)
1. a narrow pulse peak, it is characterized in that: the block isolating circuit that input is made up of electric capacity (C1) and resistance (R1), by the DC component filtering of pulse input signal, comparison circuit (N1) after block isolating circuit, the voltage of pulse input signal and holding capacitor (C2) is compared, the output of comparison circuit (N1) is passed through by resistance (R2), the clamp circuit that diode (V1) forms, be connected with field effect transistor (Q1), and by field effect transistor (Q1), holding capacitor (C2) is charged, peakvalue's checking output connects a buffer (N2), holding capacitor (C2) and next stage circuit are kept apart by buffer, pulse input signal is connected with high-speed comparator (N3) by after block isolating circuit, the output of high-speed comparator (N3) is connected with CPLD, logical process is carried out in the output of CPLD to high-speed comparator (N3), the electric discharge of holding capacitor (C2) is controlled.
2. narrow pulse peak according to claim 1, is characterized in that: described comparison circuit (N1) is ultrahigh speed difference single ended line receiver.
3. narrow pulse peak according to claim 1, is characterized in that: described field effect transistor (Q1) is P-channel enhancement type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420546017.2U CN204156832U (en) | 2014-09-22 | 2014-09-22 | A kind of narrow pulse peak |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420546017.2U CN204156832U (en) | 2014-09-22 | 2014-09-22 | A kind of narrow pulse peak |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204156832U true CN204156832U (en) | 2015-02-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420546017.2U Active CN204156832U (en) | 2014-09-22 | 2014-09-22 | A kind of narrow pulse peak |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204156832U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110460322A (en) * | 2019-08-29 | 2019-11-15 | 华南理工大学 | A kind of narrow pulse peak sampling hold circuit and its control method |
| CN114039579A (en) * | 2021-11-11 | 2022-02-11 | 北京理工大学 | Narrow pulse eliminating circuit for driving signal of power electronic device |
| CN114325040A (en) * | 2021-12-06 | 2022-04-12 | 东莞声索电子有限公司 | Pulse voltage detection circuit |
-
2014
- 2014-09-22 CN CN201420546017.2U patent/CN204156832U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110460322A (en) * | 2019-08-29 | 2019-11-15 | 华南理工大学 | A kind of narrow pulse peak sampling hold circuit and its control method |
| CN110460322B (en) * | 2019-08-29 | 2023-09-26 | 华南理工大学 | Narrow pulse peak value sampling hold circuit and control method thereof |
| CN114039579A (en) * | 2021-11-11 | 2022-02-11 | 北京理工大学 | Narrow pulse eliminating circuit for driving signal of power electronic device |
| CN114325040A (en) * | 2021-12-06 | 2022-04-12 | 东莞声索电子有限公司 | Pulse voltage detection circuit |
| CN114325040B (en) * | 2021-12-06 | 2024-06-04 | 东莞声索电子有限公司 | Pulse voltage detection circuit |
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