CN204155102U

CN204155102U - A kind of high precision restructural digital delay line

Info

Publication number: CN204155102U
Application number: CN201420651374.5U
Authority: CN
Inventors: 廖宏宾; 付建群
Original assignee: XI'AN FARADAY ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: XI'AN FARADAY ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2014-11-04
Filing date: 2014-11-04
Publication date: 2015-02-11
Anticipated expiration: 2024-11-04

Abstract

A kind of high precision restructural digital delay line, include A/D converter, A/D converter output terminal is connected with delay unit input end, and delay unit input end is connected with control module output terminal, and delay unit output terminal is connected with D/A converter; The simulating signal of time delay that needs of input is converted to digital signal by A/D converter, and digital signal is exported to the delay unit in FPGA, and delay unit arranges delay time according to the instruction of control module, and the digital signal after time delay is exported to D/A converter; Have total delay time long, extend that precision is high, the feature of restructural, compact conformation and highly versatile.

Description

A kind of high precision restructural digital delay line

Technical field

The utility model relates to a kind of digital delay line, particularly a kind of high precision restructural digital delay line.

Background technology

Digital delay line is used for the element of electric signal time delay a period of time or device.Digital delay line is widely used in each electron-like and communication system, as radar target echo signal simulation system, phased array radar system, time figure system and synchronous communication system etc.In general, delay cell is divided into special and general two large classes.Special lag line is as AD9501, and he adopts analog device to realize, and precision can reach 10 ps levels, but its dynamic range is less than 10us.Generally, there is total delay time short in dedicated delay line, postponing step-length can not adjust, and controls inflexible defect.General delay cell generally adopts programmable logic device (PLD) to realize, and has dynamic range large, the reliable advantage of simplicity of design, but it postpones the impact that precision is but subject to devices function clock, generally in ns rank.In radar target signal imitation system, phased array radar system system, require that the total delay time of delay line is much larger than 10us, and require that delay stepsize can accurate adjustment.

Summary of the invention

In order to overcome above-mentioned the deficiencies in the prior art, the purpose of this utility model is to provide a kind of high precision restructural digital delay line, have total delay time long, extend that precision is high, the feature of restructural, compact conformation and highly versatile.

To achieve these goals, the technical solution adopted in the utility model is: a kind of high precision restructural digital delay line, include A/D converter, the output terminal of A/D converter is connected with the input end of delay unit, the input end of delay unit is connected with the output terminal of control module, and the output terminal of delay unit is connected with D/A converter.

The utility model has the following advantages: owing to have employed High Performance FPGA, system can realize man-machine interaction, automatically can detect the key parameter of input simulating signal, the parameter of needs can be shown simultaneously, and carry out fault pre-diagnosing and fault real-time diagnosis according to these parameters.System changes the scheme of conventional digital delay line, adopts High Performance FPGA and two-forty, high-resolution AD and DA device, solves dedicated delay line generally, there is total delay time short, and postponing step-length can not adjust, and controls inflexible defect.Having 1) total delay time can reach more than 100ms; 2) high precision: postpone step-length precision at 5ns, the highest 380 MHz of frequency input signal, input signal precision is 14bit; 3) restructural: the feature of reconstruction delay time under 5ns postpones step-length precision.This product has the feature of compact conformation, highly versatile simultaneously.

Accompanying drawing explanation

Fig. 1 is the utility model theory diagram.

Embodiment

Below in conjunction with accompanying drawing, principle of work of the present utility model is described in further detail.

See Fig. 1, a kind of high precision restructural digital delay line, include A/D converter 3, A/D converter 3 output terminal is connected with delay unit 2 input end, delay unit 2 input end is connected with control module 1 output terminal, and delay unit 2 output terminal is connected with D/A converter 4.

This digital delay wire system is based on two-forty, high-resolution AD and DA device; Adopt High Performance FPGA extensive, at a high speed.Ultimate principle is as shown in Fig. 1.

Described control module be responsible for delay time control and control information mutual; Delay unit is responsible for carrying out accurate time delay to data; The time delay simulating signal that needs of input is converted to digital signal by A/D converter; Digital signal after time delay is converted to analog signal output by D/A converter.

principle of work of the present utility model is:

The simulating signal of time delay that needs of input is converted to digital signal by A/D converter, and delay unit digital signal exported in FPGA, delay unit arranges delay time according to the instruction of control module, digital signal after time delay is exported to D/A converter, thus completes the functional requirement will exported after the simulating signal time delay a period of time needing time delay.

Claims

1. a high precision restructural digital delay line, it is characterized in that, include A/D converter (3), the output terminal of A/D converter (3) is connected with the input end of delay unit (2), the input end of delay unit (2) is connected with the output terminal of control module (1), and the output terminal of delay unit (2) is connected with D/A converter (4).