CN204119195U - A kind of anti-interference reset circuit - Google Patents
A kind of anti-interference reset circuit Download PDFInfo
- Publication number
- CN204119195U CN204119195U CN201420641884.4U CN201420641884U CN204119195U CN 204119195 U CN204119195 U CN 204119195U CN 201420641884 U CN201420641884 U CN 201420641884U CN 204119195 U CN204119195 U CN 204119195U
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- inverter
- circuit
- pmos
- input
- reset circuit
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Abstract
The utility model discloses a kind of anti-interference reset circuit, comprise source electrode be connected with power supply, drain to be connected with the capacitor of one end ground connection, the PMOS of grounded-grid and inverter circuit, described PMOS is connected with the input of inverter circuit with the tie point of capacitor, the output of described inverter circuit connects external circuit, described inverter circuit comprises the first inverter, the second inverter and the 3rd inverter that are sequentially connected in series, and the power input of described first inverter and the second inverter is connected to the drain electrode of described PMOS.The utility model structure is simple, and not needing increases components and parts, does not increase chip area and cost, and improves the jamproof ability of reset circuit.
Description
Technical field
The utility model relates to integrated circuit fields, is specifically related to a kind of reset circuit.
Background technology
In existing integrated circuit (IC) design technology, according to the different application environment of chip, can propose different anti-interference problems, as the circuit with large driving, driving can have an impact to power supply.Reset circuit ensures that chip can the circuit of normal initialization, and as shown in Figure 1, inverter is by Power supply for general typical circuit.Not suddenly change principle according to the voltage of electric capacity C, by PMOS transistor, electric capacity C is charged, can reset function be realized.But, if supply voltage is unstable, the mains ripple of the first inverter, the second inverter, the 3rd inverter is larger, or wave time is longer, because PMOS transistor is conducting, and in order to ensure long enough resetting time, PMOS is generally designed to weak pipe, like this, the input change of inverter circuit is comparatively slow, asynchronous with the power supply of inverter, internal circuit can be made like this to produce reset, causing the function of chip chaotic, in order to improve the antijamming capability of circuit to power supply, being badly in need of a kind of anti-interference reset circuit.
Summary of the invention
Goal of the invention of the present utility model is to provide a kind of anti-interference reset circuit, solves because of PMOS conducting in prior art, in power-supply fluctuation situation, causes internal circuit to reset by mistake and causes the problem of chip functions disorder.
To achieve the above object of the invention, the technical solution adopted in the utility model is: a kind of anti-interference reset circuit, comprise source electrode to be connected with power supply, drain electrode is connected with the capacitor of one end ground connection, the PMOS of grounded-grid and inverter circuit, described PMOS is connected with the input of inverter circuit with the tie point of capacitor, the output of described inverter circuit connects external circuit, described inverter circuit comprises the first inverter be sequentially connected in series, second inverter and the 3rd inverter, the power input of described first inverter and the second inverter is connected to the drain electrode of described PMOS.
In technique scheme, described being connected in series refers to, the output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the input of the 3rd inverter, by the input of the first inverter as the input of whole inverter circuit, the output of the 3rd inverter is as the output of whole inverter circuit.
Because technique scheme is used, the utility model compared with prior art has following advantages:
1. utilize the characteristic that capacitance voltage does not suddenly change, directly by the control of capacitance voltage, improve the jamproof ability of reset circuit;
2. the utility model structure is simple, and not needing increases components and parts, does not increase chip area and cost.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of the reset circuit of prior art;
Fig. 2 is the circuit structure diagram of anti-interference reset circuit described in the utility model;
Fig. 3 is the application schematic diagram of embodiment 1.
Wherein: 1, power supply; 2, PMOS; 3, capacitor; 4, the first inverter; 5, the second inverter; 6, the 3rd inverter.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described:
Embodiment one: as shown in Figure 2, for the circuit structure diagram of the anti-interference reset circuit of the present embodiment, when powering on, electric capacity 3 voltage is " 0 ", the input of Nverter circuit is " 0 ", because the power supply of the first inverter 4 and the second inverter 5 is inverter circuit input voltage over the ground, therefore, through two inverters, the output of the second inverter 5 is " 0 ", and circuit is in reset mode, after electric charge on electric capacity 3 is full of, the output of the second inverter 5 is " 1 ", and reset and terminate, reseting procedure normally completes.
When the voltage on power supply 1 has interference, because on electric capacity 3, voltage does not suddenly change, namely inverter circuit input current potential does not suddenly change, power supply 1 disturbs all not to be affected the input of the supply power voltage on the first inverter 4 and the second inverter 5 and the first inverter 4, reset output signal also would not have the generation of misoperation, reaches the object improving antijamming capability.
As shown in Figure 3, it is one of application scheme of the present embodiment, in a LED drive chip, Vdd is the power supply of chip, LDO provides stabilized voltage power supply for logical circuit, reset circuit provides reset signal for logical circuit, and the output signal that logical circuit produces, through LEVEL SHIFT circuit, controls the LED circuit of drive circuit driving chip outside.If the load that LED drives is larger, larger impact will be produced to power supply, but by LDO, internal circuit ensures that power supply is stable, adopt the reset circuit described in the present embodiment can guarantee the normal initialization of chip, whole system antijamming capability under the prerequisite not increasing cost significantly improves, and ensures that chip can stably work.
Claims (1)
1. an anti-interference reset circuit, comprise source electrode to be connected with power supply (1), drain electrode is connected with the capacitor (3) of one end ground connection, the PMOS (2) of grounded-grid and inverter circuit, described PMOS (2) is connected with the input of described inverter circuit with the tie point of capacitor (3), the output of described inverter circuit connects external circuit, described inverter circuit comprises the first inverter (4) be sequentially connected in series, second inverter (5) and the 3rd inverter (6), it is characterized in that: the power input of described first inverter (4) and the second inverter (5) is connected to the drain electrode of described PMOS (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420641884.4U CN204119195U (en) | 2014-10-31 | 2014-10-31 | A kind of anti-interference reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420641884.4U CN204119195U (en) | 2014-10-31 | 2014-10-31 | A kind of anti-interference reset circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204119195U true CN204119195U (en) | 2015-01-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420641884.4U Expired - Fee Related CN204119195U (en) | 2014-10-31 | 2014-10-31 | A kind of anti-interference reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204119195U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104283534A (en) * | 2014-10-31 | 2015-01-14 | 苏州大学 | Anti-interference reset circuit |
| CN115765699A (en) * | 2022-12-16 | 2023-03-07 | 上海功成半导体科技有限公司 | Reset circuit, reset method, reset switch circuit and electronic equipment |
-
2014
- 2014-10-31 CN CN201420641884.4U patent/CN204119195U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104283534A (en) * | 2014-10-31 | 2015-01-14 | 苏州大学 | Anti-interference reset circuit |
| CN115765699A (en) * | 2022-12-16 | 2023-03-07 | 上海功成半导体科技有限公司 | Reset circuit, reset method, reset switch circuit and electronic equipment |
| CN115765699B (en) * | 2022-12-16 | 2023-11-17 | 上海功成半导体科技有限公司 | Reset circuit, reset method, reset switch circuit and electronic equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150121 Termination date: 20171031 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |