CN204104030U - Support the VGA display module structure of PAL-D video superimpose - Google Patents
Support the VGA display module structure of PAL-D video superimpose Download PDFInfo
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- CN204104030U CN204104030U CN201420580196.1U CN201420580196U CN204104030U CN 204104030 U CN204104030 U CN 204104030U CN 201420580196 U CN201420580196 U CN 201420580196U CN 204104030 U CN204104030 U CN 204104030U
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Abstract
Support a VGA display module structure for PAL-D video superimpose, above-mentioned VGA display module structure comprises: VGA input interface, CVBS input interface, video decoding image chip superposed, fpga chip, video coding chip and VGA output interface; VGA input interface connects with CVBS input and is connected with video decoding image chip superposed simultaneously, and video decoding image chip superposed, fpga chip, video coding chip and VGA output interface are linked in sequence successively.VGA display is input to video decoding image chip superposed by VGA input interface, PAL-D standard signal by CVBS input interface, and signal, successively through fpga chip, video coding chip, is finally exported by VGA output interface.The utility model solves the problem that computer VGA display frame and CVBS interface PAL-D Signal averaging show, and structure is simple, is convenient to practical application.
Description
Technical field
The utility model relates to the technical field of video display, is a kind of VGA display module structure supporting PAL-D video superimpose specifically.
Background technology
Along with the development of science and technology, video superimpose technology has been applied very extensive, the picture-in-picture in TV programme, and in supermarket, many pictures watch-dog has all been applied to video superimpose technology, has enriched the various display demands of people.But current this superposition is all the superposition between software layer last time substantially, and the direct superposition of display interface is little.CVBS interface equipment is ubiquity in video acquisition and display field, and what China CVBS interface equipment adopted is PAL-D standard signal.Computer there is no such interface, use PAL-D standard device just must design a equipment increasing a CVBS interface Overlapping display in computer outside on computers, therefore support that the design of the VGA display module of PAL-D video overlapping function ground is very necessary.
Support that the equipment of the VGA display module of PAL-D video overlapping function is little on the market, the product of main flow is that PAL-D turns VGA display converter.It is that incoming video signal directly links display device through this transducer that this type of main flow PAL-D turns VGA display converter main feature, and the camera that such as PAL-D video standard signal exports directly receives VGA display display information through this transducer.Chinese patent " multi-cannel OSD video superposition controller " (application number 200810054007.6) discloses a kind of multi-channel video overlaying scheme.The program mainly teaches and is added in multichannel non-synchronous video signal by monochromatic for any User Defined character or figure based on bitmap mode, in this design, character or figure are by User Defined, superposition needs extra memory to come store character or figure, be only applicable to the superposition of multichannel monochrome video, but be not suitable for the PAL-D video superimpose display mode of computer USB interface.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of VGA display module structure supporting PAL-D video superimpose.
The technical scheme that the utility model is taked for the technical problem existed in solution known technology is:
The VGA display module structure of support PAL-D video superimpose of the present utility model, comprising: VGA input interface, CVBS input interface, video decoding image chip superposed, FPGA chip, video coding chip and VGA output interface; VGA input interface connects with CVBS input and is connected with video decoding image chip superposed simultaneously, and video decoding image chip superposed, FPGA chip, video coding chip and VGA output interface are linked in sequence successively.
The utility model can also adopt following technical measures:
Described VGA input interface connects with computer VGA display interface; VGA input interface is the public mouth socket of DB15.
Described CVBS input interface connects with CVBS output interface; CVBS input interface is the female mouth socket of RCA JACK.
Video decode and the image digitazation chip of described video decoding image chip superposed to be model be ADV7181C.
The chip of described FPGA chip to be model be EP3C5E144I7N.
The VGA video coding chip of described video coding chip to be model be ADV7125KST140.
Described VGA output interface connects with VGA display display interface; VGA output interface is the female mouth socket of DB15.
The advantage that the utility model has and good effect are:
In the VGA display module structure of support PAL-D video superimpose of the present utility model, VGA display is input to video decoding image chip superposed by VGA input interface, and PAL-D standard signal is input to video decoding image chip superposed by CVBS input interface, signal through video decoding image chip superposed, FPGA chip, video coding chip and VGA output interface, is finally exported by VGA output interface successively.The utility model solves the problem that computer VGA display frame and CVBS interface PAL-D Signal averaging show, plug and play, without the need to mounting software driver, has flexible operation, structure is simple, be convenient to the advantages such as practical application.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the VGA display module structure of support PAL-D video superimpose of the present utility model;
Fig. 2 is the circuit pin schematic diagram of video decoding image chip superposed in the VGA display module structure of support PAL-D video superimpose of the present utility model;
Fig. 3 is the circuit pin schematic diagram of video coding chip in the VGA display module structure of support PAL-D video superimpose of the present utility model.
Embodiment
Referring to drawings and Examples, the utility model is described in detail.
Fig. 1 is the schematic diagram of the VGA display module structure of support PAL-D video superimpose of the present utility model; Fig. 2 is the circuit pin schematic diagram of video decoding image chip superposed in the VGA display module structure of support PAL-D video superimpose of the present utility model; Fig. 3 is the circuit pin schematic diagram of video coding chip in the VGA display module structure of support PAL-D video superimpose of the present utility model.
As shown in Figure 1, the VGA display module structure of support PAL-D video superimpose of the present utility model, comprising: VGA input interface, CVBS input interface, video decoding image chip superposed, FPGA chip, video coding chip and VGA output interface; VGA input interface connects with CVBS input and is connected with video decoding image chip superposed simultaneously, and video decoding image chip superposed, FPGA chip, video coding chip and VGA output interface are linked in sequence successively.
VGA input interface is connected with video decoding image chip superposed, CVBS input interface is connected with video decoding image chip superposed, video decoding image chip superposed is connected with FPGA chip, and FPGA chip is connected with video coding chip, and video coding chip is connected with VGA output interface.
VGA input interface connects with computer VGA display interface, and the VGA input interface in embodiment adopts the public mouth socket of conventional DB15, and in the course of the work, VGA input interface is for connecting the female mouth socket of DB15 of the VGA display of the equipment such as computer.
CVBS input interface is used for connecting with the CVBS output interface of display device, CVBS input interface in embodiment adopts conventional designation to be the female mouth socket of RCA JACK, in the course of the work, the RCA JACK public mouth socket of CVBS input interface for connecting CVBS interface equipment, to access PAL-D signal.
Video decoding image chip superposed is used for VGA, PAL-D signal decoding, digitized processing and video superimpose.As shown in Figure 2, video decoding image chip superposed employing Ya De promise company (Analog Devices) model of embodiment is video decode and the image digitazation chip of ADV7181C, superpose in the course of work at PAL-D, video decoding image chip superposed is responsible for VGA and PAL-D to decode, vision signal superposes, and digitized processing becomes the vision signal of YUV standard.
FPGA chip is used for the vision signal of YUV standard is carried out to video format conversion and exported.FPGA chip employing model in embodiment is the embedded chip of the EP3C5E144I7N of altera corp, and in the PAL-D Overlapping display course of work, FPGA chip is responsible for 24 the TFT signals vision signal of YUV standard being converted to standard.
It is VGA display translation signal that video coding chip is used for 24 of standard TFT Signal codings.As shown in Figure 3, the model of video coding chip employing Ya De promise company (Analog Devices) in embodiment is the VGA video coding chip of ADV7125KST140, in the course of the work, video coding chip is responsible for 24 TFT Signal codings being VGA display and passing out to VGA output interface.
VGA output interface is used for connecting with VGA display display interface.The VGA output interface of embodiment adopts the female mouth socket of conventional DB15, the DB15 public mouth socket of VGA output interface 6 for connecting VGA display.
The utility model in use, PAL-D signal is input to video decoding image chip superposed through CVBS input interface, VGA display through VGA display interface simultaneously, converts the digital signal of the YUV standard of superposition through video decode, imaging importing, image digitazation process to.YUV digital signal after superposition conversion is input to fpga chip, carries out 24 TFT Signal form translates.The TFT signal changed is input to video coding chip and encodes, and the VGA signal converting standard to send VGA output interface, on VGA display, finally show the video image of PAL-D and VGA superposition.
Embodiment experiment shows, the VGA display module structure of support PAL-D video superimpose of the present utility model, can by camera PAL-D format video and computer VGA display video Overlapping display, and button can control to superpose on off state.When opening superposition, display camera as prospect, the superimposed image of VGA video as a setting; When closing superposition, only outputting VGA video image.
The above, it is only preferred embodiment of the present utility model, not any pro forma restriction is done to the utility model, although the utility model with preferred embodiment openly as above, but, and be not used to limit the utility model, any those skilled in the art, do not departing within the scope of technical solutions of the utility model, certainly the technology contents of announcement can be utilized to make a little change or modification, become the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solutions of the utility model, according to any simple modification that technical spirit of the present utility model is done above embodiment, equivalent variations and modification, all belong in the scope of technical solutions of the utility model.
Claims (7)
1. support a VGA display module structure for PAL-D video superimpose, it is characterized in that: above-mentioned VGA display module structure comprises: VGA input interface, CVBS input interface, video decoding image chip superposed, FPGA chip, video coding chip and VGA output interface; VGA input interface connects with CVBS input and is connected with video decoding image chip superposed simultaneously, and video decoding image chip superposed, FPGA chip, video coding chip and VGA output interface are linked in sequence successively.
2. the VGA display module structure of support PAL-D video superimpose according to claim 1, is characterized in that: VGA input interface connects with computer VGA display interface; VGA input interface is the public mouth socket of DB15.
3. the VGA display module structure of support PAL-D video superimpose according to claim 1 and 2, is characterized in that: CVBS input interface connects with CVBS output interface; CVBS input interface is the female mouth socket of RCA JACK.
4. the VGA display module structure of support PAL-D video superimpose according to claim 3, is characterized in that: video decode and the image digitazation chip of video decoding image chip superposed to be model be ADV7181C.
5. the VGA display module structure of support PAL-D video superimpose according to claim 4, is characterized in that: the chip of FPGA chip to be model be EP3C5E144I7N.
6. the VGA display module structure of support PAL-D video superimpose according to claim 5, is characterized in that: the VGA video coding chip of video coding chip to be model be ADV7125KST140.
7. the VGA display module structure of the support PAL-D video superimpose according to claim 1 or 6, is characterized in that: VGA output interface connects with VGA display display interface; VGA output interface is the female mouth socket of DB15.
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| CN201420580196.1U CN204104030U (en) | 2014-10-09 | 2014-10-09 | Support the VGA display module structure of PAL-D video superimpose |
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| CN201420580196.1U CN204104030U (en) | 2014-10-09 | 2014-10-09 | Support the VGA display module structure of PAL-D video superimpose |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105704408A (en) * | 2016-02-04 | 2016-06-22 | 天津市英贝特航天科技有限公司 | Real time superposition controller and method for asynchronous images |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105704408A (en) * | 2016-02-04 | 2016-06-22 | 天津市英贝特航天科技有限公司 | Real time superposition controller and method for asynchronous images |
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