CN204089768U

CN204089768U - RS485 automatic reversing circuit

Info

Publication number: CN204089768U
Application number: CN201420493239.2U
Authority: CN
Inventors: 戴林; 宁盛创
Original assignee: Tianjin Tiandy Digital Technology Co Ltd
Current assignee: Tianjin Tiandy Digital Technology Co Ltd
Priority date: 2014-08-29
Filing date: 2014-08-29
Publication date: 2015-01-07
Anticipated expiration: 2024-08-29

Abstract

The utility model discloses a kind of RS485 automatic reversing circuit, comprise 485 transceiving chips and commutating circuit, and described commutating circuit comprises NAND gate circuit and delay circuit, NAND gate circuit comprises three NAND gate, and delay circuit forms with a capacitances in series by after diode and a resistor coupled in parallel again; Two inputs of the first NAND gate are connected with the 4th pin of 485 transceiving chips, and are connected to the TXD end of processor chips UART universal serial bus, the first NAND gate and delay circuit; Second NAND gate is connected with delay circuit, and another input is connected with the 3rd NAND gate, and is connected to the second pin and the 3rd pin of 485 transceiving chips.The utility model saves the port resource of controller, improves the compatibility of software simultaneously and reduces the development difficulty of embedded program under an operating system, improves transmission range and the antijamming capability of RS485 greatly.

Description

RS485 automatic reversing circuit

Technical field

The utility model relates to electric digital data processing field, particularly relates to a kind of RS485 automatic reversing circuit.

Background technology

RS-485 bus, as a kind of electrical code of multiple spot differential data transmission, has become one of standard communication interface that industry is most widely used.This communication interface allows to carry out multiple spot two-way communication on simple a pair twisted-pair feeder, and the noise inhibiting ability that it has, message transmission rate, cable length and reliability are that other standards is incomparable.Just because of this, RS-485 is widely used in the industries such as safety monitoring.General control chip has all carried serial line interface, but integrated 485 interfaces of little meeting, so controller must could realize the conversion of serial UART interface to 485 interfaces by external change-over circuit.RS485 communication interface signal is differential level form, semiduplex mode work.Synchronization only can send or receive, and needs the direction controlling to send and receive, and the complete interactive communication of ability ensures to receive and dispatch normally.

Existing RS485 interface circuit commutation programme generally has two kinds, software program control commutation, hardware circuit controlling party to.

Utilize the commutation control of software program, the schematic diagram of circuit as shown in Figure 1, by the I/O1 of CPU, I/O2 pin respectively with the direction controlling DE of RS485 transceiver, RE pin connects, by the I/O1 of CPU, I/O2 pin level carrys out control realization direction controlling, when I/O level is high, 485 transceivers are sending mode, the data that now serial ports TX sends can deliver to 485 buses, when I/O level is low, 485 transceivers are receiving mode, data now in 485 buses can be sent to the RX holding wire of serial ports, so just can complete and realize the object with 485 interface communications by UART interface.

Another kind utilizes hardware implementing, circuit is as shown in Fig. 2 ~ 3, U1 is 485 transceiving chip models is ISL3152EIBZ, U2A is the effect that not circuit or transistor switching circuit realize not gate, model is 74HC14, the RE not sum DE pin of U1 connects the input pin 1 of DI pin by UART_TXD connection not circuit U2A of the output pin 2, U1 of not circuit U2A by 485-_DIR, working method is, when UART_TXD does not have data, its level is often high, and 485 transceiving chip U1 are in receiving mode, can normal receive data, when UART_TXD sends data, first send data start bit 0, all the other controllers now in bus start to enter accepting state, sending data bit is 0, 485 transceiving chip U1 are sending mode, normally can send data, when transmission data bit is 1, 485 transceiving chip U1 patterns are for receiving, although now UART_RXD there is high level to occur still because there is no start bit from high to low, UART can't start the data accepting to appear on UART_RXD, other controller simultaneously in bus is all in accepting state, bus free, now the level of bus is decided by the pull-up resistor R2 of transmit control device and pull down resistor R3, 485_A is high level, 485_B is low level, being equivalent to now send data is 1, have sent of data bit 0 and 1 can be completed like this.

Utilize software control 485 to commutate and there are some problems: first can take controller pin, secondly having the environment of operating system, under the environment that especially linux is such, increase the development difficulty of embedded software, and the software compatibility be not easy to.Utilize the commutation control circuit of hardware, based on a not gate mostly, such circuit its driving force when transmission 1 depends on pull-up resistor R2 and pull down resistor R3 completely, driving force is more weak, simultaneously because upper pull down resistor can destroy the impedance of differential lines, upper drop-down resistance value suitably can be reduced in order to increase driving force, although can increase by 485 output driving forces to a certain extent like this, the power that resistance meeting consumption rate is larger.

Summary of the invention

The utility model provides a kind of RS485 automatic reversing circuit in order to solve the problem.

The utility model for addressing this problem taked technical scheme is:

A kind of RS485 automatic reversing circuit of the present utility model, comprise 485 transceiving chips and commutating circuit, and described commutating circuit comprises NAND gate circuit and delay circuit, NAND gate circuit comprises three NAND gate, and delay circuit forms with a capacitances in series by after diode and a resistor coupled in parallel again; Two inputs of the first NAND gate are connected with the 4th pin of 485 transceiving chips, and are connected to the TXD end of processor chips UART universal serial bus, the output of the first NAND gate and the input of delay circuit; An input of the second NAND gate is connected with the output of delay circuit, and another input is connected with the output of the 3rd NAND gate, and is connected to the second pin and the 3rd pin of 485 transceiving chips; An input of the 3rd NAND gate is connected with the output of the second NAND gate, and another input is connected with the 4th pin of 485 transceiving chips.

The advantage that the utility model has and good effect are:

RS485 automatic reversing circuit of the present utility model, the interface conversion of UART to RS485 can be realized, achieve the automatic control in RS485 direction, do not need to take separately controller IO resource, go the control realizing sending and receiving, save the port resource of controller, improve the compatibility of software simultaneously and reduce the development difficulty of embedded program under an operating system, the transmission range of great raising RS485 and antijamming capability, for safety monitoring etc. needs the data transmission applications of highly reliable, long distance 485 to provide good guarantee.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of software realization mode in prior art;

Fig. 2 is the circuit diagram of 485 transceiving chips of hardware implementation mode in prior art;

Fig. 3 is the circuit diagram of not gate in prior art;

Fig. 4 is the circuit diagram of 485 transceiving chips of the present utility model;

Fig. 5 is the circuit diagram of commutating circuit of the present utility model;

Fig. 6 is the sequential chart that UART_TXD of the present utility model sends a byte.

Embodiment

Referring to drawings and Examples, RS485 automatic reversing circuit of the present utility model is described in detail.

As shown in Fig. 4 ~ 6, a kind of RS485 automatic reversing circuit, comprise 485 transceiving chips and commutating circuit, described commutating circuit comprises NAND gate circuit and delay circuit, NAND gate circuit comprises three NAND gate, and delay circuit forms with a capacitances in series by after diode and a resistor coupled in parallel again; Two inputs of the first NAND gate are connected with the 4th pin of 485 transceiving chips, and the TXD being connected to processor chips UART universal serial bus holds the output of the first NAND gate and the input of delay circuit; An input of the second NAND gate is connected with the output of delay circuit, and another input is connected with the output of the 3rd NAND gate, and is connected to the second pin and the 3rd pin of 485 transceiving chips; An input of the 3rd NAND gate is connected with the output of the second NAND gate, and another input is connected with the 4th pin of 485 transceiving chips.

The anode of diode and the junction point of resistance are the input of delay circuit, and the negative electrode of diode and the junction point of resistance are the output of delay circuit.

NAND gate circuit model is 74HC00, comprises 4 NAND gate, and optionally wherein three U1B, U1C, U1D NAND gate use.

Specific works mode is:

When UART_TXD starts to send start bit, (level is by high step-down, keep the time span of a data), 13 pin of U1D can become low level, 11 pin of U1D can become high level immediately, thus the pattern of U2 becomes sending mode, this process lag is in nanosecond, simultaneously, 5 pin of U1B become low level, 6 pin of U1B become high level, by diode D1 fast for electric capacity C2 charges, when C2 is full of electricity, 9 pin of U1C become high level, 8 pin become low level simultaneously, 12 of U1D becomes low level, now the 11 pin level of U1D are decided by the level of 13 pin of U1D, namely the level of UART_TXD decides, supposing that UART sends data by TXD is the byte of 0xff, first send start bit, level change procedure is now described above, and then first of data first sends, namely send a data 1, now 13 pin of U1D can become high level, 5 pin of U1 become high level, 6 pin of U1B become low level, now 9 pin of U1C are still high level, and the discharge loop of an electric capacity is formed between 6 pin of 9 pin of U1C and U1B by R2, R2 is the resistance of a large resistance, need a bit of time, the level of 9 pin of U1C just slowly can become low level, 9 pin level remain high in, followed by 7 data bit sent below, 7 next is all 1, repeat the process of transmitting of the first bit data position above, last position of rest 1 is equally also the same process, before position of rest sends, 9 pin of U1C all keep high level, 8 pin of U1C just keep low level, 12 pin of U1D just keep low level, 11 pin of U1D just keep high level, U2 just keeps sending mode constant, when position of rest is sent, UART_TXD level is high, the 6 pin level of U1B are low, now through the discharge time of the transmission duration of byte 8 bit data, the voltage on electric capacity C2 is lower, and 9 pin of U1C are for being identified as low level, 8 pin of U1C are high level, 12 pin of U1D are just high level, thus 11 pin of U1D are low level, and U2 is in and is switched to receiving mode.UART_TXD keeps high level, and U2 keeps receiving mode, now bus has data, just can receive data normally.

This circuit the parameter of adjusting resistance R2 and electric capacity C2 can adjust the best the response speed being sent to receiving mode according to the difference of baud rate, for 9600, a start bit, 8 bit data, a stopping, sending the time that a byte needs ten bit data, the chances are 1ms, can by the value of adjusting resistance R2 and electric capacity C2, making the 9 pin voltages of U1 drop to identifiable design by height is time of low level voltage be just in time greater than 1ms.In actual (tube) length Distance Transmission, generally baud rate can be selected, and also because transmission line distance, relatively low to the conversion speed requirements being sent to reception, this circuit can meet the needs of actual (tube) length Distance Transmission completely.

UART refers to the serial ports of Transistor-Transistor Logic level here, and computer export is generally externally the serial ports of RS232 level, and Transistor-Transistor Logic level is 5V, and RS232 is negative logic level, and it defines+5 ~+12V is low level, and-12 ~-5V is high level.RXD, TXD etc. of Uart serial ports are generally direct to be connected with the pin of processor chips, and RXD, TXD etc. of RS232 serial ports generally need just can receive on the pin of processor chips through level conversion (usually carrying out level conversion by chips such as Max232), otherwise chip burns out by too high voltage possibly.Universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter), so-called UART is a kind of asynchronous receiving-transmitting transmitter, is usually integrated in embedded controller or periphery IC equipment.

Claims

1. a RS485 automatic reversing circuit, comprise 485 transceiving chips and commutating circuit, it is characterized in that: described commutating circuit comprises NAND gate circuit and delay circuit, NAND gate circuit comprises three NAND gate, and delay circuit forms with a capacitances in series by after diode and a resistor coupled in parallel again; Two inputs of the first NAND gate are connected with the 4th pin of 485 transceiving chips, and are connected to the TXD end of processor chips UART universal serial bus, the output of the first NAND gate and the input of delay circuit; An input of the second NAND gate is connected with the output of delay circuit, and another input is connected with the output of the 3rd NAND gate, and is connected to the second pin and the 3rd pin of 485 transceiving chips; An input of the 3rd NAND gate is connected with the output of the second NAND gate, and another input is connected with the 4th pin of 485 transceiving chips.