CN204009884U - A kind of many network interface cards NCSI management system - Google Patents
A kind of many network interface cards NCSI management system Download PDFInfo
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- CN204009884U CN204009884U CN201420439434.7U CN201420439434U CN204009884U CN 204009884 U CN204009884 U CN 204009884U CN 201420439434 U CN201420439434 U CN 201420439434U CN 204009884 U CN204009884 U CN 204009884U
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Abstract
The utility model provides a kind of many network interface cards NCSI management system, and described system comprises the network card chip of BMC chip, server, and this BMC chip connects respectively switching chip, the first resistance in series, the second resistance in series and clock buffer; The other end of described the second resistance, described switching chip and described clock buffer is all connected described network card chip, and described switching chip connects described BMC chip and row's pin by control signal wire, and described clock buffer connects crystal oscillator by resistance in series.This system effectively solves the interconnected problem of NCSI bus between a BMC chip and a plurality of network card chip, realizes a network card chip and breaks down and still can continue the function of being monitored and being managed by other network card chips.
Description
Technical field
The utility model relates to a kind of device of computer realm, is specifically related to a kind of many network interface cards NCSI management system.
Background technology
Along with the fast development of IT technology, people will try to achieve more and more higher to the administrative skill of server, and wherein reliability and stability are very important index requests.The way of the previous routine of order is to utilize BMC (Baseboard ManagementController, baseboard management controller) chip is by NCSI (Network Controller Sideband Interface), network controller sideband interface) network card chip on signal bus connection server mainboard, the network interface by share service device network card chip sends the monitor message of server or receive into.But the feature of this kind of method for designing is a BMC chip only connects a network card chip, once this network card chip goes wrong, BMC chip has just lost the path with external communication, also just cannot realize effective monitoring function.
At present, the product that has a plurality of network card chips in server product is very common, but only has a set of NCSI supervising the network, cannot realize NCSI bus between BMC chip and a plurality of network card chip interconnected, if exist a network card chip to break down, the technological deficiency that other network card chips also cannot be monitored and manage.
Therefore, need to provide a kind of many network interface cards NCSI management system.
Summary of the invention
In order to overcome the defect of above-mentioned prior art, the utility model provides a kind of many network interface cards NCSI management system.
In order to realize above-mentioned utility model object, the utility model is taked following technical scheme:
Many network interface cards NCSI management system, described system comprises the network card chip of BMC chip, server, its improvements are: described BMC chip connects respectively switching chip, the first resistance in series, the second resistance in series and clock buffer;
The other end of described the second resistance, described switching chip and described clock buffer is all connected described network card chip, and described switching chip connects described BMC chip and row's pin by control signal wire, and described clock buffer connects crystal oscillator by resistance in series.
Further, the number of described network card chip is N, and N is positive integer.
Further, described BMC chip and described network card chip clock homology are synchronous.
Further, by described clock buffer, be divided into the clock of multichannel homology, connect respectively described BMC chip and described network card chip.
Further, row's pin that the control signal of described BMC chip connects is tripod row pin;
The 1st pin of described tripod row pin by resistance at 1K ohm to the accessory power supply of moving 3.3V on the pull-up resistor between 10K ohm to, the switching that the signal control signal of the 2nd pin is connected to described switching chip enables pin, be connected with the control signal from described BMC chip, control the switching of switching chip simultaneously; The 3rd underfooting moved ground to;
Further, described tripod row pin number is
get integer, N is positive integer; The control signal of described BMC chip is drawn
signal line connects tripod row pin.
Compared with prior art, the beneficial effects of the utility model are:
1, the utility model provides network interface card NCSI management system effectively solves the interconnected problem of NCSI bus between a BMC chip and a plurality of network card chip, thereby can realize at a network card chip, breaks down and still can continue the effect of being monitored and being managed by other network card chips.
2, the design proposal that the utility model provides does not almost increase extra cost.Utilize the design feature of the original BMC chip just existing, many network interface cards, clock buffer in current server design, just additionally increased by one and switched chip and corresponding row's pin, cost is almost ignored.
3, two kinds of handover schemes that the utility model provides, both the mode that can control by remote terminal computer realizes the switching between many network interface cards, very flexible, the mode that can arrange pin by scene again realizes the switching of many network interface cards, for on-the-spot maintenance and repair convenience very.
Accompanying drawing explanation
Fig. 1 is the NCSI Functional Design structural drawing of two network card chips in the present embodiment;
Reference numeral: 1-BMC chip; 2-resistance in series; 3-resistance in series; 4-switches chip; 5-the first network card chip; 6-the second network card chip; 7-arranges pin; 8-pull-up resistor; 9-accessory power supply; 10-ground; 11-network; 12-terminal computer; 13-crystal oscillator; 14-resistance in series; 15-clock buffer.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail.
The utility model provides a kind of many network interface cards NCSI management system, and this system comprises the network card chip of BMC chip, server, and described BMC chip connects respectively switching chip, the first resistance in series, the second resistance in series and clock buffer; The other end of described the second resistance, described switching chip and described clock buffer is all connected described network card chip, and described switching chip connects described BMC chip and row's pin by control signal wire, and described clock buffer connects crystal oscillator by resistance in series.The number of described network card chip is N, and N is positive integer.
The clock that is divided into multichannel homology by described clock buffer, connects respectively described BMC chip and described network card chip, realizes described BMC chip and described network card chip clock homology is synchronous.
The control mode of switching chip comprises two kinds:
One, by the control signal of described BMC chip, control the blocked operation of described switching chip;
When described BMC chip by described control signal be arranged to will gating the corresponding control signal level combination of network card chip time, enable to switch the respective channel of chip, the enable signal of the transmission data of described BMC chip can be switched to the enable signal of the transmission data that are connected to wanted gating network card chip.
Two, by the mode of row's pin jumping cap, control switching;
The control signal of described BMC chip connects tripod row pin;
The 1st pin of described tripod row pin by resistance at 1K ohm to the accessory power supply of moving 3.3V on the pull-up resistor between 10K ohm to, the switching that the control signal of the 2nd pin is connected to described switching chip enables pin, be connected with the control signal from described BMC chip, control the switching of switching chip simultaneously; The 3rd underfooting moved ground to;
When jumping cap is arranged on the 1st pin and the 2nd pin, described control signal can be drawn high; When jumping cap is arranged on the 2nd pin and the 3rd pin, described control signal can be dragged down.
By be arranged on jumping cap the high/low level that diverse location is controlled connect control signal on a plurality of row's pins, enable to switch the respective channel of chip, the enable signal of the transmission data of described BMC chip can be switched to the enable signal of the transmission data that are connected to wanted gating network card chip.
Tripod row pin number is definite according to the number of network card chip, and network card chip number is N, and tripod row pin number is
get integer, N is positive integer; The control signal of BMC chip is drawn
get integer signal line and connect tripod row pin, described tripod row pin is controlled respectively the switching of a plurality of network card chips.
For example, when network card chip number is 4, required tripod row pin number is that 2,2 control signal wires connect tripod row pin; When network card chip number is 6, required tripod row pin number is that 3,3 control signal wires connect tripod row pin; When network card chip number is 9, required tripod row pin number is that 4,4 signal line connect tripod row pin.
Suppose to have 2 control signals, 00,01,10,11 respectively corresponding network card chip one, network card chip two, network card chip three, network card chips four so, different when only having two network card chips, be no longer that simple drawing high drags down, but to some draw high, and other positions drag down processing.
If control signal 3, so 000,001,010,011,110,111 corresponding network card chip one, network card chip two, network card chip three, network card chip four, network card chip five, network card chips six respectively.If five network card chips only need by the wherein combination of five certainly.
If 4～X bar control signal, identically controls respectively each network card chip with binary combination number with upper.
When described BMC chip is used the NCSI function of arbitrary network card chip, control method is as follows:
By described BMC chip, this control signal is carried out to the setting of corresponding level, maybe by jumping cap and be arranged on the corresponding stitch of corresponding row's pin, control signal level is carried out to relative set, all the enable signal of the transmission data of described BMC chip can be switched on the enable signal that be connected to wanted gating network card chip transmission data; Disconnect the connection of the enable signal of transmission data and the enable signal of original network card chip transmission data of described BMC chip, terminal computer is by access to netwoks and control described BMC chip simultaneously.
If described network card chip damages while maybe needing to use the NCSI function of another network card chip, described BMC chip is arranged to control signal the corresponding control signal level combination of network card chip of wanted gating, maybe by jumping cap and be arranged on the corresponding stitch of the corresponding tripod row of network card chip pin of wanted gating, control signal is arranged to corresponding signal level combination, enables to switch the corresponding signalling channel of chip and the enable signal of the transmission data of described BMC chip is switched to the enable signal that is connected to wanted gating network card chip transmission data; Disconnect the connection of the enable signal of transmission data and the enable signal of original network card chip transmission data of described BMC chip, terminal computer is by access to netwoks and control described BMC chip simultaneously.
As shown in Figure 1, Fig. 1 is the NCSI Functional Design structural drawing of two network card chips in the present embodiment.
In the present embodiment, the designing requirement of reference clock (RMIIRCLK) is that the clock of BMC chip, the first network card chip, the second network card chip will accomplish that homology is synchronous.Adopt the crystal oscillator 13 of 50MHZ by the resistance 14 connection clock buffers 15 of a resistance between 15 ohm to 50 ohm, by clock buffer 15, be divided into the 50MHZ clock of 3 tunnel homologies.
Wherein a road clock BMC_RMIIRCLK (reference clock signal of BMC chip) is input to BMC chip, the second road clock NIC1_RMIIRCLK (reference clock signal of the first network card chip) is input to the first network card chip 5, and Third Road clock NIC2_RMIIRCLK (reference clock signal of the second network card chip) is input to the second network card chip 6.Thereby, realize the homology requirement of BMC chip and network card chip clock.
The long process such as BMC_RMIIRCLK (reference clock signal of BMC chip), NIC1_RMIIRCLK (reference clock signal of the first network card chip), NIC2_RMIIRCLK (reference clock signal of the second network card chip) will do on pcb board, have realized the synchronous requirement of 3 road clocks.
The resistance 2 of a resistance between 15 ohm to 50 ohm of enable signal (RMIITXEN) signal (BMC_RMIITXEN) series connection of the transmission data of BMC chip, is then connected to and switches on chip 4.
Enable signal NIC1_RMIITXEN (enable signals of the transmission data of the first network card chip) and the NIC2_RMIITXEN (enable signals of the transmission data of the second network card chip) of the transmission data of two outputs of switching chip 4 are connected respectively on the first network card chip 5 and the second network card chip 6.
Switching chip 4 can switch BMC_RMIITXEN (enable signals of the transmission data of BMC chip) to be connected on NIC1_RMIITXEN (enable signals of the transmission data of the first network card chip), also BMC_RMIITXEN (enable signals of the transmission data of BMC chip) can be switched and is connected to NIC2_RMIITXEN above, but each moment BMC can only be communicated with 1 network interface card.
In the present embodiment, two kinds of control modes switching chip 4 are as follows:
The control signal of one, drawing by BMC (Control_Signal) is controlled the blocked operation that switches chip, when BMC chip is drawn high Control_Signal, the BMC_RMIITXEN of BMC chip can be switched and is connected on the NIC1_RMIITXEN of the first network card chip, when BMC chip drags down control signal, the BMC_RMIITXEN of BMC chip can be switched and is connected on NIC2_RMIITXEN.
Two, by the mode of row's pin jumping cap, control switching.
As shown in Figure 1, the 1st pin of row's pin 7 of 3 pin by a resistance at 1K (1,000) ohm to the accessory power supply P3V3_AUX9 that moves 3.3V on the pull-up resistor 8 between 10K ohm to, the switching that the control signal of the 2nd pin is connected to switching chip 4 enables on pin, also be connected with the control signal from BMC chip, control together the switching of switching chip simultaneously.The 3rd underfooting moved ground to, pulls down to zero level.
When jumping cap is arranged on the 1st pin and the 2nd pin, control signal can be drawn high, the BMC_RMIITXEN switching that BMC chip can be sent is connected on NIC1_RMIITXEN, when jumping cap is arranged on the 2nd pin and the 3rd pin, Control_Signal can be dragged down, the BMC_RMIITXEN of BMC can be switched and is connected on NIC2_RMIITXEN.
When BMC chip is used the NCSI function of arbitrary network card chip, control method is as follows:
When if BMC chip is used the NCSI function of the first network card chip 1, by BMC chip, control signal is drawn high, second method is that jumping cap is arranged on the 1st and the 2nd pin of arranging pin control signal is drawn high, switch the BMC_RMIITXEN of BMC chip to be connected on NIC1_RMIITXEN in capital, and disconnected the connection of BMC_RMIITXEN and NIC2_RMIITXEN simultaneously, so BMC chip can be accessed and control to terminal computer 12 by the network of the first network card chip 1.
When if the first network card chip damages or wants to use the NCSI function of the second network card chip 2, BMC drags down Control_Signal, or jumping cap is arranged on the 2nd and the 3rd pin of arranging pin control signal is dragged down, the BMC_RMIITXEN of BMC chip can be switched and is connected on NIC2_RMIITXEN, BMC chip and disconnected BMC_RMIITXEN simultaneously, is connected with NIC1_RMIITXEN, so can be accessed and control to terminal computer 12 by the network of the second network card chip 2.
The 1st (RMIITXD1) method for designing that receives the 0th (RMIIRXD0), the 1st (RMIIRXD1), carrier sense and the data significance bit (RMIICRSDV) that receive data bus of data bus, the 0th (RMIITXD0) sending data bus, transmission data bus is as follows:
The 1st (RMIITXD1) these 5 signals that receive the 0th (RMIIRXD0), the 1st (RMIIRXD1), carrier sense and the data significance bit (RMIICRSDV) that receive data bus of data bus, the 0th (RMIITXD0) sending data bus, transmission data bus are identical with the connected mode of the topological structure shown in Other BMC Signals in Fig. 1 (other BMC signals), the resistance 2 of the resistance between 15 ohm to 50 ohm of first connecting, then be branched into two signal wires, be connected respectively to the first network card chip 5 and the second network card chip 6.
The 0th (RMIIRXD0) of described reception data bus, the 1st (RMIIRXD1), carrier sense and the data significance bit (RMIICRSDV) that receive data bus, the 0th (RMIITXD0) of transmission data bus are, the one end of the 1st (RMIITXD1) of transmission data bus is connected respectively a resistance, another end yoke of resistance is divided into two signal wires, is connected respectively to the first network card chip 5 and the second network card chip 6.If network card chip number is N, another end yoke of signal wire resistance is divided into N root signal wire.
In the present embodiment, switch chip 4 and adopt: the model NC7SB3157L6X of Fairchild Semiconductor company; Network interface card adopts: Intel Company's model is WGI210AT; Clock buffer adopts: ICS company signal is ICS9112AM; Clock adopts: the 7W 50.00000BB-T of TXC company; BMC chip adopts: the AST2400 of ASPEED company.
Finally should be noted that: above embodiment is only in order to illustrate that the technical solution of the utility model is not intended to limit, although the utility model is had been described in detail with reference to above-described embodiment, those of ordinary skill in the field are to be understood that: still can modify or be equal to replacement embodiment of the present utility model, and do not depart from any modification of the utility model spirit and scope or be equal to replacement, it all should be encompassed in the middle of claim scope of the present utility model.
Claims (6)
1. the NCSI of network interface card a more than management system, described system comprises the network card chip of BMC chip, server, it is characterized in that: described BMC chip connects respectively switching chip, the first resistance in series, the second resistance in series and clock buffer;
The other end of described the second resistance, described switching chip and described clock buffer is all connected described network card chip, and described switching chip connects described BMC chip and row's pin by control signal wire, and described clock buffer connects crystal oscillator by resistance in series.
2. the system as claimed in claim 1, is characterized in that: the number of described network card chip is N, and N is positive integer.
3. system as claimed in claim 2, is characterized in that: described BMC chip and described network card chip clock homology are synchronous.
4. system as claimed in claim 3, is characterized in that: by described clock buffer, be divided into the clock of multichannel homology, connect respectively described BMC chip and described network card chip.
5. the system as claimed in claim 1, is characterized in that: row's pin that the control signal of described BMC chip connects is tripod row pin;
The 1st pin of described tripod row pin by resistance at 1K ohm to the accessory power supply of moving 3.3V on the pull-up resistor between 10K ohm to, the switching that the signal control signal of the 2nd pin is connected to described switching chip enables pin, be connected with the control signal from described BMC chip, control the switching of switching chip simultaneously; The 3rd underfooting moves ground to.
6. system as claimed in claim 5, is characterized in that: described tripod row pin number is
get integer, N is positive integer; The control signal of described BMC chip is drawn
signal line connects tripod row pin.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104133799A (en) * | 2014-08-06 | 2014-11-05 | 曙光信息产业(北京)有限公司 | Multi-network-card NCSI management system |
| CN107070699A (en) * | 2017-03-04 | 2017-08-18 | 郑州云海信息技术有限公司 | Controller monitoring is managed in storage system redundancy design method and device |
| CN107888222A (en) * | 2017-11-16 | 2018-04-06 | 郑州云海信息技术有限公司 | A kind of circuit structure and method of optimization NCSI signal qualitys |
| CN108009114A (en) * | 2017-12-08 | 2018-05-08 | 郑州云海信息技术有限公司 | A kind of isometric structure of optimization NCSI clock cables |
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2014
- 2014-08-06 CN CN201420439434.7U patent/CN204009884U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104133799A (en) * | 2014-08-06 | 2014-11-05 | 曙光信息产业(北京)有限公司 | Multi-network-card NCSI management system |
| CN107070699A (en) * | 2017-03-04 | 2017-08-18 | 郑州云海信息技术有限公司 | Controller monitoring is managed in storage system redundancy design method and device |
| CN107888222A (en) * | 2017-11-16 | 2018-04-06 | 郑州云海信息技术有限公司 | A kind of circuit structure and method of optimization NCSI signal qualitys |
| CN107888222B (en) * | 2017-11-16 | 2020-08-25 | 苏州浪潮智能科技有限公司 | Circuit structure and method for optimizing NCSI signal quality |
| CN108009114A (en) * | 2017-12-08 | 2018-05-08 | 郑州云海信息技术有限公司 | A kind of isometric structure of optimization NCSI clock cables |
| CN108009114B (en) * | 2017-12-08 | 2020-09-29 | 苏州浪潮智能科技有限公司 | Structure for optimizing equal length of NCSI clock signal line |
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