CN204008993U - The multiplexing automatic testing equipment of the non-principle of a kind of miniaturization - Google Patents
The multiplexing automatic testing equipment of the non-principle of a kind of miniaturization Download PDFInfo
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- CN204008993U CN204008993U CN201420415424.XU CN201420415424U CN204008993U CN 204008993 U CN204008993 U CN 204008993U CN 201420415424 U CN201420415424 U CN 201420415424U CN 204008993 U CN204008993 U CN 204008993U
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Abstract
Problem for existing automatic testing equipment poor compatibility, the utility model provides the non-principle of a kind of miniaturization multiplexing automatic testing equipment, comprise boundary scanning chip array group, JTAG adapter and JTAG router, wherein, multiplexing test interface circuit links together boundary scanning chip array group and JTAG adapter both-way communication respectively with by JTAG router; In addition: be provided with a multiplexing test interface circuit; Described multiplexing test interface circuit is connected with boundary scanning chip array group, JTAG router respectively and two-way communication.Described multiplexing test interface circuit is by control circuit, level shifting circuit and resistance protection the electric circuit constitute; The utility model has the advantage of: this product has simple in structure, wiring compactness, and adopts ripe chip and electronic devices and components, has extremely low purchase cost and good compatibility.
Description
Technical field
The utility model belongs to circuit test field, relates in particular to the multiplexing automatic testing equipment of the non-principle of a kind of miniaturization.
Background technology
Be widely used in electronic equipment in industrial circle in the robotization that becomes, intelligentized while, because they are a large amount of, adopt large scale integrated circuit and even VLSI (very large scale integrated circuit), cause the circuit board of these electronic equipments to be designed to become increasingly complex, the new technical barrier thereupon bringing: the maintenance of the circuit board of these electronic equipments and detection also become more and more difficult.
Under these circumstances, can carry out automatic testing equipment to above-mentioned electronic equipment and become more and more important.Yet mostly the existing automatic testing equipment for circuit board is for specific model board design research and development, an automatic testing equipment is only for the circuit board in a kind of electronic equipment of model, and usable range is very narrow.In order to improve the usable range of automatic testing equipment, there is producer to manufacture to have the checkout equipment of many interfaces to attempt to improve the scope of application that device is established in existing automatic detection.But the interface that is equipped with many specifications can solve the fitness to existing circuit board under test, the problem that thereupon also can produce interface wiring complexity, consume additional channels resource, electromagnetic interference (EMI) increases and cost rises.In addition, along with the development of equipment and electronic technology, the kind of interface is in constantly upgrading improves, and the incompatibility problem of the old and new's interface is also becoming increasingly conspicuous, therefore configure merely the versatility problem that the method for many specifications interface can not solve automatic detection device well.Finally, complicated wiring interface and hardware cloth ray mode, also can cause development and testing program difficulty, and then impact is used.
Utility model content
For the problem of existing automatic testing equipment poor compatibility, technical matters to be solved of the present utility model is to provide a kind of cost lower and have the multiplexing automatic testing equipment of the non-principle of miniaturization of favorable compatibility, and its concrete structure is as follows:
The multiplexing automatic testing equipment of the non-principle of a kind of miniaturization, comprise boundary scanning chip array group 1, (the Joint Test Action Group of combined testing action group, JTAG) adapter 3 and JTAG router four, wherein, multiplexing test interface circuit 2 links together boundary scanning chip array group 1 and JTAG adapter 3 both-way communication respectively with by JTAG router four; In addition: be provided with a multiplexing test interface circuit 2; Described multiplexing test interface circuit 2 is connected with boundary scanning chip array group 1, JTAG router four respectively and two-way communication.
Furtherly, multiplexing test interface circuit 2 is comprised of control circuit 21, level shifting circuit 22 and resistance protection circuit 23; Wherein, level shifting circuit 22 is connected with control circuit 21, resistance protection circuit 23 respectively; By level shifting circuit 22, be connected with boundary scanning chip array group 1, the JTAG router four of multiplexing test interface circuit 2 outsides respectively and two-way communication.
the utility model has the advantage of
The utility model provides a kind of multiplexing automatic testing equipment of the non-principle of miniaturization of being furnished with multiplexing test interface circuit 2, there is simple in structure, wiring compactness, and adopt ripe chip and electronic devices and components, there is extremely low purchase cost and good interface compatibility.
This product is not the pin of drawing simply 256 test use; but configured level conversion and resistance protection structure for each pin, can prevent electrical noise interference that the level differences because of the socket of different equipment to be detected causes, eliminate because of the different abnormal signals that bring of electric potential difference.Therefore, there is good extending space.
This product adopts single multiplex interface---be multiplexing test interface circuit 2, avoid configuring the interface of a plurality of different sizes simultaneously and cause take the problem that internal system resource is many, electromagnetic interference (EMI) is large.
Therefore, adopt the automatic detection device of interface that the utility model provides to there is strong adaptability, the feature that cost is low, have versatility, non-principle.
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present utility model.
Fig. 2 is the structured flowchart of multiplexing test interface in Fig. 1.
Fig. 3 is the circuit diagram of resistance protection circuit in Fig. 2.
Fig. 4 is the simple view of single pin electronic circuit in Fig. 3.
In figure, sequence number is: boundary scanning chip array group 1, multiplexing test interface circuit 2, JTAG adapter 3 and JTAG router four, control circuit 21, level shifting circuit 22, resistance protection circuit 23.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in detail.
Referring to Fig. 1, the multiplexing automatic testing equipment of the non-principle of a kind of miniaturization, comprise boundary scanning chip array group 1, JTAG adapter 3 and JTAG router four, wherein, multiplexing test interface circuit 2 links together boundary scanning chip array group 1 and JTAG adapter 3 both-way communication respectively with by JTAG router four; It is characterized in that: be provided with a multiplexing test interface circuit 2; Described multiplexing test interface circuit 2 is connected with boundary scanning chip array group 1, JTAG router four respectively and two-way communication.
Furtherly, multiplexing test interface circuit 2 is comprised of control circuit 21, level shifting circuit 22 and resistance protection circuit 23; Wherein, level shifting circuit 22 is connected with control circuit 21, resistance protection circuit 23 respectively; By level shifting circuit 22, be connected with boundary scanning chip array group 1, the JTAG router four of multiplexing test interface circuit 2 outsides respectively and two-way communication, refer to Fig. 2.
Furtherly, described resistance protection circuit 23 consists of 16 groups of resistance protection electronic circuits, be followed successively by the 1st resistance protection electronic circuit, the 2nd resistance protection electronic circuit, the 3rd resistance protection electronic circuit, the 4th resistance protection electronic circuit, the 5th resistance protection electronic circuit, the 6th resistance protection electronic circuit, the 7th resistance protection electronic circuit, the 8th resistance protection electronic circuit, the 9th resistance protection electronic circuit, the 10th resistance protection electronic circuit, the 11st resistance protection electronic circuit, the 12nd resistance protection electronic circuit, the 13rd resistance protection electronic circuit, the 14th resistance protection electronic circuit, the 15th resistance protection electronic circuit and the 16th resistance protection electronic circuit, refer to Fig. 3,
Described level shifting circuit 22 consists of 16 level transferring chip; Be followed successively by the 1st level transferring chip, the 2nd level transferring chip, the 3rd level transferring chip, the 4th level transferring chip, the 5th level transferring chip, the 6th level transferring chip, the 7th level transferring chip, the 8th level transferring chip, the 9th level transferring chip, the 10th level transferring chip, the 11st level transferring chip, the 12nd level transferring chip, the 13rd level transferring chip, the 14th level transferring chip, the 15th level transferring chip and the 16th level transferring chip, refer to Fig. 3;
16 groups of described resistance protection electronic circuits connect one by one with 16 corresponding level transferring chip respectively, the 1st resistance protection electronic circuit is connected with the 1st level transferring chip, the 2nd resistance protection electronic circuit is connected with the 2nd level transferring chip, by that analogy, the 16th resistance protection electronic circuit is connected with the 16th level transferring chip, refers to Fig. 3;
In addition, 16 level transferring chip are all connected with control circuit 21, refer to Fig. 3.
Furtherly, each resistance protection electronic circuit all includes 16 pin electronic circuits; Referring to Fig. 4, every pin electronic circuit forms by the power end resistance R b connecting successively, leads ends resistance R _ f and pin; Wherein, a termination 3.3V of power end resistance R b or the power supply of 5V, the other end of power end resistance R b is connected with one end of leads ends resistance R _ f, and the other end of leads ends resistance R _ f is connected with pin; Power end resistance R b is connected with corresponding level transferring chip with the node between leads ends resistance R _ f, refers to Fig. 3.This product amounts to 256 pins, is divided into 16 groups, and every 16 pins share a level transferring chip; The external interface that described 256 pins form be take CPCI connector and PXI connector as main, also can replace to PCI connector, ISA connector, or by interface conversion adapter, transfer into the connector of other specification.Because the interfaces such as CPCI, PXI have similar agreement, even other interfaces also can be realized compatible expansion by interface conversion adapter, and this device has holding circuit, can compatible for plurality of level, so versatility is stronger.In addition owing to being based on boundary scan testing, therefore adopt after the multiplexing test interface 2 of this product, the test procedure of proving installation self does not need secondary development, so performance history is simple, easy to use.
Furtherly, the resistance of power end resistance R b is 10K Ω, and the resistance of leads ends resistance R _ f is 0 Ω.
Furtherly, the model of power end resistance R b is RMK1005MB103JM, and the model of leads ends resistance R _ f is RMK1005MB000JM, and the model of level transferring chip is IDT74FCT164245; Control circuit 21 is a chip that model is SMD566-743.
Furtherly, between JTAG router four and boundary scanning chip array 1, adopt jtag bus to be connected; Between JTAG router four and multiplexing test interface 2, adopt jtag bus to be connected; Between JTAG adapter 3 and JTAG router four, adopt usb bus to be connected; Boundary scanning chip array group 1 is swept chip by 4 EP1C6F256 limits and is formed, and each IO pin that chip is swept on each EP1C6F256 limit is a test resource.EP1C6F256 sweeps on limit that chip I/O number of pin is more, cheap, chip size is little, can effectively reduce the volume of automatic testing equipment.Chip is swept on four EP1C6F256 limits, and TDI, two signals of TDO are connected in series, and TCK, two signals of TMS are connected according to bus.
This product, by boundary scanning chip array 1 and multiplexing test interface 2 are combined together to use, with the board design of small-scale, is realized to common interfaces the automatic test of interface cards such as CPCI, PXI.This product is without the interface of form various kinds and complicated wiring, what therefore the size of this product can be done is very little, only need to be linked in the cabinet of circuit-under-test plate, or when circuit-under-test plate has expansion CPCI, PXI interface, directly be inserted on circuit-under-test plate, therefore test is simple.
Finally, the multiplexing test interface 2 that this product adopts, has realized the conversion between the varying levels such as TTL, CMOS, has also strengthened driving force, has guaranteed the reliability of test.On cost, the existing testing apparatus of comparing, this infrastructure product cheap.
Claims (7)
1. the multiplexing automatic testing equipment of the non-principle of miniaturization, comprise boundary scanning chip array group (1), JTAG adapter (3) and JTAG router (4), wherein, multiplexing test interface circuit (2) links together boundary scanning chip array group (1) and JTAG adapter (3) both-way communication respectively with by JTAG router (4); It is characterized in that: be provided with a multiplexing test interface circuit (2); Described multiplexing test interface circuit (2) is connected with boundary scanning chip array group (1), JTAG router (4) respectively and two-way communication.
2. the multiplexing automatic testing equipment of the non-principle of a kind of miniaturization as claimed in claim 1, is characterized in that: multiplexing test interface circuit (2) is comprised of control circuit (21), level shifting circuit (22) and resistance protection circuit (23); Wherein, level shifting circuit (22) is connected with control circuit (21), resistance protection circuit (23) respectively; By level shifting circuit (22), be connected and two-way communication with boundary scanning chip array group (1), the JTAG router (4) of multiplexing test interface circuit (2) outside respectively.
3. the multiplexing automatic testing equipment of the non-principle of a kind of miniaturization as claimed in claim 2, it is characterized in that: described resistance protection circuit (23) consists of 16 groups of resistance protection electronic circuits, be followed successively by the 1st resistance protection electronic circuit, the 2nd resistance protection electronic circuit ..., until the 16th resistance protection electronic circuit; Described level shifting circuit (22) consists of 16 level transferring chip, be followed successively by the 1st level transferring chip, the 2nd level transferring chip ..., until the 16th level transferring chip; 16 groups of described resistance protection electronic circuits connect one by one with 16 corresponding level transferring chip respectively, the 1st resistance protection electronic circuit is connected with the 1st level transferring chip, the 2nd resistance protection electronic circuit is connected with the 2nd level transferring chip, by that analogy, the 16th resistance protection electronic circuit is connected with the 16th level transferring chip; 16 level transferring chip are all connected with control circuit (21).
4. the multiplexing automatic testing equipment of the non-principle of a kind of miniaturization as claimed in claim 3, is characterized in that: each resistance protection electronic circuit all includes 16 pin electronic circuits; Wherein, every pin electronic circuit forms by the power end resistance R b connecting successively, leads ends resistance R _ f and pin; Wherein, power end resistance R b is connected with corresponding level transferring chip with the node between leads ends resistance R _ f.
5. the multiplexing automatic testing equipment of the non-principle of a kind of miniaturization as claimed in claim 4, is characterized in that: the resistance of power end resistance R b is 10K Ω, and the resistance of leads ends resistance R _ f is 0 Ω.
6. the multiplexing automatic testing equipment of the non-principle of a kind of miniaturization as claimed in claim 5, it is characterized in that: the model of power end resistance R b is RMK1005MB103JM, the model of leads ends resistance R _ f is RMK1005MB000JM, and the model of level transferring chip is IDT74FCT164245; Control circuit (21) is a chip that model is SMD566-743.
7. the multiplexing automatic testing equipment of the non-principle of a kind of miniaturization as claimed in claim 6, is characterized in that: between JTAG router (4) and boundary scanning chip array (1), adopt jtag bus to be connected; Between JTAG router (4) and multiplexing test interface (2), adopt jtag bus to be connected; Between JTAG adapter (3) and JTAG router (4), adopt usb bus to be connected; Boundary scanning chip array group (1) is swept chip by 4 EP1C6F256 limits and is formed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420415424.XU CN204008993U (en) | 2014-07-25 | 2014-07-25 | The multiplexing automatic testing equipment of the non-principle of a kind of miniaturization |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420415424.XU CN204008993U (en) | 2014-07-25 | 2014-07-25 | The multiplexing automatic testing equipment of the non-principle of a kind of miniaturization |
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| CN204008993U true CN204008993U (en) | 2014-12-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105866599A (en) * | 2016-05-26 | 2016-08-17 | 梁平县天胜电子有限公司 | Device and method for testing 24PIN transformer by adopting 20PIN transformer general-purpose tester |
| CN111579974A (en) * | 2020-06-09 | 2020-08-25 | 中国电子科技集团公司第十四研究所 | Tested module, embedded system and test method for realizing boundary scan test |
-
2014
- 2014-07-25 CN CN201420415424.XU patent/CN204008993U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105866599A (en) * | 2016-05-26 | 2016-08-17 | 梁平县天胜电子有限公司 | Device and method for testing 24PIN transformer by adopting 20PIN transformer general-purpose tester |
| CN111579974A (en) * | 2020-06-09 | 2020-08-25 | 中国电子科技集团公司第十四研究所 | Tested module, embedded system and test method for realizing boundary scan test |
| CN111579974B (en) * | 2020-06-09 | 2021-09-03 | 中国电子科技集团公司第十四研究所 | Embedded system for realizing boundary scan test and test method |
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