CN203858866U - Sense amplifier and storage system applying same - Google Patents
Sense amplifier and storage system applying same Download PDFInfo
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- CN203858866U CN203858866U CN201420239372.5U CN201420239372U CN203858866U CN 203858866 U CN203858866 U CN 203858866U CN 201420239372 U CN201420239372 U CN 201420239372U CN 203858866 U CN203858866 U CN 203858866U
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- pmos pipe
- sense amplifier
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- power supply
- node
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Abstract
The utility model discloses a sense amplifier and a storage system applying same. The sense amplifier comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube. The fifth PMOS tube is connected between a node and a power supply, the source electrode of the fifth PMOS tube is connected with the power supply, the drain electrode and the grid electrode are connected with the node, and under the condition of not adding additional power consumption, the voltage of the node after the sense amplifier is electrified has a definite voltage value, so that the jump amplitude of the voltage at nodes before and behind the fifth PMOS tube can also be a definite value; through the fifth PMOS tube properly selected, the jump amplitude of the voltage at the node can also be reduced, so that the dithering of ambient signals caused by voltage jump of the nodes can be reduced.
Description
Technical field
The utility model relates to technical field of memory, relates in particular to a kind of sense amplifier and applies its storage system.
Background technology
In stocking system, conventionally with using sense amplifier, be used for the size of the electric current that electric current that comparison storage unit produces and reference unit produce, be 0 or 1 with what determine cell stores.
In sense amplifier, can comprise some middle nodes, some node can be directly connected to power supply or ground, and some can not be directly connected to power supply or ground, will keep floating dummy status.In sense amplifier, conventionally also have a lot of switch (can realize with transistor), before switch closure, particularly for the first time before closure, the voltage of the node in floating dummy status is unpredictable, therefore, after switch closure, the voltage jump value of this node and the impact that brings thereof also can not be estimated.In order to reduce the impact of switch closure front and back saltus step, can before switch closure, floating empty voltage be placed in to a voltage that relatively approaches working value, the voltage while reducing as far as possible switch closure is beated.
Fig. 1 is the circuit diagram of the sense amplifier of prior art.Referring to Fig. 1, sense amplifier comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3 and the 4th PMOS pipe P4 and for receiving the first signal end REFEN of first signal, for receiving the secondary signal end SAEN of secondary signal, for receiving reference current input end REF0, the output terminal OUT0 of reference current and the node PS0 in floating dummy status.After sense amplifier has powered on, be added in reference voltage VREF0 on the grid of the 2nd PMOS pipe P2 and the grid of the 3rd PMOS pipe P3 and equal the voltage of power supply VS0, and the voltage of node PS0 is a uncertain value.In the time that secondary signal is low level, the 4th PMOS pipe P4 conducting, in conducting moment, the voltage of node PS0 is elevated to the voltage of power supply VS0 fast from a uncertain value, its significantly saltus step meeting be coupled and cause the shake of the periphery signals such as reference voltage VREF by stray capacitance.
Utility model content
In view of this, the utility model embodiment provides a kind of sense amplifier and applies its storage system, to solve the significantly technical matters of the caused periphery signal jitter of saltus step of voltage of sense amplifier of the prior art node in floating dummy status before and after switch closure.
First aspect, the utility model embodiment provides a kind of sense amplifier, comprising: a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe and the 5th PMOS pipe;
The grid of a described PMOS pipe is connected with first signal end, and source electrode connects power supply, and drain electrode is connected with the source electrode of described the 2nd PMOS pipe;
The drain electrode of described the 2nd PMOS pipe is connected with reference current input end, and grid is connected with the grid of its drain electrode and described the 3rd PMOS pipe;
The drain electrode of described the 3rd PMOS pipe is connected with output terminal, and source electrode is connected with the drain electrode of described the 4th PMOS pipe and the drain electrode of described the 5th PMOS pipe by node;
The grid of described the 4th PMOS pipe is connected with secondary signal end, and source electrode connects power supply;
The grid of described the 5th PMOS pipe is connected with its drain electrode, and source electrode connects power supply.
Further, described first signal end is used for receiving first signal, and described secondary signal end is used for receiving secondary signal, and described reference current input end is used for receiving reference current.
Further, in the process powering at described sense amplifier, described power supply charges to described node by described the 5th PMOS pipe;
After described sense amplifier has powered on, the threshold voltage of the voltage that the voltage of described node is described power supply and described the 5th PMOS pipe poor.
Further, after described sense amplifier has powered on, the reference voltage that is applied to the grid of described the 2nd PMOS pipe and the grid of described the 3rd PMOS pipe equals the voltage of described power supply;
After described sense amplifier has powered on and in the time that described first signal is low level, a described PMOS pipe conducting, starts to set up described reference voltage according to the size of described reference current simultaneously;
After described reference voltage has been set up and in the time that described secondary signal is low level, described the 4th PMOS pipe conducting, the voltage of described node becomes the voltage of described power supply, makes described the 3rd PMOS pipe conducting, and sense amplifier is started working.
Further, the threshold voltage of described the 2nd PMOS pipe equates with the threshold voltage of described the 3rd PMOS pipe, and the overdrive voltage of described the 2nd PMOS pipe is less than the threshold voltage of described the 5th PMOS pipe.
Second aspect, the utility model embodiment also provides a kind of storage system, described storage system comprises reference unit, storage unit and sense amplifier, the reference current input end of described sense amplifier is connected with described reference unit and the output terminal of described sense amplifier is connected with described storage unit, the size of the electric current that the electric current that described sense amplifier produces for more described reference unit and described storage unit produce, wherein, described sense amplifier is the sense amplifier described in above-mentioned first aspect.
The sense amplifier that the utility model embodiment provides and apply its storage system, on basis by the sense amplifier in prior art, between node and power supply, be connected a 5th PMOS pipe, the source electrode of the 5th PMOS pipe is connected with power supply, drain electrode is connected with its grid and node, in the situation that not increasing extra power consumption, can make the voltage of the node after sense amplifier has powered on have a definite magnitude of voltage, thereby can make the hopping amplitude of the voltage of the node before and after the 5th PMOS pipe conducting is also a definite value, can also reduce again the hopping amplitude of the voltage of node by suitably choosing the 5th PMOS pipe, thereby can reduce the shake due to the caused periphery signal of voltage jump of node.
Brief description of the drawings
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, it is more obvious that other features, objects and advantages of the present utility model will become:
Fig. 1 is the circuit diagram of the sense amplifier of prior art;
Fig. 2 is the circuit diagram of a kind of sense amplifier of the utility model embodiment;
Fig. 3 is the sequential chart about each signal of the sense amplifier in Fig. 2;
Fig. 4 is the structural representation of a kind of storage system of the utility model embodiment.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the utility model, but not to restriction of the present utility model.It also should be noted that, for convenience of description, in accompanying drawing, only show the part relevant to the utility model but not full content.
The utility model embodiment provides a kind of sense amplifier.Fig. 2 is the circuit diagram of a kind of sense amplifier of the utility model embodiment.As shown in Figure 2, described sense amplifier comprises: a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4 and the 5th PMOS pipe MP5; The grid of a described PMOS pipe MP1 is connected with first signal end EN1, and source electrode meets power supply VS, and drain electrode is connected with the source electrode of described the 2nd PMOS pipe MP2; The drain electrode of described the 2nd PMOS pipe MP2 is connected with reference current input end REF, and grid is connected with the grid of its drain electrode and described the 3rd PMOS pipe MP3; The drain electrode of described the 3rd PMOS pipe MP3 is connected with output terminal OUT, and source electrode is connected with the drain electrode of described the 4th PMOS pipe MP4 and the drain electrode of described the 5th PMOS pipe MP5 by node PS1; The grid of described the 4th PMOS pipe MP4 is connected with secondary signal end EN2, and source electrode meets power supply VS; The grid of described the 5th PMOS pipe MP5 is connected with its drain electrode, and source electrode meets power supply VS.
Further, described first signal end EN1 is used for receiving first signal ENS1, and described secondary signal end EN2 is used for receiving secondary signal ENS2, and described reference current input end REF is used for receiving reference current IREF.It should be noted that, first signal ENS1 and secondary signal ENS2 belong to pulse signal, and for controlling the duty of sense amplifier, wherein the high level of pulse signal is the voltage VDD of power supply VS, and low level is 0; Reference current IREF is a constant electric current, if sense amplifier is applied to storage system, reference current IREF can be provided by the reference unit in storage system.
Further, in the process powering at described sense amplifier, described power supply VS charges to described node PS1 by described the 5th PMOS pipe MP5; After described sense amplifier has powered on, the voltage of described node PS1 is the poor of the voltage VDD of described power supply VS and the threshold voltage of described the 5th PMOS pipe MP5.
Particularly, before sense amplifier powers on, the voltage of node PS1 is 0.In the time that sense amplifier powers on beginning, because the voltage of node PS1 is 0, make the 5th PMOS pipe conducting, and in the process powering at sense amplifier, power supply VS is node PS1 charging by the 5th PMOS pipe of conducting, until the voltage of node PS1 becomes the poor of the voltage VDD of power supply VS and the threshold voltage of the 5th PMOS pipe, the 5th PMOS pipe cut-off, the charging of complete paired node PS1, also can say, after sense amplifier has powered on, the voltage of node PS1 has a definite magnitude of voltage, the size of this magnitude of voltage equals the poor of the voltage VDD of power supply VS and the threshold voltage of the 5th PMOS pipe.
In the time of the 4th PMOS pipe conducting, the voltage of node PS1 becomes the voltage VDD of power supply VS, and compared with before the 4th PMOS pipe conducting, the voltage of node PS1 has only changed the size of a threshold voltage of the 5th PMOS pipe, and hopping amplitude is also a definite value.When sense amplifier in design drawing 2, suitably the smaller PMOS pipe of selected threshold voltage is managed as the 5th PMOS, the voltage that can make like this node PS1 before the 5th PMOS pipe conducting closer to the voltage VDD of power supply VS, be the operating voltage of sense amplifier, can reduce as much as possible the saltus step of the voltage of node PS1 before and after the 5th PMOS pipe conducting.Therefore, compared with the sense amplifier of the prior art in Fig. 1, the sense amplifier that the utility model embodiment in Fig. 2 provides by connecting a 5th PMOS pipe MP5 between power supply VS and node PS1, in the situation that not increasing extra power consumption, can make the voltage of the node PS1 after having powered on have a definite magnitude of voltage, thereby can make the hopping amplitude of the voltage of the node PS1 before and after the 5th PMOS pipe conducting is also a definite value, can also reduce again the hopping amplitude of the voltage of node PS1 by suitably choosing the 5th PMOS pipe MP5, thereby can reduce the shake due to the caused periphery signal of voltage jump of node PS1.
Fig. 3 is the sequential chart about each signal of the sense amplifier in Fig. 2.It should be noted that, Fig. 3 is the sequential chart of each signal after sense amplifier has powered on.Referring to Fig. 2 and Fig. 3, after described sense amplifier has powered on, the reference voltage VREF that is applied to the grid of described the 2nd PMOS pipe MP2 and the grid of described the 3rd PMOS pipe MP3 equals the voltage VDD of described power supply VS.Now first signal ENS1 and secondary signal ENS2 are high level, and a PMOS pipe MP1 and the 4th PMOS pipe MP4 are also in cut-off state.
Referring to Fig. 2 and Fig. 3, in the time that described first signal ENS1 is low level, a described PMOS pipe MP1 conducting, starts to set up described reference voltage VREF according to the size of described reference current IREF simultaneously.Due in the time that sense amplifier is normally worked, need the 3rd PMOS pipe MP3 in conducting state, and after sense amplifier has powered on, reference voltage VREF equals the voltage VDD of power supply VS, the magnitude of voltage of this reference voltage VREF cannot make the 3rd PMOS pipe MP3 conducting, thereby also just can not make sense amplifier normally work.Therefore, need to reduce with reference to voltage VREF, the process of this reduction is exactly the process that reference voltage VREF sets up, and is reduced to concrete magnitude of voltage, is decided by the size of reference current IREF.In Fig. 3, the T time period represents the time period of reference voltage VREF process of establishing.As can be seen from Figure 3, within the T time period, reference voltage VREF drops to the first voltage V1 from the voltage VDD of power supply VS, i.e. the required reference voltage level of the normal work of sense amplifier, and the size of the first voltage V1 is relevant with the size of reference current IREF.
Describe in detail the process of establishing of reference voltage VREF below in conjunction with Fig. 2 and Fig. 3.In the time that first signal ENS1 is low level, the one PMOS pipe MP1 conducting, the voltage at the source electrode place of the 2nd PMOS pipe MP2 is the voltage VDD of power supply VS, now also equal the voltage VDD of power supply VS due to reference voltage VREF, the 2nd PMOS pipe MP2 is still in cut-off state, constant reference current IREF extracts electric charge by the Nodes from reference voltage VREF place and forms, therefore, reference voltage VREF starts to decline from the voltage VDD of power supply VS, in the time that reference voltage VREF equals the difference of the voltage VDD of power supply VS and the threshold voltage of the 2nd PMOS pipe MP2, the 2nd critical point of PMOS pipe MP2 in conducting, along with reference voltage VREF continues to decline, the 2nd PMOS pipe MP2 starts conducting, and the 2nd PMOS pipe MP2 starts generation current.When the electric current producing as the 2nd PMOS pipe MP2 equals reference current IREF, reference voltage VREF has set up, now reference voltage VREF equals the size of the first voltage V1, and the size of reference voltage VREF is now the required reference voltage level of the normal work of sense amplifier.
Setting up in the process of reference voltage VREF, in order to ensure that the 3rd PMOS pipe MP3 is still in cut-off state, preferably, the threshold voltage of described the 2nd PMOS pipe MP2 equates with the threshold voltage of described the 3rd PMOS pipe MP3, and the overdrive voltage that described the 2nd PMOS manages MP2 is less than described the 5th PMOS manages the threshold voltage of MP5.For convenience described below, the threshold voltage of establishing the 2nd PMOS pipe MP2 is VT2, and the threshold voltage of the 3rd PMOS pipe MP3 is that the threshold voltage of VT3 and the 5th PMOS pipe MP5 is VT5.The overdrive voltage of the 2nd PMOS pipe MP2 is VDD-VT2-VREF, and is more than or equal to 0.In the process of setting up at reference voltage VREF, the overdrive voltage of the 2nd PMOS pipe MP2 starts to produce from the critical point of its conducting, start to produce when VDD-VT2=VREF, and along with the reduction of VREF, it is large that overdrive voltage becomes.And in the process of setting up at reference voltage VREF, the voltage difference between source electrode and the grid of the 3rd PMOS pipe MP3 is the voltage difference of voltage and the reference voltage VREF of node PS1, be VDD-VT5-VREF.When choosing the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3 and the 5th PMOS pipe MP5, while making the threshold V T 2 of the 2nd PMOS pipe MP2 equal the threshold V T 3 of the 3rd PMOS pipe MP3 and the overdrive voltage of the 2nd PMOS pipe MP2 to be less than the threshold V T 5 of stating the 5th PMOS pipe MP5, in the process of setting up at reference voltage VREF, there is VDD-VT5-VREF to be less than VT3, in the process of setting up at reference voltage VREF, the 3rd PMOS pipe MP3 remain off state always.
Referring to Fig. 2 and Fig. 3, after described reference voltage VREF has set up and in the time that described secondary signal ENS2 is low level, described the 4th PMOS pipe MP4 conducting, the voltage of described node PS1 becomes the voltage VDD of described power supply VS, make described the 3rd PMOS pipe MP3 conducting, sense amplifier is started working.Particularly, because the voltage of node PS1 is now VDD, the voltage difference between source electrode and the grid of the 3rd PMOS pipe MP3 is greater than the threshold V T 3 of the 3rd PMOS pipe MP3, therefore the 3rd PMOS pipe MP3 conducting, and now sense amplifier is started working.
The utility model embodiment also provides a kind of storage system.Fig. 4 is the structural representation of a kind of storage system of the utility model embodiment.Referring to Fig. 4, described storage system comprises reference unit 11, storage unit 12 and sense amplifier 13, the reference current input end REF1 of described sense amplifier 13 is connected with described reference unit 11 and the output terminal OUT1 of described sense amplifier 13 is connected with described storage unit 12, the size of the electric current that the electric current that described sense amplifier 13 produces for more described reference unit 11 and described storage unit 12 produce is 0 or 1 with what determine that described storage unit 12 stores.Wherein, described sense amplifier 13 is above-mentioned sense amplifier.
Above-mentioned storage system can be the storage system of NOR (or non-) type flash-memory storage system, NAND (with non-) type flash-memory storage system or other types.
The sense amplifier that the utility model embodiment provides and apply its storage system, on basis by the sense amplifier in prior art, between node and power supply, be connected a 5th PMOS pipe, the source electrode of the 5th PMOS pipe is connected with power supply, drain electrode is connected with its grid and node, in the situation that not increasing extra power consumption, can make the voltage of the node after sense amplifier has powered on have a definite magnitude of voltage, thereby can make the hopping amplitude of the voltage of the node before and after the 5th PMOS pipe conducting is also a definite value, can also reduce again the hopping amplitude of the voltage of node by suitably choosing the 5th PMOS pipe, thereby can reduce the shake due to the caused periphery signal of voltage jump of node.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Skilled person in the art will appreciate that the utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various obvious variations, readjust and substitute and can not depart from protection domain of the present utility model.Therefore, although the utility model is described in further detail by above embodiment, but the utility model is not limited only to above embodiment, in the situation that not departing from the utility model design, can also comprise more other equivalent embodiment, and scope of the present utility model is determined by appended claim scope.
Claims (6)
1. a sense amplifier, is characterized in that, comprising: a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe and the 5th PMOS pipe;
The grid of a described PMOS pipe is connected with first signal end, and source electrode connects power supply, and drain electrode is connected with the source electrode of described the 2nd PMOS pipe;
The drain electrode of described the 2nd PMOS pipe is connected with reference current input end, and grid is connected with the grid of its drain electrode and described the 3rd PMOS pipe;
The drain electrode of described the 3rd PMOS pipe is connected with output terminal, and source electrode is connected with the drain electrode of described the 4th PMOS pipe and the drain electrode of described the 5th PMOS pipe by node;
The grid of described the 4th PMOS pipe is connected with secondary signal end, and source electrode connects power supply;
The grid of described the 5th PMOS pipe is connected with its drain electrode, and source electrode connects power supply.
2. sense amplifier according to claim 1, is characterized in that, described first signal end is used for receiving first signal, and described secondary signal end is used for receiving secondary signal, and described reference current input end is used for receiving reference current.
3. sense amplifier according to claim 2, is characterized in that, in the process powering at described sense amplifier, described power supply charges to described node by described the 5th PMOS pipe;
After described sense amplifier has powered on, the threshold voltage of the voltage that the voltage of described node is described power supply and described the 5th PMOS pipe poor.
4. sense amplifier according to claim 3, is characterized in that, after described sense amplifier has powered on, the reference voltage that is applied to the grid of described the 2nd PMOS pipe and the grid of described the 3rd PMOS pipe equals the voltage of described power supply;
After described sense amplifier has powered on and in the time that described first signal is low level, a described PMOS pipe conducting, starts to set up described reference voltage according to the size of described reference current simultaneously;
After described reference voltage has been set up and in the time that described secondary signal is low level, described the 4th PMOS pipe conducting, the voltage of described node becomes the voltage of described power supply, makes described the 3rd PMOS pipe conducting, and sense amplifier is started working.
5. sense amplifier according to claim 4, is characterized in that, the threshold voltage of described the 2nd PMOS pipe equates with the threshold voltage of described the 3rd PMOS pipe, and the overdrive voltage of described the 2nd PMOS pipe is less than the threshold voltage of described the 5th PMOS pipe.
6. a storage system, described storage system comprises reference unit, storage unit and sense amplifier, the reference current input end of described sense amplifier is connected with described reference unit and the output terminal of described sense amplifier is connected with described storage unit, the size of the electric current that the electric current that described sense amplifier produces for more described reference unit and described storage unit produce, it is characterized in that, described sense amplifier is the sense amplifier described in any one in the claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420239372.5U CN203858866U (en) | 2014-05-12 | 2014-05-12 | Sense amplifier and storage system applying same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420239372.5U CN203858866U (en) | 2014-05-12 | 2014-05-12 | Sense amplifier and storage system applying same |
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| Publication Number | Publication Date |
|---|---|
| CN203858866U true CN203858866U (en) | 2014-10-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420239372.5U Withdrawn - After Issue CN203858866U (en) | 2014-05-12 | 2014-05-12 | Sense amplifier and storage system applying same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956179A (en) * | 2014-05-12 | 2014-07-30 | 北京兆易创新科技股份有限公司 | Sense amplifier and memory system using same |
-
2014
- 2014-05-12 CN CN201420239372.5U patent/CN203858866U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956179A (en) * | 2014-05-12 | 2014-07-30 | 北京兆易创新科技股份有限公司 | Sense amplifier and memory system using same |
| CN103956179B (en) * | 2014-05-12 | 2017-05-24 | 北京兆易创新科技股份有限公司 | Sense amplifier and memory system using same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20141001 Effective date of abandoning: 20170524 |