CN203827472U - Ground reception digital STB tuner circuit - Google Patents
Ground reception digital STB tuner circuit Download PDFInfo
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- CN203827472U CN203827472U CN201420244862.4U CN201420244862U CN203827472U CN 203827472 U CN203827472 U CN 203827472U CN 201420244862 U CN201420244862 U CN 201420244862U CN 203827472 U CN203827472 U CN 203827472U
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Abstract
The utility model relates to the digital STB technical field, and provides a ground reception digital STB tuner circuit comprising a tuner main chip UT2, an LC frequency selective network circuit, a difference transmission circuit, an automatic gain control circuit, a channel selection control circuit, a signal output circuit and a peripheral circuit; the LC frequency selective network circuit can improve the capability of receiving effective signals; a transformer of 0the difference transmission circuit respectively transmits a difference signal to a third base pin and a second base pin of the UT2, thereby preventing common mode signal interference and effectively limiting noise interferences; the automatic gain control circuit comprises a resistor RT2 and a capacitor CT5 connected in parallel, and is electrically connected with a sixth base pin AGC so as to prevent fading of a video signal; the channel selection control circuit forms a data control line and a clock output line; SDA and SCL form an I2C bus; the data is controlled to be outputted by the tuner main chip; the signal output circuit outputs the signal received from a reception antenna to a demodulation chip.
Description
Technical field
The utility model belongs to top box of digital machine technical field, relates in particular to a kind of ground and receives top box of digital machine high frequency tuner circuit.
Background technology
According to the transmission means of digital television signal, Digital Television can be divided into terrestrial DTV, satellite digital TV and cable digital TV.For the transmission of ground digital television signal, International Telecommunication Union has successively ratified four standard criterions, be the ATSC standard of the U.S., DVB-T standard, the ISDB-T standard of Japan and DTMB (the Digital Television Terrestrial Multimedia Broadcasting) standard of China in Europe, and Chinese DTMB standard is to use for reference on the basis of above-mentioned international three large digital television transfer standards, the terrestrial DTV transmission specification that independent research forms.
At present, ground digital television signal, in transmitting procedure, is easily subject to various interference and stops, effectively signal is cut down, and causes ground digital television signal not reach the designing requirement of terrestrial DTV SD set-top box device.
Utility model content
The purpose of this utility model is to provide a kind of ground to receive top box of digital machine high frequency tuner circuit, the Digital Television tuner that being intended to solve prior art provides receives digital television signal and is subject to various interference and stops, causes ground digital television signal not reach the problem of the designing requirement of terrestrial DTV SD set-top box device.
The utility model is to realize like this, a kind of ground receives top box of digital machine high frequency tuner circuit, described ground receives the peripheral circuit that top box of digital machine high frequency tuner circuit comprises tuner master chip UT2 and is electrically connected with described tuner master chip UT2 respective pin, described top box of digital machine high frequency tuner circuit also comprises LC frequency-selective network circuit, differential transmission circuit, automatic gain control circuit, channel selection control circuit and signal output apparatus, described differential transmission circuit, automatic gain control circuit, channel selection control circuit and signal output apparatus are electrically connected with described tuner master chip UT2 respective pin respectively, described LC frequency-selective network circuit is electrically connected with described differential transmission circuit, wherein:
Described LC frequency-selective network circuit comprises tuner reception antenna, the output electrical connection capacitor C T7 of described tuner reception antenna, the other end electrical connection inductance L T1 of described capacitor C T7, the other end of described inductance L T1 connects and connects respectively the inductance L T3 and the inductance L T4 that are connected in parallel;
Described differential transmission circuit comprises the capacitor C T15 being electrically connected with the output of described inductance L T3, the pin 3 of the other end electrical connection transformer TA1 of described capacitor C T15, pin 1 ground connection of described transformer TA1, pin 2 and pin 4 output difference sub-signals are to the 3rd pin LNA_INN and the 2nd pin LNA_INP of described tuner master chip UT2;
Described automatic gain control circuit comprises the resistance R T2 being electrically connected with the pin IF_AGC of demodulation chip, the other end of described resistance R T2 is electrically connected the 6th pin AGC of described tuner master chip UT2, the 6th pin AGC of described tuner master chip UT2 is also electrically connected capacitor C T5, the other end ground connection of described capacitor C T5, described capacitor C T5 and described resistance R T2 are connected in parallel;
Described channel selection control circuit comprises respectively pin SDA_TUN, resistance R T3 and the resistance R T4 that pin SCL_TUN is electrically connected with the GPIO mouth of Set Top Box master chip, the other end of described resistance R T3 is electrically connected the 17th pin SDA of described tuner master chip UT2, and the other end of described resistance R T4 is electrically connected the 16th pin SCL of described tuner master chip UT2;
Described signal output apparatus comprises the capacitor C T6 being electrically connected with the 7th pin IF_OUTP of described tuner master chip UT2 and the capacitor C T4 being electrically connected with the 8th pin IF_OUTN of described tuner master chip UT2, and the other end of described capacitor C T6 and capacitor C T4 is electrically connected respectively demodulation chip.
As a kind of improved plan, the other end electrical connection capacitor C T11 of described inductance L T4, the other end ground connection of described capacitor C T11.
As a kind of improved plan, the output electrical connection capacitor C T14 of the pin 2 of described transformer TA1, the other end of described capacitor C T14 is electrically connected the 3rd pin LNA_INN of described tuner master chip UT2.
As a kind of improved plan, the output electrical connection capacitor C T16 of the pin 4 of described transformer TA1, the other end of described capacitor C T16 is electrically connected the 2nd pin LNA_INP of described tuner master chip UT2.
Because receiving top box of digital machine high frequency tuner circuit, ground comprises tuner master chip UT2, LC frequency-selective network circuit, differential transmission circuit, automatic gain control circuit, channel selection control circuit and peripheral circuit, wherein:
Form LC frequency-selective network circuit by reception antenna, capacitor C T7, inductance L T1, inductance L T3 and inductance L T4, improve the ability of tuner reception useful signal;
The pin 2 of the transformer TA1 of differential transmission circuit and pin 4 are carried the 3rd pin LNA_INN from differential signal to tuner master chip UT2 and the 2nd pin LNA_INP respectively, prevent common-mode signal interference, effectively suppress the interference of noise to vision signal;
Automatic gain control circuit comprises the resistance R T2 and the capacitor C T5 that are connected in parallel, is then electrically connected in the lump the 6th pin AGC of tuner master chip UT2, thus automatic gain control prevent vision signal in transmitting procedure owing to stopping the decline causing;
Channel selection control circuit comprises resistance R T3 and resistance R T4, resistance R T3 is electrically connected the 17th pin SDA of described tuner master chip UT2, the other end of described resistance R T4 is electrically connected the 16th pin SCL of described tuner master chip UT2, the clock output line of the Data Control line of the 17th pin SDA composition of resistance R T3 and tuner master chip UT2 and the 16th pin SCL composition of resistance R T4 and tuner master chip UT2, SDA and SCL composition I
2c bus, controls data and is exported by tuner master chip;
Signal output apparatus comprises the capacitor C T6 being electrically connected with the 7th pin IF_OUTP of described tuner master chip UT2 and the capacitor C T4 being electrically connected with the 8th pin IF_OUTN of described tuner master chip UT2, the other end of described capacitor C T6 and capacitor C T4 is electrically connected respectively demodulation chip, completes the signal receiving from reception antenna is delivered to demodulation chip.
Brief description of the drawings
Fig. 1 is the structural representation that the ground that provides of the utility model receives top box of digital machine high frequency tuner circuit;
Fig. 2 is the circuit diagram that the ground that provides of the utility model receives top box of digital machine high frequency tuner circuit.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
Refer to Fig. 1 and Fig. 2, for convenience of explanation, in figure, only provided the part relevant to the utility model.
Ground receives the peripheral circuit that top box of digital machine high frequency tuner circuit comprises tuner master chip UT2 and is electrically connected with described tuner master chip UT2 respective pin, described top box of digital machine high frequency tuner circuit also comprises LC frequency-selective network circuit, differential transmission circuit, automatic gain control circuit, channel selection control circuit and signal output apparatus, described differential transmission circuit, automatic gain control circuit, channel selection control circuit and signal output apparatus are electrically connected with described tuner master chip UT2 respective pin respectively, described LC frequency-selective network circuit is electrically connected with described differential transmission circuit, wherein:
Described LC frequency-selective network circuit comprises tuner reception antenna, the output electrical connection capacitor C T7 of described tuner reception antenna, the other end electrical connection inductance L T1 of described capacitor C T7, the other end of described inductance L T1 connects and connects respectively the inductance L T3 and the inductance L T4 that are connected in parallel;
Described differential transmission circuit comprises the capacitor C T15 being electrically connected with the output of described inductance L T3, the pin 3 of the other end electrical connection transformer TA1 of described capacitor C T15, pin 1 ground connection of described transformer TA1, pin 2 and pin 4 output difference sub-signals are to the 3rd pin LNA_INN and the 2nd pin LNA_INP of described tuner master chip UT2;
Described automatic gain control circuit comprises the resistance R T2 being electrically connected with the pin IF_AGC of demodulation chip, the other end of described resistance R T2 is electrically connected the 6th pin AGC of described tuner master chip UT2, the 6th pin AGC of described tuner master chip UT2 is also electrically connected capacitor C T5, the other end ground connection of described capacitor C T5, described capacitor C T5 and described resistance R T2 are connected in parallel;
Described channel selection control circuit comprises respectively pin SDA_TUN, resistance R T3 and the resistance R T4 that pin SCL_TUN is electrically connected with the GPIO mouth of Set Top Box master chip, the other end of described resistance R T3 is electrically connected the 17th pin SDA of described tuner master chip UT2, and the other end of described resistance R T4 is electrically connected the 16th pin SCL of described tuner master chip UT2;
Described signal output apparatus comprises the capacitor C T6 being electrically connected with the 7th pin IF_OUTP of described tuner master chip UT2 and the capacitor C T4 being electrically connected with the 8th pin IF_OUTN of described tuner master chip UT2, and the other end of described capacitor C T6 and capacitor C T4 is electrically connected respectively demodulation chip.
In the utility model, as shown in Figure 2, the other end electrical connection capacitor C T11 of described inductance L T4, the other end ground connection of described capacitor C T11.
In the utility model, the output electrical connection capacitor C T14 of the pin 2 of described transformer TA1, the other end of described capacitor C T14 is electrically connected the 3rd pin LNA_INN of described tuner master chip UT2.
In the utility model, the output electrical connection capacitor C T16 of the pin 4 of described transformer TA1, the other end of described capacitor C T16 is electrically connected the 2nd pin LNA_INP of described tuner master chip UT2.
In the utility model, the clock output line of the Data Control line of the 17th pin SDA composition of resistance R T3 and tuner master chip UT2 and the 16th pin SCL composition of resistance R T4 and tuner master chip UT2, SDA and SCL composition I
2c bus, controls data and is exported by tuner master chip, particularly:
Set Top Box master chip does not have I
2c bus interface, its kernel is 51 series monolithics, utilizes 57 pin H_51P2[3 of Set Top Box master chip] for I
2clock line SCL, the 58 pin H_51P2[4 of C bus] for I
2the data wire SDA of C bus, utilizes these two lines to realize I
2the data of C bus send and status poll function, use function mode, process the configuration directly related with register downwards, and the interface method design driven program of configuration register is upwards provided for user;
Its control mode is utilized software to realize and is made channel control and select more flexible and convenient.
Certainly, in the utility model, in the circuit diagram shown in Fig. 2, also comprise other pins and corresponding electronic component, do not repeating at this, but not in order to limit the utility model.
In the utility model, digital terrestrial television signals receives through reception antenna, aerial signal is connected to the RF_IN input of tuner, tuner carries out useful signal frequency-selecting, differential signal transmission to digital television signal, Gain Automatic control and channel selection control, through IF_OUTP and the output of IF_OUTN pin of tuner, specific as follows:
Form LC frequency-selective network circuit by reception antenna, capacitor C T7, inductance L T1, inductance L T3 and inductance L T4, digital television signal is carried out to effective frequency-selecting, improve the ability of tuner reception useful signal;
The pin 2 of the transformer TA1 of differential transmission circuit and pin 4 are carried the 3rd pin LNA_INN from differential signal to tuner master chip UT2 and the 2nd pin LNA_INP respectively, prevent common-mode signal interference, effectively suppress the interference of noise to vision signal;
Automatic gain control circuit comprises the resistance R T2 and the capacitor C T5 that are connected in parallel, is then electrically connected in the lump the 6th pin AGC of tuner master chip UT2, thus automatic gain control prevent vision signal in transmitting procedure owing to stopping the decline causing;
Channel selection control circuit comprises resistance R T3 and resistance R T4, resistance R T3 is electrically connected the 17th pin SDA of described tuner master chip UT2, the other end of described resistance R T4 is electrically connected the 16th pin SCL of described tuner master chip UT2, the clock output line of the Data Control line of the 17th pin SDA composition of resistance R T3 and tuner master chip UT2 and the 16th pin SCL composition of resistance R T4 and tuner master chip UT2, SDA and SCL composition I
2c bus, controls data and is exported by tuner master chip;
Signal output apparatus comprises the capacitor C T6 being electrically connected with the 7th pin IF_OUTP of described tuner master chip UT2 and the capacitor C T4 being electrically connected with the 8th pin IF_OUTN of described tuner master chip UT2, the other end of described capacitor C T6 and capacitor C T4 is electrically connected respectively demodulation chip, completes the signal receiving from reception antenna is delivered to demodulation chip.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any amendments of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (4)
1. a ground receives top box of digital machine high frequency tuner circuit, described ground receives the peripheral circuit that top box of digital machine high frequency tuner circuit comprises tuner master chip UT2 and is electrically connected with described tuner master chip UT2 respective pin, it is characterized in that, described top box of digital machine high frequency tuner circuit also comprises LC frequency-selective network circuit, differential transmission circuit, automatic gain control circuit, channel selection control circuit and signal output apparatus, described differential transmission circuit, automatic gain control circuit, channel selection control circuit and signal output apparatus are electrically connected with described tuner master chip UT2 respective pin respectively, described LC frequency-selective network circuit is electrically connected with described differential transmission circuit, wherein:
Described LC frequency-selective network circuit comprises tuner reception antenna, the output electrical connection capacitor C T7 of described tuner reception antenna, the other end electrical connection inductance L T1 of described capacitor C T7, the other end of described inductance L T1 connects and connects respectively the inductance L T3 and the inductance L T4 that are connected in parallel;
Described differential transmission circuit comprises the capacitor C T15 being electrically connected with the output of described inductance L T3, the pin 3 of the other end electrical connection transformer TA1 of described capacitor C T15, pin 1 ground connection of described transformer TA1, pin 2 and pin 4 output difference sub-signals are to the 3rd pin LNA_INN and the 2nd pin LNA_INP of described tuner master chip UT2;
Described automatic gain control circuit comprises the resistance R T2 being electrically connected with the pin IF_AGC of demodulation chip, the other end of described resistance R T2 is electrically connected the 6th pin AGC of described tuner master chip UT2, the 6th pin AGC of described tuner master chip UT2 is also electrically connected capacitor C T5, the other end ground connection of described capacitor C T5, described capacitor C T5 and described resistance R T2 are connected in parallel;
Described channel selection control circuit comprises respectively pin SDA_TUN, resistance R T3 and the resistance R T4 that pin SCL_TUN is electrically connected with the GPIO mouth of Set Top Box master chip, the other end of described resistance R T3 is electrically connected the 17th pin SDA of described tuner master chip UT2, and the other end of described resistance R T4 is electrically connected the 16th pin SCL of described tuner master chip UT2;
Described signal output apparatus comprises the capacitor C T6 being electrically connected with the 7th pin IF_OUTP of described tuner master chip UT2 and the capacitor C T4 being electrically connected with the 8th pin IF_OUTN of described tuner master chip UT2, and the other end of described capacitor C T6 and capacitor C T4 is electrically connected respectively demodulation chip.
2. ground according to claim 1 receives top box of digital machine high frequency tuner circuit, it is characterized in that the other end electrical connection capacitor C T11 of described inductance L T4, the other end ground connection of described capacitor C T11.
3. ground according to claim 1 receives top box of digital machine high frequency tuner circuit, it is characterized in that, the output electrical connection capacitor C T14 of the pin 2 of described transformer TA1, the other end of described capacitor C T14 is electrically connected the 3rd pin LNA_INN of described tuner master chip UT2.
4. ground according to claim 1 receives top box of digital machine high frequency tuner circuit, it is characterized in that, the output electrical connection capacitor C T16 of the pin 4 of described transformer TA1, the other end of described capacitor C T16 is electrically connected the 2nd pin LNA_INP of described tuner master chip UT2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420244862.4U CN203827472U (en) | 2014-05-14 | 2014-05-14 | Ground reception digital STB tuner circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420244862.4U CN203827472U (en) | 2014-05-14 | 2014-05-14 | Ground reception digital STB tuner circuit |
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| Publication Number | Publication Date |
|---|---|
| CN203827472U true CN203827472U (en) | 2014-09-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420244862.4U Expired - Fee Related CN203827472U (en) | 2014-05-14 | 2014-05-14 | Ground reception digital STB tuner circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN203827472U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109788355A (en) * | 2018-12-18 | 2019-05-21 | 深圳市纽格力科技有限公司 | Set-top box and method based on live signal adjustment parameter |
| CN110312092A (en) * | 2018-03-27 | 2019-10-08 | 晨星半导体股份有限公司 | Channel scan device and channel scan method in satellite TV system |
-
2014
- 2014-05-14 CN CN201420244862.4U patent/CN203827472U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110312092A (en) * | 2018-03-27 | 2019-10-08 | 晨星半导体股份有限公司 | Channel scan device and channel scan method in satellite TV system |
| CN109788355A (en) * | 2018-12-18 | 2019-05-21 | 深圳市纽格力科技有限公司 | Set-top box and method based on live signal adjustment parameter |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHANDONG DONGSHENG ELECTRONIC LIMITED BY SHARE LTD Free format text: FORMER NAME: WEIFANG DONGSHENG ELECTRONIC CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 261061 No. 211, Golden Road, hi tech Zone, Shandong, Weifang Patentee after: Shandong limited company of Dong Sheng electronics group Address before: 261061 Software Park, No. 10179, healthy East Street, hi tech Zone, Shandong, Weifang, China, World Trade Center, six floors Patentee before: Weifang Dongsheng Electronic Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140910 Termination date: 20170514 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |