CN203825415U - Single-row auxiliary engine electrically operated gate logic circuit - Google Patents
Single-row auxiliary engine electrically operated gate logic circuit Download PDFInfo
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- CN203825415U CN203825415U CN201420189204.XU CN201420189204U CN203825415U CN 203825415 U CN203825415 U CN 203825415U CN 201420189204 U CN201420189204 U CN 201420189204U CN 203825415 U CN203825415 U CN 203825415U
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Abstract
A single-row auxiliary engine electrically operated gate logic circuit at least comprises an opening command circuit, a closing command circuit, a being opening indicating circuit, a being closing indicating circuit, an opening fault indicating circuit and a closing fault indicating circuit; the being opening indicating circuit at least comprises a being opening indicating lamp, a third logic OR gate circuit, a forth SR trigger, a twelfth logic AND gate circuit and an eleventh logic AND gate circuit; and the being closing indicating circuit at least comprises a being closing indicating lamp, a fifth logic OR gate circuit, a fifth SR trigger, a fourteenth logic AND gate circuit and a thirteenth logic AND gate circuit. The single-row auxiliary engine electrically operated gate logic circuit can solve the problems, which exist in the control of an electrically operated gate of a single-row auxiliary engine, that quantity production is difficult to realize and fault states monitoring and output are imperfect.
Description
Technical field
The application relates to the automatic control system in generating plant, especially a kind of single-row subsidiary engine Electrically operated gate logical circuit.
Background technology
In production run, have two large classes to control, a class is controlled for simulation, and a class is sequential control.
Sequential control only with the opening of equipment, stop, open and close are relevant.It is according to the conditions such as operating mode of the operating mode of production equipment and controlled device, according to the order of predetermining, goes to open, stops, open and close controlled device.In this class control system, the information of detection, computing and control use is all " 0 " and " 1 " two kinds of information.
In supercritical unit control system, along with the increase of unit capacity and the raising of parameter, the complexity of subsidiary engine quantity and therrmodynamic system increases greatly, sequence control system need to control the size numerous equipment and system, make the involvement aspect of this system very wide, have a large amount of input/output signals and logic judgement.
For the utility appliance of important power plant, the operation of system, although logical relation is simple, but opening, stopping in the important operations such as process and accident treatment at large-scale unit, operand is numerous, complex operation step, manual operation amount is large, and occurs unavoidably maloperation, affects unit safety operation.According to prior regulated procedure, under the driving of operational order, complete the opening of Controlling Auxiliaries in Power Plants, stop, automatic control and the operation of open and close, the task of sequence control system that Here it is.
A 600MW unit approximately has actuator more than the 300 platform covers such as subsidiary engine, Electrically operated gate, pneumatic door, and more than 800 operation item realizes by sequence control system that technological process ripe and that have a fixing operation step is carried out automatically controlling is a kind of inexorable trend.
Auxiliary operational system comprises that steam turbine assists operational system, as oxygen-eliminating device, steam trap, water pump etc.
The auxiliary operational system of boiler comprises that major pant item is air preheater, and blower fan, blower fan comprise induced draft fan, pressure fan, primary air fan etc.
The sequential control of utility appliance comprises controlling pressure fan, induced draft fan, air preheater, coal pulverizer, water circulating pump, feed pump, well heater etc., and its related system is as air and flue system, pulverized coal preparation system, and circulation, water supply system all can adopt sequential control.
The advantage of the single-row configuration of subsidiary engine: reduce cost, reduced number of devices, baffle plate has been cancelled in the outlet of induced draft fan and pressure fan, and air and flue system is simplified greatly.When single-row configuration primary air fan can be avoided biserial configuration, pressure head is large, the feature that flow is little, so primary air fan when its efficiency will configure higher than biserial, when underrun, odds for effectiveness is more obvious; The air leak rate of air curtain of air preheater is relevant with its girth, and the air leak rate of air curtain of the air preheater of single-row configuration configures air preheater lower than biserial.
The integrity problem of the single-row configuration of boiler accessory machinery and the impact that unit is caused are generally relatively paid close attention to.The non-number of times that stops that auxiliary machinery fault causes may increase.Unit Commitment number of times increases affects the life-span.Subsidiary engine maintenance can only be carried out when shutting down.
After the single-row configuration of subsidiary engine, single-row fault can cause compressor emergency shutdown.So control system is proposed to requirements at the higher level after the single-row configuration of subsidiary engine.
Traditional Electrically operated gate indication point is exactly several information such as standard-sized sheet, complete shut-down, electric fault, distant place control, and the how nonstandard change of logic of existing Electrically operated gate, varies with each individual, and is difficult to realize batch production; The supervision output imperfection of malfunction, for example, may only have open and close fault and not open indication, close indication.
Utility model content
In order to address the above problem, the utility model provides single-row subsidiary engine ultra supercritical 660MW unit Electrically operated gate standard logical devices, and the state indication logic of perfect Electrically operated gate, can realize the supervision of intermediateness, realize the standardization of steering logic, contributed to batch production.
A single-row subsidiary engine Electrically operated gate logical circuit, at least comprises out command circuit, closes command circuit, drives indicating circuit, closes indicating circuit, opens failure indicating circuit, closes failure indicating circuit;
Driving indicating circuit at least comprises:
Opening pilot lamp;
The 3rd logic sum gate circuit, first input end connects the output terminal of described pass command circuit, and the 3rd input end receives valve wide open signal;
The 4th set-reset flip-floop, R end connects the output terminal of described the 3rd logic sum gate circuit, opens the output terminal of command circuit described in S end connects, and opens the input end of failure indicating circuit described in output terminal I connects;
The 12 logical AND gate circuit, opens the output terminal of failure indicating circuit described in the second input end connects, first input end confirmation of receipt signal, and output terminal connects the second input end of described the 3rd logic sum gate circuit;
The 11 logical AND gate circuit, first input end is connected with the output terminal I of described the 4th set-reset flip-floop, and the second input end receives the negate signal of valve complete shut-down signal, described in output terminal connects, is opening pilot lamp;
Closing indicating circuit at least comprises:
Closing pilot lamp;
The 5th logic sum gate circuit, opens the output terminal of command circuit described in first input end connects, the 3rd input end receives valve complete shut-down signal;
The 5th set-reset flip-floop, R end connects the output terminal of described the 3rd logic sum gate circuit, opens the output terminal of command circuit described in S end connects, and opens the input end of failure indicating circuit described in output terminal I connects;
The 14 logical AND gate circuit, opens the output terminal of failure indicating circuit, first input end confirmation of receipt signal described in the second input end connects; Output terminal connects the second input end of described the 5th logic sum gate circuit;
The 13 logical AND gate circuit, first input end is connected with the output terminal I of described the 5th set-reset flip-floop, and the second input end receives the negate signal of valve wide open signal, described in output terminal connects, is closing pilot lamp.
Alternatively, also comprise hang-up and solution extension circuit, described hang-up and solution extension circuit are used for generating hang-up or solution extension signal, and hang-up and solution extension circuit output end are at least to described command circuit, pass command circuit conveying hang-up or the solution extension signal opened.
Alternatively, described hang-up at least comprises the first set-reset flip-floop, hangs up pilot lamp with solution extension circuit;
Described the first set-reset flip-floop, the first output of output terminal I is used for to opening command circuit, pass command circuit output hang-up and solution extension signal, and pilot lamp is hung up in the second output connection of output terminal I;
R termination is received to separate and is hung signal, and S termination is received pending signal.
Alternatively, described hang-up also comprises the 9th logic sum gate circuit, the tenth logic sum gate circuit, the 7th pulse generating circuit, the 8th pulse generating circuit with solution extension circuit;
Described the 9th logic sum gate circuit, first input end connects the output terminal of described the 7th pulse generating circuit, and the second input end receives manual pending signal, and output terminal connects the S end of described the first set-reset flip-floop;
The input end of described the 7th pulse generating circuit receives the pending signal that external circuit sends;
Described the tenth logic sum gate circuit, first input end connects the output terminal of described the 8th pulse generating circuit, and the second input end receives to separate hangs signal, and output terminal connects the R end of described the first set-reset flip-floop;
The input end of described the 8th pulse generating circuit receives the solution extension signal that external circuit sends;
Alternatively, described in, opening command circuit at least comprises the first logic sum gate circuit, the first logical AND gate circuit, the second logical AND gate circuit, the 3rd logical AND gate circuit, the 4th logical AND gate circuit, opens permission pilot lamp;
The first logical AND gate circuit, first input end receives single operation and opens request signal, and the second input end receives opens permission signal, and allows pilot lamp to be connected with opening, and output terminal connects the first input end of the first logic sum gate circuit;
The second logical AND gate circuit, first input end reception sequence is opened signal, the second input end receives and opens permission signal, and output terminal connects the second input end of the first logic sum gate circuit;
The 3rd logical AND gate circuit, first input end receives interlocking and opens signal, and the second input end receives and opens permission signal, and output terminal connects the 3rd input end of the first logic sum gate circuit;
The four-input terminal of described the first logic sum gate circuit receives protection and opens signal;
The 4th logical AND gate circuit, first input end connects the output terminal of the first logic sum gate circuit, and the second input end receive to be hung up and is separated the negate signal of hanging signal, and what output terminal connected outside delay circuit opens order end;
Described pass command circuit at least comprises the 5th logical AND gate circuit, the 6th logical AND gate circuit, the 7th logical AND gate circuit, the 8th logical AND gate circuit, the second logic sum gate circuit, closes permission pilot lamp;
The 5th logical AND gate circuit, request signal is closed in first input end reception single operation, and the second input end receives to close and allows signal, and allows pilot lamp to be connected with pass, and output terminal connects the first input end of the second logic sum gate circuit;
The 6th logical AND gate circuit, first input end receives sequence and closes signal, and the second input end receives to close and allows signal, and output terminal connects the second input end of the second logic sum gate circuit;
The 7th logical AND gate circuit, first input end receives interlocking and closes signal, and the second input end receives to close and allows signal, and output terminal connects the 3rd input end of the second logic sum gate circuit;
The four-input terminal of described the second logic sum gate circuit receives protection and closes signal;
The 8th logical AND gate circuit, first input end connects the output terminal of the second logic sum gate circuit, and the second input end receives to be hung up and separates the negate signal of hanging signal, and output terminal connects the pass order end of outside delay circuit.
Alternatively, described in, opening command circuit also comprises:
The first pulse generating circuit, opens request signal for receiving single operation, produces trigger pulse, and output terminal connects the first input end of the first logical AND gate circuit;
The second pulse generating circuit, for receiving sequence, open request signal, produce trigger pulse, output terminal connects the first input end of the second logical AND gate circuit;
The 3rd pulse generating circuit, for receiving interlocking, open request signal, produce trigger pulse, output terminal connects the first input end of the 3rd logical AND gate circuit;
Described pass command circuit also comprises:
The 4th pulse generating circuit, for receiving single operation, close request signal, produce trigger pulse,
Output terminal connects the first input end of the 5th logical AND gate circuit;
The 5th pulse generating circuit, for receiving sequence, close request signal, produce trigger pulse, output terminal connects the first input end of the 6th logical AND gate circuit;
The 6th pulse generating circuit, for receiving interlocking, close request signal, produce trigger pulse, output terminal connects the first input end of the 7th logical AND gate circuit.
Alternatively, open command circuit and also comprise the 9th pulse generating circuit, the 11 logic sum gate circuit;
Described the 9th pulse generating circuit, input end receives the single operation of external circuit input and opens request signal, and output terminal connects the second input end of described the 11 logic sum gate circuit; Described the 11 logic sum gate circuit, first input end receives manual single operation and opens request signal, and output terminal connects the input end of described the first pulse generating circuit;
Close command circuit and also comprise the tenth pulse generating circuit, the 12 logic sum gate circuit;
Described the tenth pulse generating circuit, input end receives the single operation pass request signal that external circuit sends, output terminal connects the second input end of described the 12 logic sum gate circuit, described the 12 logic sum gate circuit, first input end receives single operation and closes request signal, and output terminal connects the input end of described the 4th pulse generating circuit.
Alternatively, the described indicating circuit of opening also comprises the 4th logic inverter circuit, and for by described valve complete shut-down signal negate computing, input end receives valve complete shut-down signal, and output terminal connects described the 11 logical AND gate circuit the second input end;
The described indicating circuit that closing also comprises the 5th logic inverter circuit, and for by described valve wide open signal negate computing, input end receives valve wide open signal, and output terminal connects described the 13 logical AND gate circuit the second input end.
Alternatively, also comprise protection start make indicating circuit, action indicating circuit is closed in protection;
Described protection is started and is made indicating circuit and at least comprise that protection opens action indicator, the second set-reset flip-floop, the 9th logical AND gate circuit, the 15 logical AND gate circuit;
Described the 9th logical AND gate circuit, first input end receives to be hung up and separates the negate signal of hanging signal; The second input end receives protection and opens actuating signal, and output terminal connects the S end of described the second set-reset flip-floop;
Described the second set-reset flip-floop, output terminal I output protection is opened actuating signal, the first output connects protection and opens action indicator, the second output connects the second input end of described the 15 logical AND gate circuit, R end connects the output terminal of the 15 logical AND gate circuit, the first input end confirmation of receipt signal of described the 15 logical AND gate circuit;
Described protection is closed action indicating circuit and is at least comprised protection pass action indicator, Three S's R trigger, the tenth logical AND gate circuit, the 16 logical AND gate circuit;
Described the tenth logical AND gate circuit, first input end receives to be hung up and separates the negate signal of hanging signal; The second input end receives protection and closes actuating signal, and output terminal connects the S end of described Three S's R trigger;
Described Three S's R trigger; output terminal I output protection closes actuating signal; the first output connects protection and closes action indicator; the second output connects the second input end of described the 16 logical AND gate circuit; R end connects the output terminal of described the 16 logical AND gate circuit, the first input end confirmation of receipt signal of described the 16 logical AND gate circuit.
Alternatively, described protection is started and is made indicating circuit and also comprise the 11 pulse generating circuit, described the 11 pulse generating circuit, and input end receives protection and opens actuating signal, and output terminal connects the second input end of described the 9th logical AND gate circuit;
Described protection is closed action indicating circuit and is also comprised twelve-pulse circuit for generating, described twelve-pulse circuit for generating, and input end receives protection and closes actuating signal, and output terminal connects the second input end of described the tenth logical AND gate circuit,
Alternatively, also comprise the first logic inverter circuit, for the output signal negate that described hang-up and solution are hung to circuit,
Described the first logic inverter circuit, input end receives to be hung up and separates the output signal of hanging circuit,
The first output of output terminal connects the first input end of the 4th logical AND gate circuit of opening command circuit;
The second output of output terminal connects the first input end of the 8th logical AND gate circuit that closes command circuit;
The 3rd output of output terminal connects the first input end that the 9th logical AND gate circuit of making indicating circuit is started in protection;
The 4th output of output terminal connects the first input end that the tenth logical AND gate circuit of action indicating circuit is closed in protection.
Alternatively, described confirmation signal is by confirming that circuit produces;
Described confirmation circuit at least comprises the first pulse generating circuit, the 4th logic sum gate circuit; The input end of described the first pulse generating circuit receives distant place confirmation signal, and output terminal connects the first input end of the 4th logic sum gate circuit, and the second input end of described the 4th logic sum gate circuit receives manual confirmation signal;
The output terminal of described the 4th logic sum gate circuit,
The first output connects the first input end that the 15 logical AND gate circuit of making indicating circuit is started in protection;
The second output connects the first input end that the 16 logical AND gate circuit of action indicating circuit is closed in protection;
The 3rd output connects the first input end of the 12 logical AND gate circuit of driving indicating circuit;
The 4th output connects the first input end of the 14 logical AND gate circuit that is closing indicating circuit.
Alternatively, the described indicating circuit of opening also comprises the 4th logic inverter circuit, for by the negate of valve complete shut-down signal;
Described the 4th logic inverter circuit, input end receives valve complete shut-down signal, and output terminal is connected with the second input end of described the 11 logical AND gate circuit;
The described indicating circuit that closing also comprises the 5th logic inverter circuit, for by the negate of valve wide open signal;
Described the 5th logic inverter circuit, input end receives valve wide open signal, and output terminal is connected with the second input end of described the 13 logical AND gate circuit.
Alternatively, also comprise that fault shows "Σ" logic circuit;
Described fault shows that "Σ" logic circuit at least comprises the 6th logic sum gate circuit, electric fault pilot lamp, opens malfunction indicator lamp, closes malfunction indicator lamp, input and output I/O faulty circuit, fault show and gather pilot lamp, the first delay circuit, the second delay circuit;
The output terminal of described the 6th logic sum gate circuit connects fault and gathers pilot lamp;
Described the first delay circuit of opening faulty circuit, the second output of output terminal connects opens malfunction indicator lamp, and the 3rd output of output terminal connects the second input end of described the 6th logic sum gate circuit;
The described malfunction indicator lamp of opening is connected with the second input end of described the 6th logic sum gate circuit;
The second delay circuit of described pass faulty circuit, the second output of output terminal connects described pass malfunction indicator lamp,
The 3rd output of output terminal connects the 3rd input end of described the 6th logic sum gate circuit;
Closing malfunction indicator lamp is connected with the 3rd input end of described the 6th logic sum gate circuit.
Described input and output I/O faulty circuit at least comprises input and output I/O malfunction indicator lamp, the 7th logic sum gate circuit;
The input and output I/O malfunction indicator lamp of described input and output I/O faulty circuit connects described the 6th logic sum gate circuit four-input terminal;
Described the 7th logic sum gate circuit, output terminal the first output connects described the 6th logic sum gate circuit four-input terminal, and output terminal the second output connects described input and output I/O malfunction indicator lamp.
Alternatively, described input and output I/O faulty circuit also comprises the 3rd delay circuit, the 17 logical AND gate circuit, the 18 logical AND gate circuit, the second logic inverter circuit, the 3rd logic inverter circuit, the first quality decision gate circuit, the second quality decision gate circuit;
Described the 7th logic sum gate circuit, first input end connects the output terminal of the 3rd delay circuit, and the second input end connects the output terminal of the 17 logical AND gate circuit, and the 3rd input end connects the output terminal of the 8th logic sum gate circuit;
The input end of described the 3rd delay circuit connects the output terminal of the 18 logical AND gate circuit;
Described the 18 logical AND gate circuit, first input end connects the output terminal of the second logic inverter circuit, and the second input end connects the output terminal of the 3rd logic inverter circuit;
The input end of described the second logic inverter circuit receives valve wide open signal;
The input end of described the 3rd logic inverter circuit receives valve complete shut-down signal;
Described the 17 logical AND gate circuit, first input end receives valve wide open signal, and the second input end receives valve complete shut-down signal;
Described the 8th logic sum gate circuit, first input end connects the output terminal of the first quality decision gate circuit, and the second input end connects the output terminal of the second quality decision gate circuit;
The input end of described the first quality decision gate circuit receives valve wide open signal;
The input end of described the second quality decision gate circuit receives valve complete shut-down signal.
The utility model improves traditional Electrically operated gate logic circuit structure, can solve in the control of Electrically operated gate of current single-row subsidiary engine, exist be difficult to realize batch production, malfunction monitors the incomplete problem of output.
Accompanying drawing explanation
Fig. 1 is circuit connecting relation schematic diagram of the present utility model;
Fig. 2 is structural representation block diagram of the present utility model.
Embodiment
Below in conjunction with drawings and Examples, the technical solution of the utility model is described in detail.
First, in the sequence program of power plant, often use following logic and device.
Logical OR computing truth table:
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Logical OR operation expression: Y=A+B
Logic and operation truth table
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Logic and operation expression formula: Y=AB
Set-reset flip-floop claims again SR latch, is the simplest trigger flip-flop, and trigger flip-flop is conventional storage unit, and it can store 1 bit binary data.Trigger flip-flop has two stable states, " 0 " state and one state, in the situation that there is no outer signals, these two states can remain unchanged, once and have suitable outer signals to do the used time, these two states can be changed mutually.
There are two input signal ends, S, R; Have two output terminals, when trigger is normally worked, the state of these two output terminals is reciprocal.
In basic set-reset flip-floop, there is no clock signal, output state directly changes with the variation of input signal, and the interval of existing state and next state is not obvious, in reality, uses seldom separately.On the basis of basic set-reset flip-floop, increase a clock signal for synchro control and just formed synchronous set-reset flip-floop, for fear of within a clock period, there is upset twice or phenomenon repeatedly in flip-flop states, on the basis of synchronizer trigger, has designed master-slave flip-flop.
When Clock pulse CP is 0, no matter S, R input signal are 0 or 1, and output is 1, SR and is equivalent to be blocked by CP.When CP is 1, CP removes the blockade of input end S, R.
Set-reset flip-floop is the preferential trigger that resets.
| S | 0 | 1 | 0 | 1 |
| R | 0 | 0 | 1 | 1 |
| Output | Keep | 1 | 0 | 0 |
Middle delay circuit is opened, and Electrically operated gate is opened, and middle delay circuit cuts out, and Electrically operated gate is closed.
A single-row subsidiary engine Electrically operated gate logical circuit, concrete circuit connects as shown in Figure 1, wherein each element and between connection will below specifically describe.
Structure after described circuit is divided according to function as shown in Figure 2, at least comprises out command circuit, closes command circuit, drives indicating circuit, closes indicating circuit, opens failure indicating circuit, closes failure indicating circuit;
Driving indicating circuit at least comprises:
Opening pilot lamp;
The 3rd logic sum gate circuit, first input end connects the output terminal of described pass command circuit, and the 3rd input end receives valve wide open signal;
The 4th set-reset flip-floop, R end connects the output terminal of described the 3rd logic sum gate circuit, opens the output terminal of command circuit described in S end connects, and opens the input end of failure indicating circuit described in output terminal I connects;
The 12 logical AND gate circuit, opens the output terminal of failure indicating circuit described in the second input end connects, first input end confirmation of receipt signal, and output terminal connects the second input end of described the 3rd logic sum gate circuit;
The 11 logical AND gate circuit, first input end is connected with the output terminal I of described the 4th set-reset flip-floop, and the second input end receives the negate signal of valve complete shut-down signal, described in output terminal connects, is opening pilot lamp;
Closing indicating circuit at least comprises:
Closing pilot lamp;
The 5th logic sum gate circuit, opens the output terminal of command circuit described in first input end connects, the 3rd input end receives valve complete shut-down signal;
The 5th set-reset flip-floop, R end connects the output terminal of described the 3rd logic sum gate circuit, opens the output terminal of command circuit described in S end connects, and opens the input end of failure indicating circuit described in output terminal I connects;
The 14 logical AND gate circuit, opens the output terminal of failure indicating circuit, first input end confirmation of receipt signal described in the second input end connects; Output terminal connects the second input end of described the 5th logic sum gate circuit;
The 13 logical AND gate circuit, first input end is connected with the output terminal I of described the 5th set-reset flip-floop, and the second input end receives the negate signal of valve wide open signal, described in output terminal connects, is closing pilot lamp.
It should be noted that the utility model is also provided with many pulse generating circuits, when pulse generating circuit receives associative operation signal, production burst, pulse can arrange certain hour length, and such as arranging 2 seconds or other time value, concrete adjusts according to engineering practice.
Why pulse generating circuit be set be because:
When operating or interlocking signal is too short, in sampling process, these data are easily lost, and cause logic tripping.
When operating or interlocking signal is long, can cause final output to hold instruction (or closing instruction) and keep long high level always, and then make contrary pass instruction cannot send (or opening instruction), this is danger close under emergency work condition.
So pulse generating circuit is set, when associative operation signal is arrived in reception of impulse, take-off, becomes high level from low level, and the time width of pulse is arranged to be conducive to most the time that subsequent logic gate circuit carries out computing.
Such as being arranged to for 2 seconds, for follow-up logic gate, carry out logical operation and react, it is enough.
Certainly, do not get rid of and also have other more suitably set of times.
Also comprise hang-up and solution extension circuit, described hang-up and solution extension circuit are used for generating hang-up or solution extension signal, and hang-up and solution extension circuit output end are at least to described command circuit, pass command circuit conveying hang-up or the solution extension signal opened.
Hang up with solution extension circuit and at least comprise the first set-reset flip-floop, hang up pilot lamp;
Described the first set-reset flip-floop, the first output of output terminal I is used for to opening command circuit, pass command circuit output hang-up and solution extension signal, and pilot lamp is hung up in the second output connection of output terminal I;
R termination is received to separate and is hung signal, and S termination is received pending signal.
Hang up function: when operator presses hang-up button, pending signal is high level, be input to the S end of set-reset flip-floop, now, set-reset flip-floop output high level, hangs up pilot lamp bright.
Separate and hang function: when operator presses to separate, hang button, now separating and hanging signal is high level, is input to the R end of the first set-reset flip-floop after logical OR computing, now, the first set-reset flip-floop output low level, hangs up pilot lamp and goes out.
Hang up with solution extension circuit and also comprise the 9th logic sum gate circuit, the tenth logic sum gate circuit, the 7th pulse generating circuit, the 8th pulse generating circuit;
Described the 9th logic sum gate circuit, first input end connects the output terminal of described the 7th pulse generating circuit, and the second input end receives pending signal, and output terminal connects the S end of described the first set-reset flip-floop;
Described the tenth logic sum gate circuit, first input end connects the output terminal of described the 8th pulse generating circuit, and the second input end receives manual solution and hangs signal, and output terminal connects the R end of described the first set-reset flip-floop.
The input end of the 8th pulse generating circuit receives the solution extension signal that external circuit sends.
Separate extension circuit and can receive manual solution extension signal, also can receive the solution extension signal that external circuit sends.
When the 7th pulse generating circuit, the 8th pulse generating circuit receive coherent signal, take-off becomes high level lasting time from low level can be set to for 2 seconds, after 2 seconds, from high level, became low level;
The described command circuit of opening at least comprises the first logic sum gate circuit, the first logical AND gate circuit, the second logical AND gate circuit, the 3rd logical AND gate circuit, the 4th logical AND gate circuit, opens permission pilot lamp;
The first logical AND gate circuit, first input end receives single operation and opens request signal, and the second input end receives opens permission signal, and allows pilot lamp to be connected with opening, and output terminal connects the first input end of the first logic sum gate circuit;
The second logical AND gate circuit, first input end reception sequence is opened signal, the second input end receives and opens permission signal, and output terminal connects the second input end of the first logic sum gate circuit;
The 3rd logical AND gate circuit, first input end receives interlocking and opens signal, and the second input end receives and opens permission signal, and output terminal connects the 3rd input end of the first logic sum gate circuit;
The four-input terminal of described the first logic sum gate circuit receives protection and opens signal;
The 4th logical AND gate circuit, first input end connects the output terminal of the first logic sum gate circuit, and the second input end receive to be hung up and is separated the negate signal of hanging signal, and what output terminal connected outside relay opens order end;
Open permission signal: open and allow signal one road to be directly inputted to out permission pilot lamp, another road opens with single operation respectively that request signal, sequence are opened signal, interlocking is opened signal and carried out and computing.
Single operation open request signal, sequence open signal, interlocking open signal respectively with open allow signal carry out with computing after, then open signal with protection and carry out logical OR computing, be transferred to out order afterwards, open auxiliary reclay.
Single operation is opened request signal, sequence and is opened signal, interlocking and open signal and first must be respectively allow signal to carry out and computing with opening, when opening while allowing signal to be low level, single operation is opened request signal, sequence and is opened signal, interlocking and open signal and open that to allow signal to carry out with the result of computing be low level, that is to say, when not opening permission signal, request signal is opened in single operation, sequence is opened signal, interlocked and open signal conductively-closed;
When opening while allowing signal to be high level, single operation is opened request signal, sequence and is opened signal, interlocking and open signal and allow signal to carry out result with computing to depend on that single operation opens that request signal, sequence are opened signal, interlocking is opened signal with opening respectively;
That is to say, when having out while allowing signal, single operation opens that request signal, sequence are opened signal, interlocking is opened signal and enabled.
Further; the single operation request of opening, sequence open, interlocking to open respectively allows signal to carry out after logic and operation, opens signal again carry out logical OR computing with protection with opening; carry out and computing with the negate signal of hanging up, solution is hung through the first set-reset flip-floop output signal afterwards, be designated as signal A.Signal A is transferred to out order end, and when signal A is high level, auxiliary reclay is opened.
When hanging up, the first set-reset flip-floop output high level, becomes low level after negate computing, to the single operation request of opening, sequence open, interlock out, protect out relevant signal carry out with computing after output low level,
That is to say, during hang-up, pending signal has shielded opens the function that permission, the single operation request of opening, sequence are opened, interlocked out, protect out.
Separate while hanging, the first set-reset flip-floop output low level, becomes high level after negate computing;
Open order and depend on out that allowing signal, single operation to open request signal, sequence opens signal, interlocking and open the control that signal, protection are opened signal.
That is to say, while separate hanging, separate and hang signal and enabled to open and allow signal, single operation to open request signal, sequence to open signal, interlocking and open the function that signal, protection are opened signal.
Described pass command circuit at least comprises the 5th logical AND gate circuit, the 6th logical AND gate circuit, the 7th logical AND gate circuit, the 8th logical AND gate circuit, the second logic sum gate circuit, closes permission pilot lamp;
The 5th logical AND gate circuit, request signal is closed in first input end reception single operation, and the second input end receives to close and allows signal, and allows pilot lamp to be connected with pass, and output terminal connects the first input end of the second logic sum gate circuit;
The 6th logical AND gate circuit, first input end receives sequence and closes signal, and the second input end receives to close and allows signal, and output terminal connects the second input end of the second logic sum gate circuit;
The 7th logical AND gate circuit, first input end receives interlocking and closes signal, and the second input end receives to close and allows signal, and output terminal connects the 3rd input end of the second logic sum gate circuit;
The four-input terminal of described the second logic sum gate circuit receives protection and closes signal;
The 8th logical AND gate circuit, first input end connects the output terminal of the second logic sum gate circuit, and the second input end receives to be hung up and separates the negate signal of hanging signal, and output terminal connects the pass order end of outside relay.
Close permission signal: pass allows signal one road to be directly inputted to pass and allows pilot lamp, carry out and computing with single operation pass request signal, sequence pass signal, interlocking pass signal respectively on another road.
Single operation close request signal, sequence close signal, interlocking close signal respectively with close allow signal carry out with computing after, then close signal with protection and carry out logical OR computing, be transferred to afterwards and close order, close auxiliary reclay.
Request signal is closed in single operation, sequence is closed signal, interlocking pass signal and first must be allowed signal to carry out and computing with pass respectively, when pass allows signal to be low level, it is low level that single operation pass request signal, sequence pass signal, interlocking pass signal carry out with the result of computing with pass permission signal, that is to say, when not closing permission signal, request signal is closed in single operation, sequence is closed signal, interlocked and close signal conductively-closed;
When pass permission signal is high level, single operation is closed request signal, sequence pass signal, interlocking pass signal and is allowed signal to carry out depending on that with the result of computing single operation pass request signal, sequence are closed signal, the pass signal of interlocking with pass respectively;
That is to say, when relevant permission signal, single operation pass request signal, sequence are closed signal, interlocking closes signal and enables.
Further, the single operation request of closing, sequence are closed, interlocking closes respectively allows signal to carry out after logic and operation, closes signal again carries out logical OR computing with protection with closing, afterwards with hang up and separate the negate signal of hanging output signal and carry out and computing, be designated as signal B.Signal B is transferred to and closes order end, and when signal B is high level, auxiliary reclay cuts out.
When hanging up, the first set-reset flip-floop output high level, becomes low level after negate computing, close to single operation that request, sequence are closed, interlocking closes, protection close relevant signal carry out with computing after output low level,
That is to say, during hang-up, pending signal has shielded and has closed permission, the request of single operation pass, sequence pass, interlocking pass, protected the function of closing.
Separate while hanging, the first set-reset flip-floop output low level, becomes high level after negate computing;
Close order and depend on that pass allows signal, single operation pass request signal, sequence to close the control of signal, interlocking pass signal, protection pass signal.
That is to say, when solution is hung, solution extension signal has enabled pass permission signal, single operation is closed request signal, sequence pass signal, the pass signal of interlocking, protected the function of closing signal.
Alternatively, described in, opening command circuit also comprises:
The first pulse generating circuit, opens request signal for receiving single operation, produces trigger pulse, and output terminal connects the first input end of the first logical AND gate circuit;
The second pulse generating circuit, for receiving sequence, open request signal, produce trigger pulse, output terminal connects the first input end of the second logical AND gate circuit;
The 3rd pulse generating circuit, for receiving interlocking, open request signal, produce trigger pulse, output terminal connects the first input end of the 3rd logical AND gate circuit;
Described pass command circuit also comprises:
The 4th pulse generating circuit, for receiving single operation, close request signal, produce trigger pulse,
Output terminal connects the first input end of the 5th logical AND gate circuit;
The 5th pulse generating circuit, for receiving sequence, close request signal, produce trigger pulse, output terminal connects the first input end of the 6th logical AND gate circuit;
The 6th pulse generating circuit, for receiving interlocking, close request signal, produce trigger pulse, output terminal connects the first input end of the 7th logical AND gate circuit.
The first pulse generating circuit, the second pulse generating circuit, the 3rd pulse generating circuit, the 4th pulse generating circuit, the 5th pulse generating circuit, the 6th pulse generating circuit, while receiving coherent signal, take-off becomes high level from low level, burst length continued for 2 seconds, and after 2 seconds, high level becomes low level.
Alternatively, described in, open command circuit and also comprise the 9th pulse generating circuit, the 11 logic sum gate circuit;
Described the 9th pulse generating circuit, request signal is opened in the single operation that input end reception external circuit sends, and output terminal connects the second input end of described the 11 logic sum gate circuit; Described the 11 logic sum gate circuit, first input end receives manual single operation and opens request signal, and output terminal connects the input end of described the first pulse generating circuit;
Single operation is opened request signal and can, by manually producing, also can be produced by outside.
Close command circuit and also comprise the tenth pulse generating circuit, the 12 logic sum gate circuit;
Described the tenth pulse generating circuit, input end receives the single operation pass request signal that external circuit sends, output terminal connects the second input end of described the 12 logic sum gate circuit, described the 12 logic sum gate circuit, first input end receives manual single operation and closes request signal, and output terminal connects the input end of described the 4th pulse generating circuit.
Single operation is closed request signal and can, by manually producing, also can be produced by outside.
When the 9th pulse generating circuit, the tenth pulse generating circuit receive coherent signal, take-off becomes high level from low level, and the burst length continued for 2 seconds, and after 2 seconds, high level becomes low level.
Alternatively, the described indicating circuit of opening also comprises the 4th logic inverter circuit, and for by described valve complete shut-down signal negate computing, input end receives valve complete shut-down signal, and output terminal connects described the 11 logical AND gate circuit the second input end;
The described indicating circuit that closing also comprises the 5th logic inverter circuit, and for by described valve wide open signal negate computing, input end receives valve wide open signal, and output terminal connects described the 13 logical AND gate circuit the second input end.
Alternatively, also comprise protection start make indicating circuit, action indicating circuit is closed in protection;
Described protection is started and is made indicating circuit and at least comprise that protection opens action indicator, the second set-reset flip-floop, the 9th logical AND gate circuit, the 15 logical AND gate circuit;
Described the 9th logical AND gate circuit, first input end receives to be hung up and separates the negate signal of hanging signal; The second input end receives protection and opens actuating signal, and output terminal connects the S end of described the second set-reset flip-floop;
Described the second set-reset flip-floop, output terminal I output protection is opened actuating signal, the first output connects protection and opens action indicator, the second output connects the second input end of described the 15 logical AND gate circuit, R end connects the output terminal of the 15 logical AND gate circuit, the first input end confirmation of receipt signal of described the 15 logical AND gate circuit;
Described protection is closed action indicating circuit and is at least comprised protection pass action indicator, Three S's R trigger, the tenth logical AND gate circuit, the 16 logical AND gate circuit;
Described the tenth logical AND gate circuit, first input end receives to be hung up and separates the negate signal of hanging signal; The second input end receives protection and closes actuating signal, and output terminal connects the S end of described Three S's R trigger;
Described Three S's R trigger; output terminal I output protection closes actuating signal; the first output connects protection and closes action indicator; the second output connects the second input end of described the 16 logical AND gate circuit; R end connects the output terminal of described the 16 logical AND gate circuit, the first input end confirmation of receipt signal of described the 16 logical AND gate circuit.
The application treats interlocking and protection with a certain discrimination, is specifically to say holding circuit and interlock circuit to separate, and holding circuit is divided into again protecting to start makes indicating circuit, protection pass action indicating circuit.
Interlocking is opened signal input and is opened command circuit, and interlocking closes signal input and closes command circuit.
Protect and open function: protect another road of opening signal to carry out and computing with the negate signal of hanging up the solution extension signal signal that namely the first set-reset flip-floop is exported; after computing, be input to the S end of the second set-reset flip-floop; the second set-reset flip-floop output signal is designated as G; when output signal G is high level, it is bright that action indicator is opened in protection.
Function is closed in protection: another road that signal is closed in protection with hang up separate hang signal namely the negate signal of the first set-reset flip-floop output signal carry out and computing; after computing, be input to the S end of the second set-reset flip-floop; the second set-reset flip-floop output signal is designated as H; when output signal H is high level, it is bright that action indicator is closed in protection.
Alternatively, described protection is started and is made indicating circuit and also comprise the 11 pulse generating circuit, described the 11 pulse generating circuit, and input end receives protection and opens actuating signal, and output terminal connects the second input end of described the 9th logical AND gate circuit;
Described protection is closed action indicating circuit and is also comprised twelve-pulse circuit for generating, described twelve-pulse circuit for generating, and input end receives protection and closes actuating signal, and output terminal connects the second input end of described the tenth logical AND gate circuit,
The 11 pulse generating circuit receives to be protected while opening signal, and take-off becomes high level from low level, and the duration was 2 seconds, and after 2 seconds, pulse becomes low level from high level.
When twelve-pulse circuit for generating receives protection pass signal, take-off becomes high level from low level, and the duration was 2 seconds, and after 2 seconds, pulse becomes low level from high level.
Alternatively, on the spot control knob with control on the spot pilot lamp and be connected, when pressing on the spot control knob, control on the spot pilot lamp bright.
Alternatively, also comprise the first logic inverter circuit,
For the output signal negate that described hang-up and solution are hung to circuit,
Described the first logic inverter circuit, input end receives to be hung up and separates the output signal of hanging circuit,
The first output of output terminal connects the first input end of the 4th logical AND gate circuit of opening command circuit;
The second output of output terminal connects the first input end of the 8th logical AND gate circuit that closes command circuit;
The 3rd output of output terminal connects the first input end that the 9th logical AND gate circuit of making indicating circuit is started in protection;
The 4th output of output terminal connects the first input end that the tenth logical AND gate circuit of action indicating circuit is closed in protection.
Alternatively, described confirmation signal is by confirming that circuit produces;
Described confirmation circuit at least comprises the first pulse generating circuit, the 4th logic sum gate circuit; The input end of described the first pulse generating circuit receives distant place confirmation signal, and output terminal connects the first input end of the 4th logic sum gate circuit, and the second input end of described the 4th logic sum gate circuit receives manual confirmation signal;
The output terminal of described the 4th logic sum gate circuit,
The first output connects the first input end that the 15 logical AND gate circuit of making indicating circuit is started in protection;
The second output connects the first input end that the 16 logical AND gate circuit of action indicating circuit is closed in protection;
The 3rd output connects the first input end of the 12 logical AND gate circuit of driving indicating circuit;
The 4th output connects the first input end of the 14 logical AND gate circuit that is closing indicating circuit.
During valve wide open, output valve standard-sized sheet signal, is designated as C.
The signal that distant place confirmation signal, manual confirmation button P7 send carries out logical OR computing, the signal after computing:
1, carry out and computing with signal G, the signal after computing is input to the R end of the second set-reset flip-floop,
That is to say, when in separating extension state, have and protect while opening signal, the S of the second set-reset flip-floop end is high level, and output terminal is high level, and signal G is high level, and protection is turned on light bright.
When having distant place confirmation signal or having manual confirmation signal; with signal G carry out with computing after for high level; now; the R end of the second set-reset flip-floop is high level; the output terminal upset of the second set-reset flip-floop becomes low level; signal G is low level; protection is turned on light and is gone out; because signal G becomes low level, with distant place confirmation signal or manual confirmation signal carry out with computing after, the signal after computing is low level; the R end of the second set-reset flip-floop becomes low level; the output terminal upset of the second set-reset flip-floop becomes high level, and signal G becomes high level, and protection is turned on light bright.
That is to say, when having distant place confirmation signal or having manual confirmation signal, protection is turned on light can be in blink states.
2, carry out and computing with signal H, the signal after computing is input to the R end of Three S's R trigger,
That is to say, when in separating extension state, have and protect while closing signal, the S of Three S's R trigger end is high level, and output terminal is high level, and signal H is high level, and protection is turned off the light bright.
When having distant place confirmation signal or having manual confirmation signal, and after signal G and computing, be high level, now, the R of Three S's R trigger end is high level, and the output terminal upset of Three S's R trigger becomes low level, and signal H is low level, and protection is turned off the light and is gone out.
When having distant place confirmation signal or having manual confirmation signal; with after signal H and computing, be high level; now; the R end of Three S's R trigger is high level; the output terminal upset of Three S's R trigger becomes low level; signal H is low level; protection is turned off the light and is gone out; because signal H becomes low level, with distant place confirmation signal or manual confirmation signal carry out with computing after, the signal after computing is low level; the R end of Three S's R trigger becomes low level; the output terminal upset of Three S's R trigger becomes high level, and signal H becomes high level, and protection is turned off the light bright.
That is to say, when having distant place confirmation signal or having manual confirmation signal, protection is closed lantern festival in blink states.
3, with signal E and computing, after computing, carry out exclusive disjunction with signal B, valve wide open signal.After computing, be input to the R end of the 4th set-reset flip-floop, the S end of the 4th set-reset flip-floop connects signal A,
The output signal of the 4th set-reset flip-floop:
1) signal and after signal D negate computing carries out and computing, and the signal after computing is transferred to opens pilot lamp;
2) with the time delay delay circuit of 30 seconds after, form signal E, signal E is transferred to out fault-signal pilot lamp.
That is to say, open fault indication signal and be designated as E, when opening order while enabling, A is high level, whether now checks fault, is mainly check valve wide open.
Because signal B is for closing command signal, when opening order while enabling, close order and close, signal B is low level,
If valve wide open button is pressed, valve wide open signal is that high level is also high level after exclusive disjunction, is transferred to the R end of the 4th set-reset flip-floop, and the output terminal upset of the 4th set-reset flip-floop becomes low level, and signal E is low level, opens malfunction indicator lamp and goes out.Because valve wide open, valve complete shut-down button signal D is low level, after negate computing with after the output end signal of the 4th set-reset flip-floop and computing, be also low level, opening pilot lamp and going out.
If valve does not have standard-sized sheet, valve wide open signal is low level.
Now, the level of the S of the 4th set-reset flip-floop end depends on confirmation signal, and confirmation signal comprises distant place confirmation signal and manual confirmation signal.When having confirmation signal, the S end of the 4th set-reset flip-floop is high level, the output terminal upset of the 4th set-reset flip-floop becomes low level, and signal E is low level, opens malfunction indicator lamp and goes out, after signal E is low level, after confirmation signal and computing, the S of the 4th set-reset flip-floop end is low level, and the output terminal upset of the 4th set-reset flip-floop becomes high level, now signal E is high level, opens malfunction indicator lamp bright;
When valve complete shut-down button is not when pressing, signal D is low level, is high level after negate, and is also high level after the high level of the output terminal of the 4th set-reset flip-floop and computing, is opening pilot lamp bright.
Visible, if valve does not have standard-sized sheet, after having confirmation signal, open malfunction indicator lamp in blink states.Opening pilot lamp in blink states.
During valve complete shut-down, valve complete shut-down signal D is high level, after negate computing with after the output end signal of the 4th set-reset flip-floop and computing, be also low level, opening pilot lamp and going out.
4, with signal F and computing, after computing, carry out exclusive disjunction with signal A, valve complete shut-down signal.After computing, be input to the R end of the 5th set-reset flip-floop, the S end of the 5th set-reset flip-floop connects signal B,
The output signal of the 5th set-reset flip-floop:
1) signal and after signal C negate computing carries out and computing, and the signal after computing is transferred to and closes pilot lamp;
2) after the time delay delay circuit of 30 seconds, form signal F, signal F is transferred to and closes fault-signal pilot lamp.
When closing order while enabling, B is high level, whether now checks fault, is mainly check valve complete shut-down.
Because signal B is for closing command signal, when pass order enables, signal B is high level, and A is low level.
If valve complete shut-down, valve complete shut-down signal is that high level is also high level after exclusive disjunction, is transferred to the R end of the 5th set-reset flip-floop, and the output terminal upset of the 5th set-reset flip-floop becomes low level, and signal F is low level, closes malfunction indicator lamp and goes out.Because valve complete shut-down, valve wide open button signal C is low level, after negate computing with after the output end signal of the 5th set-reset flip-floop and computing, be also low level, closing pilot lamp and going out.
If valve does not have complete shut-down, valve complete shut-down signal is low level, and now, the level of the R of the 5th set-reset flip-floop end depends on confirmation signal, and confirmation signal comprises distant place confirmation signal and manual confirmation signal.When having confirmation signal, the R end of the 5th set-reset flip-floop is high level, the output terminal upset of the 5th set-reset flip-floop becomes low level, and signal F is low level, closes malfunction indicator lamp and goes out, after signal F is low level, after confirmation signal and computing, the R of the 5th set-reset flip-floop end is low level, and the output terminal upset of the 5th set-reset flip-floop becomes high level, now signal F is high level, and pass malfunction indicator lamp is bright;
When valve wide open button is not when pressing, signal C is low level, is high level after negate, and is also high level after the high level of the output terminal of the 5th set-reset flip-floop and computing, is closing pilot lamp bright.
Visible, if valve does not have complete shut-down, after having confirmation signal, close malfunction indicator lamp in blink states, close pilot lamp in blink states.
Alternatively, the described indicating circuit of opening also comprises the 4th logic inverter circuit, for by the negate of valve complete shut-down signal;
Described the 4th logic inverter circuit, input end receives valve complete shut-down signal, and output terminal is connected with the second input end of described the 11 logical AND gate circuit;
The described indicating circuit that closing also comprises the 5th logic inverter circuit, for by the negate of valve wide open signal;
Described the 5th logic inverter circuit, input end receives valve wide open signal, and output terminal is connected with the second input end of described the 13 logical AND gate circuit.
Alternatively, also comprise that fault shows "Σ" logic circuit;
Described fault shows that "Σ" logic circuit at least comprises the 6th logic sum gate circuit, electric fault pilot lamp, opens malfunction indicator lamp, closes malfunction indicator lamp, input and output I/O faulty circuit, fault show and gather pilot lamp;
The output terminal of described the 6th logic sum gate circuit connects fault and gathers pilot lamp;
Described the first delay circuit of opening faulty circuit, the second output of output terminal connects opens malfunction indicator lamp, and the 3rd output of output terminal connects the second input end of described the 6th logic sum gate circuit;
The described malfunction indicator lamp of opening is connected with the second input end of described the 6th logic sum gate circuit;
The second delay circuit of described pass faulty circuit, the second output of output terminal connects described pass malfunction indicator lamp,
The 3rd output of output terminal connects the 3rd input end of described the 6th logic sum gate circuit;
Closing malfunction indicator lamp is connected with the 3rd input end of described the 6th logic sum gate circuit.
Described input and output I/O faulty circuit at least comprises input and output I/O malfunction indicator lamp, the 7th logic sum gate circuit;
The input and output I/O malfunction indicator lamp of described input and output I/O faulty circuit connects described the 6th logic sum gate circuit four-input terminal;
Described the 7th logic sum gate circuit, output terminal the first output connects described the 6th logic sum gate circuit four-input terminal, and output terminal the second output connects described input and output I/O malfunction indicator lamp.
Alternatively, described input and output I/O faulty circuit also comprises the 3rd delay circuit, the 17 logical AND gate circuit, the 18 logical AND gate circuit, the second logic inverter circuit, the 3rd logic inverter circuit, the first quality decision gate circuit, the second quality decision gate circuit;
Described the 7th logic sum gate circuit, first input end connects the output terminal of the 3rd delay circuit, and the second input end connects the output terminal of the 17 logical AND gate circuit, and the 3rd input end connects the output terminal of the 8th logic sum gate circuit;
The input end of described the 3rd delay circuit connects the output terminal of the 18 logical AND gate circuit;
Described the 18 logical AND gate circuit, first input end connects the output terminal of the second logic inverter circuit, and the second input end connects the output terminal of the 3rd logic inverter circuit;
The input end of described the second logic inverter circuit receives valve wide open signal;
The input end of described the 3rd logic inverter circuit receives valve complete shut-down signal;
Described the 17 logical AND gate circuit, first input end receives valve wide open signal, and the second input end receives valve complete shut-down signal;
Described the 8th logic sum gate circuit, first input end connects the output terminal of the first quality decision gate circuit, and the second input end connects the output terminal of the second quality decision gate circuit;
The input end of described the first quality decision gate circuit receives valve wide open signal;
The input end of described the second quality decision gate circuit receives valve complete shut-down signal.
Valve wide open signal and valve complete shut-down signal carry out with computing after signal;
Signal after signal after the negate of valve wide open signal and the negate of valve complete shut-down signal carries out and computing, and the signal of gained is through delay circuit time delay resulting signal after 30 seconds;
Signal and the valve complete shut-down signal signal through second quality decision gate circuit computing after of valve wide open signal after the first quality decision gate circuit computing carries out and computing gained signal;
Above three kinds of signals carry out exclusive disjunction, have obtained I/O fault-signal, I/O fault-signal pilot lamp indication for I/O fault-signal.
Quality decision gate circuit computing is that the measuring point of input is got to quality judgement, and quality bad time is exported high level.
Electric fault button signal is transferred to and electric fault pilot lamp.
Electric fault signal, open fault-signal E, close fault-signal F, I/O fault-signal carries out exclusive disjunction, after computing, output to fault and gather pilot lamp.
Certainly; the utility model also can have other various embodiments; in the situation that not deviating from the utility model spirit and essence thereof; those of ordinary skill in the art are when making various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection domain of claim of the present utility model.
Claims (10)
1. a single-row subsidiary engine Electrically operated gate logical circuit, is characterized in that, at least comprises out command circuit, closes command circuit, drives indicating circuit, closes indicating circuit, opens failure indicating circuit, closes failure indicating circuit;
Driving indicating circuit at least comprises:
Opening pilot lamp;
The 3rd logic sum gate circuit, first input end connects the output terminal of described pass command circuit, and the 3rd input end receives valve wide open signal;
The 4th set-reset flip-floop, R end connects the output terminal of described the 3rd logic sum gate circuit, opens the output terminal of command circuit described in S end connects, and opens the input end of failure indicating circuit described in output terminal I connects;
The 12 logical AND gate circuit, opens the output terminal of failure indicating circuit described in the second input end connects, first input end confirmation of receipt signal, and output terminal connects the second input end of described the 3rd logic sum gate circuit;
The 11 logical AND gate circuit, first input end is connected with the output terminal I of described the 4th set-reset flip-floop, and the second input end receives the negate signal of valve complete shut-down signal, described in output terminal connects, is opening pilot lamp;
Closing indicating circuit at least comprises:
Closing pilot lamp;
The 5th logic sum gate circuit, opens the output terminal of command circuit described in first input end connects, the 3rd input end receives valve complete shut-down signal;
The 5th set-reset flip-floop, R end connects the output terminal of described the 3rd logic sum gate circuit, opens the output terminal of command circuit described in S end connects, and opens the input end of failure indicating circuit described in output terminal I connects;
The 14 logical AND gate circuit, opens the output terminal of failure indicating circuit, first input end confirmation of receipt signal described in the second input end connects; Output terminal connects the second input end of described the 5th logic sum gate circuit;
The 13 logical AND gate circuit, first input end is connected with the output terminal I of described the 5th set-reset flip-floop, and the second input end receives the negate signal of valve wide open signal, described in output terminal connects, is closing pilot lamp.
2. circuit as claimed in claim 1, it is characterized in that, also comprise hang-up and solution extension circuit, described hang-up and solution extension circuit are used for generating hang-up or solution extension signal, and hang-up and solution extension circuit output end are at least to described command circuit, pass command circuit conveying hang-up or the solution extension signal opened;
Described hang-up is hung circuit with solution and is at least comprised the first set-reset flip-floop, hangs up pilot lamp;
Described the first set-reset flip-floop, the first output of output terminal I is used for to opening command circuit, pass command circuit output hang-up and solution extension signal, and pilot lamp is hung up in the second output connection of output terminal I;
R termination is received to separate and is hung signal, and S termination is received pending signal;
Described hang-up is hung circuit with solution and is also comprised the 9th logic sum gate circuit, the tenth logic sum gate circuit, the 7th pulse generating circuit, the 8th pulse generating circuit;
Described the 9th logic sum gate circuit, first input end connects the output terminal of described the 7th pulse generating circuit, and the second input end receives manual pending signal, and output terminal connects the S end of described the first set-reset flip-floop;
The input end of described the 7th pulse generating circuit receives the pending signal that external circuit sends;
Described the tenth logic sum gate circuit, first input end connects the output terminal of described the 8th pulse generating circuit, and the second input end receives to separate hangs signal, and output terminal connects the R end of described the first set-reset flip-floop;
The input end of described the 8th pulse generating circuit receives the solution extension signal that external circuit sends.
3. circuit as claimed in claim 1, it is characterized in that, described in open command circuit and at least comprise the first logic sum gate circuit, the first logical AND gate circuit, the second logical AND gate circuit, the 3rd logical AND gate circuit, the 4th logical AND gate circuit, open permission pilot lamp;
The first logical AND gate circuit, first input end receives single operation and opens request signal, and the second input end receives opens permission signal, and allows pilot lamp to be connected with opening, and output terminal connects the first input end of the first logic sum gate circuit;
The second logical AND gate circuit, first input end reception sequence is opened signal, the second input end receives and opens permission signal, and output terminal connects the second input end of the first logic sum gate circuit;
The 3rd logical AND gate circuit, first input end receives interlocking and opens signal, and the second input end receives and opens permission signal, and output terminal connects the 3rd input end of the first logic sum gate circuit;
The four-input terminal of described the first logic sum gate circuit receives protection and opens signal;
The 4th logical AND gate circuit, first input end connects the output terminal of the first logic sum gate circuit, and the second input end receive to be hung up and is separated the negate signal of hanging signal, and what output terminal connected outside delay circuit opens order end;
Described pass command circuit at least comprises the 5th logical AND gate circuit, the 6th logical AND gate circuit, the 7th logical AND gate circuit, the 8th logical AND gate circuit, the second logic sum gate circuit, closes permission pilot lamp;
The 5th logical AND gate circuit, request signal is closed in first input end reception single operation, and the second input end receives to close and allows signal, and allows pilot lamp to be connected with pass, and output terminal connects the first input end of the second logic sum gate circuit;
The 6th logical AND gate circuit, first input end receives sequence and closes signal, and the second input end receives to close and allows signal, and output terminal connects the second input end of the second logic sum gate circuit;
The 7th logical AND gate circuit, first input end receives interlocking and closes signal, and the second input end receives to close and allows signal, and output terminal connects the 3rd input end of the second logic sum gate circuit;
The four-input terminal of described the second logic sum gate circuit receives protection and closes signal;
The 8th logical AND gate circuit, first input end connects the output terminal of the second logic sum gate circuit, and the second input end receives to be hung up and separates the negate signal of hanging signal, and output terminal connects the pass order end of outside delay circuit.
4. circuit as claimed in claim 3, is characterized in that, described in open command circuit and also comprise:
The first pulse generating circuit, opens request signal for receiving single operation, produces trigger pulse, and output terminal connects the first input end of the first logical AND gate circuit;
The second pulse generating circuit, for receiving sequence, open request signal, produce trigger pulse, output terminal connects the first input end of the second logical AND gate circuit;
The 3rd pulse generating circuit, for receiving interlocking, open request signal, produce trigger pulse, output terminal connects the first input end of the 3rd logical AND gate circuit;
Described pass command circuit also comprises:
The 4th pulse generating circuit, for receiving single operation, close request signal, produce trigger pulse,
Output terminal connects the first input end of the 5th logical AND gate circuit;
The 5th pulse generating circuit, for receiving sequence, close request signal, produce trigger pulse, output terminal connects the first input end of the 6th logical AND gate circuit;
The 6th pulse generating circuit, for receiving interlocking, close request signal, produce trigger pulse, output terminal connects the first input end of the 7th logical AND gate circuit;
Open command circuit and also comprise the 9th pulse generating circuit, the 11 logic sum gate circuit;
Described the 9th pulse generating circuit, input end receives the single operation of external circuit input and opens request signal, and output terminal connects the second input end of described the 11 logic sum gate circuit; Described the 11 logic sum gate circuit, first input end receives manual single operation and opens request signal, and output terminal connects the input end of described the first pulse generating circuit;
Close command circuit and also comprise the tenth pulse generating circuit, the 12 logic sum gate circuit;
Described the tenth pulse generating circuit, input end receives the single operation pass request signal that external circuit sends, output terminal connects the second input end of described the 12 logic sum gate circuit, described the 12 logic sum gate circuit, first input end receives single operation and closes request signal, and output terminal connects the input end of described the 4th pulse generating circuit.
5. circuit as claimed in claim 1, it is characterized in that, the described indicating circuit of opening also comprises the 4th logic inverter circuit, for by described valve complete shut-down signal negate computing, input end receives valve complete shut-down signal, and output terminal connects described the 11 logical AND gate circuit the second input end;
The described indicating circuit that closing also comprises the 5th logic inverter circuit, and for by described valve wide open signal negate computing, input end receives valve wide open signal, and output terminal connects described the 13 logical AND gate circuit the second input end.
6. circuit as claimed in claim 1, is characterized in that, also comprises protecting to start making indicating circuit, protection pass action indicating circuit;
Described protection is started and is made indicating circuit and at least comprise that protection opens action indicator, the second set-reset flip-floop, the 9th logical AND gate circuit, the 15 logical AND gate circuit;
Described the 9th logical AND gate circuit, first input end receives to be hung up and separates the negate signal of hanging signal; The second input end receives protection and opens actuating signal, and output terminal connects the S end of described the second set-reset flip-floop;
Described the second set-reset flip-floop, output terminal I output protection is opened actuating signal, the first output connects protection and opens action indicator, the second output connects the second input end of described the 15 logical AND gate circuit, R end connects the output terminal of the 15 logical AND gate circuit, the first input end confirmation of receipt signal of described the 15 logical AND gate circuit;
Described protection is closed action indicating circuit and is at least comprised protection pass action indicator, Three S's R trigger, the tenth logical AND gate circuit, the 16 logical AND gate circuit;
Described the tenth logical AND gate circuit, first input end receives to be hung up and separates the negate signal of hanging signal; The second input end receives protection and closes actuating signal, and output terminal connects the S end of described Three S's R trigger;
Described Three S's R trigger, output terminal I output protection closes actuating signal, the first output connects protection and closes action indicator, the second output connects the second input end of described the 16 logical AND gate circuit, R end connects the output terminal of described the 16 logical AND gate circuit, the first input end confirmation of receipt signal of described the 16 logical AND gate circuit;
Described protection is started and is made indicating circuit and also comprise the 11 pulse generating circuit, described the 11 pulse generating circuit, and input end receives protection and opens actuating signal, and output terminal connects the second input end of described the 9th logical AND gate circuit;
Described protection is closed action indicating circuit and is also comprised twelve-pulse circuit for generating, described twelve-pulse circuit for generating, and input end receives protection and closes actuating signal, and output terminal connects the second input end of described the tenth logical AND gate circuit.
7. the circuit as described in claim 2 or 3 or 6, is characterized in that, also comprises the first logic inverter circuit,
For the output signal negate that described hang-up and solution are hung to circuit,
Described the first logic inverter circuit, input end receives to be hung up and separates the output signal of hanging circuit,
The first output of output terminal connects the first input end of the 4th logical AND gate circuit of opening command circuit;
The second output of output terminal connects the first input end of the 8th logical AND gate circuit that closes command circuit;
The 3rd output of output terminal connects the first input end that the 9th logical AND gate circuit of making indicating circuit is started in protection;
The 4th output of output terminal connects the first input end that the tenth logical AND gate circuit of action indicating circuit is closed in protection.
8. the circuit as described in claim 1 or 6, is characterized in that, described confirmation signal is by confirming that circuit produces;
Described confirmation circuit at least comprises the first pulse generating circuit, the 4th logic sum gate circuit; The input end of described the first pulse generating circuit receives distant place confirmation signal, and output terminal connects the first input end of the 4th logic sum gate circuit, and the second input end of described the 4th logic sum gate circuit receives manual confirmation signal;
The output terminal of described the 4th logic sum gate circuit,
The first output connects the first input end that the 15 logical AND gate circuit of making indicating circuit is started in protection;
The second output connects the first input end that the 16 logical AND gate circuit of action indicating circuit is closed in protection;
The 3rd output connects the first input end of the 12 logical AND gate circuit of driving indicating circuit;
The 4th output connects the first input end of the 14 logical AND gate circuit that is closing indicating circuit.
9. circuit as claimed in claim 1, is characterized in that, the described indicating circuit of opening also comprises the 4th logic inverter circuit, for by the negate of valve complete shut-down signal;
Described the 4th logic inverter circuit, input end receives valve complete shut-down signal, and output terminal is connected with the second input end of described the 11 logical AND gate circuit;
The described indicating circuit that closing also comprises the 5th logic inverter circuit, for by the negate of valve wide open signal;
Described the 5th logic inverter circuit, input end receives valve wide open signal, and output terminal is connected with the second input end of described the 13 logical AND gate circuit.
10. circuit as claimed in claim 1, is characterized in that, also comprises that fault shows "Σ" logic circuit;
Described fault shows that "Σ" logic circuit at least comprises the 6th logic sum gate circuit, electric fault pilot lamp, opens malfunction indicator lamp, closes malfunction indicator lamp, input and output I/O faulty circuit, fault show and gather pilot lamp, the first delay circuit, the second delay circuit;
The output terminal of described the 6th logic sum gate circuit connects fault and gathers pilot lamp;
Described the first delay circuit of opening faulty circuit, the second output of output terminal connects opens malfunction indicator lamp, and the 3rd output of output terminal connects the second input end of described the 6th logic sum gate circuit;
The described malfunction indicator lamp of opening is connected with the second input end of described the 6th logic sum gate circuit;
The second delay circuit of described pass faulty circuit, the second output of output terminal connects described pass malfunction indicator lamp,
The 3rd output of output terminal connects the 3rd input end of described the 6th logic sum gate circuit;
Closing malfunction indicator lamp is connected with the 3rd input end of described the 6th logic sum gate circuit;
Described input and output I/O faulty circuit at least comprises input and output I/O malfunction indicator lamp, the 7th logic sum gate circuit;
The input and output I/O malfunction indicator lamp of described input and output I/O faulty circuit connects described the 6th logic sum gate circuit four-input terminal;
Described the 7th logic sum gate circuit, output terminal the first output connects described the 6th logic sum gate circuit four-input terminal, and output terminal the second output connects described input and output I/O malfunction indicator lamp;
Described input and output I/O faulty circuit also comprise the 3rd delay circuit, the 17 logical AND gate circuit,
The 18 logical AND gate circuit, the second logic inverter circuit, the 3rd logic inverter circuit, the first product
Matter decision gate circuit, the second quality decision gate circuit;
Described the 7th logic sum gate circuit, first input end connects the output terminal of the 3rd delay circuit, and the second input end connects the output terminal of the 17 logical AND gate circuit, and the 3rd input end connects the output terminal of the 8th logic sum gate circuit;
The input end of described the 3rd delay circuit connects the output terminal of the 18 logical AND gate circuit;
Described the 18 logical AND gate circuit, first input end connects the output terminal of the second logic inverter circuit, and the second input end connects the output terminal of the 3rd logic inverter circuit;
The input end of described the second logic inverter circuit receives valve wide open signal;
The input end of described the 3rd logic inverter circuit receives valve complete shut-down signal;
Described the 17 logical AND gate circuit, first input end receives valve wide open signal, and the second input end receives valve complete shut-down signal;
Described the 8th logic sum gate circuit, first input end connects the output terminal of the first quality decision gate circuit, and the second input end connects the output terminal of the second quality decision gate circuit;
The input end of described the first quality decision gate circuit receives valve wide open signal;
The input end of described the second quality decision gate circuit receives valve complete shut-down signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420189204.XU CN203825415U (en) | 2014-04-17 | 2014-04-17 | Single-row auxiliary engine electrically operated gate logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420189204.XU CN203825415U (en) | 2014-04-17 | 2014-04-17 | Single-row auxiliary engine electrically operated gate logic circuit |
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| Publication Number | Publication Date |
|---|---|
| CN203825415U true CN203825415U (en) | 2014-09-10 |
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|---|---|---|---|
| CN201420189204.XU Expired - Lifetime CN203825415U (en) | 2014-04-17 | 2014-04-17 | Single-row auxiliary engine electrically operated gate logic circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104777805A (en) * | 2015-02-11 | 2015-07-15 | 北京配天技术有限公司 | Industrial robot safety control system as well as backup safety circuit and safety module |
| CN107575370A (en) * | 2017-10-13 | 2018-01-12 | 中石化宁波工程有限公司 | The more stand-by pump self-starting logic control circuits based on sequential control |
| CN113608458A (en) * | 2021-06-29 | 2021-11-05 | 中国大唐集团科学技术研究院有限公司火力发电技术研究院 | Switch type equipment interlocking start-stop method in thermal power generation thermal control interlocking system |
-
2014
- 2014-04-17 CN CN201420189204.XU patent/CN203825415U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104777805A (en) * | 2015-02-11 | 2015-07-15 | 北京配天技术有限公司 | Industrial robot safety control system as well as backup safety circuit and safety module |
| CN104777805B (en) * | 2015-02-11 | 2017-12-15 | 北京配天技术有限公司 | A kind of industrial robot safety control system and backup safety circuit, security module |
| CN107575370A (en) * | 2017-10-13 | 2018-01-12 | 中石化宁波工程有限公司 | The more stand-by pump self-starting logic control circuits based on sequential control |
| CN113608458A (en) * | 2021-06-29 | 2021-11-05 | 中国大唐集团科学技术研究院有限公司火力发电技术研究院 | Switch type equipment interlocking start-stop method in thermal power generation thermal control interlocking system |
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Granted publication date: 20140910 |