CN203811952U - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN203811952U CN203811952U CN201420234346.3U CN201420234346U CN203811952U CN 203811952 U CN203811952 U CN 203811952U CN 201420234346 U CN201420234346 U CN 201420234346U CN 203811952 U CN203811952 U CN 203811952U
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- 239000000758 substrate Substances 0.000 title abstract description 6
- 239000010409 thin film Substances 0.000 claims description 95
- 238000012360 testing method Methods 0.000 claims description 36
- 230000003068 static effect Effects 0.000 claims description 35
- 239000010408 film Substances 0.000 claims description 26
- 230000001681 protective effect Effects 0.000 claims description 21
- 238000007599 discharging Methods 0.000 abstract description 9
- 239000003990 capacitor Substances 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 206010047571 Visual impairment Diseases 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 235000008429 bread Nutrition 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
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Abstract
The utility model provides an array substrate which comprises multiple data lines, multiple common electrode lines and discharging units. The discharging units are arranged between at least one data line and at least one common electrode line and can selectively connect the data lines connected with the discharging units with the common electrode lines connected with the discharging units. The utility model further provides a display panel comprising the array substrate. The discharging units can selectively connect the data lines connected with the discharging units with the common electrode lines connected with the discharging units, so that quick discharging of a storage capacitor is realized, and residual image phenomena are reduced.
Description
Technical field
The utility model relates to technical field of liquid crystal display, relates in particular to a kind of array base palte and display panel.
Background technology
TFT thin film transistor monitor (TFT-LCD) is through the development of nearest decades, and due to its high-quality image quality, the advantages such as low-power and low cost, are widely applied.
In the course of work of liquid crystal display, when liquid crystal display is carried out image demonstration, the thin film transistor (TFT) corresponding with pixel electrode opened, signal can be delivered on pixel electrode by data line, be the memory capacitance charging that pixel electrode and public electrode form, when liquid crystal display does not show image (, while showing between two frame pictures), the memory capacitance that pixel electrode and public electrode form is discharged.But along with the raising of monitor resolution, because the memory capacitance velocity of discharge that pixel electrode is corresponding is limited, thereby cause occurring image retention problem in the process of two frame picture saltus steps, reduced product quality.
Therefore the speed that, how to improve the electric discharge of the corresponding memory capacitance of pixel electrode becomes this area technical matters urgently to be resolved hurrily.
Utility model content
In order to address the above problem, the display panel that the purpose of this utility model is to provide a kind of array base palte and comprises this array base palte, described array base palte can improve the velocity of discharge of the memory capacitance that data line is corresponding.
To achieve these goals, the utility model provides a kind of array base palte, comprise many data lines and many public electrode wires, described array base palte also comprises discharge cell, described at least one, described in data line and at least one, between public electrode wire, be provided with described discharge cell, described discharge cell can be by the data line being connected with this discharge cell and optionally conducting of the described public electrode wire being connected with described discharge cell.
Preferably, described array base palte also comprises driving circuit, described discharge cell comprises the first film transistor, the transistorized grid of described the first film is connected with the output terminal of described driving circuit, the transistorized source electrode of described the first film is connected with described data line with the one in drain electrode, another one is connected with described public electrode wire, and described driving circuit can be exported the control signal that described the first film transistor is optionally opened.
Preferably, described array base palte also comprises the switch signal line of the output terminal that is connected to described driving circuit, and the transistorized grid of described the first film is connected with described switch signal line, to be connected with the output terminal of described driving circuit by described switch signal line.
Preferably, described array base palte comprises a plurality of described discharge cells, between in many described public electrode wires one and every data line, is provided with a described discharge cell.
Preferably, the public electrode wire being connected with described discharge cell is many first row public electrode wires in described public electrode wire.
Preferably, be provided with static protective unit described in described switch signal line and at least one between data line, the static on described data line can be released into described switch signal line by described static protective unit.
Preferably, described static protective unit comprises the second thin film transistor (TFT) and the 3rd thin film transistor (TFT), and described the second thin film transistor (TFT) is N-type thin film transistor (TFT), and described the 3rd thin film transistor (TFT) is P type thin film transistor (TFT); Or,
Described the second thin film transistor (TFT) is P type thin film transistor (TFT), and described the 3rd thin film transistor (TFT) is N-type thin film transistor (TFT);
The source electrode of described the second thin film transistor (TFT) is connected with described switch signal line with the one in drain electrode, another one is connected with described data line, the grid of described the second thin film transistor (TFT) is connected with described switch signal line, the source electrode of described the 3rd thin film transistor (TFT) is connected with described data line with the one in drain electrode, another one is connected with described switch signal line, and the grid of described the 3rd thin film transistor (TFT) is connected with described data line.
Preferably, between every described data line and described switch signal line, be provided with described static protective unit.
Preferably, described array base palte also comprises the test cell being connected with described data line, and this test cell is for providing test signal to described data line.
Preferably, described test cell comprises p-wire and at least one the 4th thin film transistor (TFT), the corresponding data line of each the 4th thin film transistor (TFT), each the 4th thin film transistor (TFT) is all connected between corresponding described data line and described p-wire, the grid of described the 4th thin film transistor (TFT) is connected with described switch signal line, the source electrode of described the 4th thin film transistor (TFT) is connected with corresponding described data line with the one in drain electrode, and another one is connected with described p-wire.
Preferably, in the pixel region of described array base palte, be provided with red pixel electrode, green pixel electrode and blue pixel electrode, described red pixel electrode, described green pixel electrode and described blue pixel electrode are connected with corresponding data line respectively, and described p-wire is included as described red pixel electrode and provides the first p-wire of test signal, the second p-wire of test signal is provided and provides the 3rd p-wire of test signal for described blue pixel electrode for described green pixel electrode.
Preferably, between every data line and described p-wire, be provided with described the 4th thin film transistor (TFT).
Preferably, described test cell comprises a plurality of the 4th thin film transistor (TFT)s, be positioned at the described red pixel electrode of identical described pixel region, described green pixel electrode and described blue pixel electrode respectively the grid of corresponding described the 4th thin film transistor (TFT) interconnect.
Correspondingly, the utility model also provides a kind of display panel, comprises array base palte, wherein, and described array base palte array base palte provided by the utility model.
In the utility model, described array base palte comprises discharge cell, described discharge cell can be by the data line being connected with this discharge cell and optionally conducting of the described public electrode wire being connected with described discharge cell, thereby realize the memory capacitance rapid discharge corresponding to described data line, reduce the generation of afterimage phenomena; On the other hand, described array base palte also comprises static protective unit and detecting unit, described discharge cell, described static protective unit and described detecting unit are all connected with described switch signal line, thereby in the static on realizing minimizing data line and liquid crystal display detection, have simplified the structure of described array base palte.
Accompanying drawing explanation
Accompanying drawing is to be used to provide further understanding of the present utility model, and forms a part for instructions, is used from explanation the utility model, but does not form restriction of the present utility model with embodiment one below.In the accompanying drawings:
Shown in Fig. 1 is the structural representation of discharge cell in embodiment provided by the utility model;
Shown in Fig. 2 is that the structural representation of discharge cell and static protective unit is set in embodiment simultaneously;
Shown in Fig. 3 is the structural representation of static protective unit in embodiment;
Shown in Fig. 4 is the structural representation of test cell and static protective unit in embodiment;
Shown in Fig. 5 is another structural representation of test cell and static protective unit in embodiment.
Description of reference numerals
1: data line; 2, public electrode wire; 3: switch signal line; 4: the first p-wires; 5: the second p-wires; 6: the three p-wires; 7: red pixel electrode; 8: green pixel electrode; 9: blue pixel electrode; 10: test cell; M
1: the first film transistor; M
2: the second thin film transistor (TFT); M
3: the 3rd thin film transistor (TFT); M
4: the 4th thin film transistor (TFT).
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is elaborated.Should be understood that, embodiment described herein only, for description and interpretation the utility model, is not limited to the utility model.
The utility model provides a kind of array base palte, comprise many data lines 1 and many public electrode wires, described array base palte also comprises discharge cell, between at least one data line 1 and at least one public electrode wire 2, be provided with described discharge cell, described discharge cell can be by the data line 1 being connected with this discharge cell and optionally conducting of the public electrode wire 2 being connected with described discharge cell.
Well-known, arraying bread board comprises the pixel electrode connected with data line 1 and the public electrode corresponding with this pixel electrode, between described pixel electrode and described public electrode, forms memory capacitance.When comprising that the display panel of described array base palte shows image, the memory capacitance that pixel electrode and public electrode form is full of electric charge, to form electric field between pixel electrode and public electrode, controls the deflection angle of liquid crystal molecule; Between two two field pictures that show at display panel, display panel does not show image, the electric charge being filled on pixel electrode and public electrode need to be discharged.
Above described " optionally conducting " refers to, when described display panel does not show image (, show between two frame pictures), described discharge cell by the data line 1 being connected with this discharge cell and public electrode wire 2 conductings that are connected with described discharge cell (for example, can be produced and the control signal that does not show that image is corresponding by controller, make discharge cell by data line 1 and public electrode wire 2 conductings), discharging with the corresponding memory capacitance of data line; When described display panel shows image, described discharge cell (for example disconnects the data line 1 being connected with described discharge cell and the electrical connection between the public electrode wire 2 being connected with described discharge cell, can be produced and the control signal that shows that image is corresponding by controller, discharge cell is disconnected data line 1 and public electrode wire 2), can be to described memory capacitance charging, and keep the quantity of electric charge of described memory capacitance, utilize described memory capacitance to produce the electric field of controlling liquid crystal deflecting element.
In the utility model, when discharge cell by the data line 1 being connected with this discharge cell be connected with described discharge cell public electrode wire 2 conducting time, the electric charge of the corresponding memory capacitance of described data line can be released into public electrode wire 2 fast through described discharge cell, thereby realize described memory capacitance rapid discharge, and then can reduce the generation of afterimage phenomena.
The utility model is not done concrete restriction to the number of described discharge cell and structure, as long as can be by the data line 1 being connected with this discharge cell and optionally conducting of the public electrode wire 2 being connected with described discharge cell.
The utility model is not done concrete restriction to the mode of above-mentioned optionally conducting, and for example, described discharge cell can comprise controller and the switch of being controlled by this controller, and while showing image, described controller gauge tap disconnects; While not showing image, the conducting of described controller gauge tap.
As a kind of embodiment of the present utility model, described array base palte can also comprise driving circuit, and as depicted in figs. 1 and 2, described discharge cell comprises the first film transistor M
1, the first film transistor M
1grid be connected with the output terminal of described driving circuit, the first film transistor M
1source electrode with drain electrode in one be connected with data line 1, another one is connected with public electrode wire 2.Described driving circuit can be exported control signal between demonstration two two field pictures, and the first film transistor M1 is opened, thereby by the data line and the public electrode wire conducting that are connected with the first film transistor M1.
In the utility model, the first film transistor M
1grid can directly be connected with described driving circuit, also can indirectly be connected with described driving circuit.As a kind of preferred implementation of the present utility model, described array base palte also comprises the switch signal line 3 of the output terminal that is connected to described driving circuit, the first film transistor M
1grid be connected with switch signal line 3, to be indirectly connected with the output terminal of described driving circuit by switch signal line 3.The first film transistor M
1can be N-type thin film transistor (TFT), can be also P type thin film transistor (TFT).
At the first film transistor M
1in situation for N-type thin film transistor (TFT), when comprising that the display panel of described array base palte does not show image, described driving circuit is exported corresponding high level signal, the first film transistor M
1open, the data line 1 being connected with described discharge cell and public electrode wire 2 conductings that are connected with described discharge cell, so that memory capacitance electric discharge corresponding to the data line 1 connected with described discharge cell; When comprising that the display panel of described array base palte shows image, described driving circuit is exported corresponding low level signal, the first film transistor M
1close, the data line 1 being connected with described discharge cell disconnects with the public electrode wire 2 being connected with described discharge cell, can charge to described memory capacitance, and keep the voltage at described memory capacitance two ends.
Correspondingly, at the first film transistor M
1in situation for P type thin film transistor (TFT), when comprising that the display panel of described array base palte does not show image, described driving circuit is exported corresponding low level signal, the first film transistor M
1open, the data line 1 being connected with described discharge cell and public electrode wire 2 conductings that are connected with described discharge cell, so that memory capacitance electric discharge corresponding to the data line 1 connected with described discharge cell; When described display panel shows image, described driving circuit is exported corresponding high level signal, the first film transistor M
1close, the public electrode wire 2 that the data line 1 being connected with described discharge cell is connected with described discharge cell disconnects, and can charge to described memory capacitance, and keep the voltage at described memory capacitance two ends.
In order to make many corresponding memory capacitance of data line all can rapid discharge, preferably, as shown in Figure 1, described array base palte can comprise a plurality of described discharge cells, between one in every data line 1 and many public electrode wires 2, be provided with a described discharge cell (, the quantity of described discharge cell equates with the number of data line in described array base palte), so that the electric charge of memory capacitance corresponding to every row pixel electrode all can be released into public electrode wire 2 by described discharge cell, thereby can reduce equably the afterimage between two frame pictures.
Further, in order to make full use of the space of described array base palte, the public electrode wire 2 being connected with described discharge cell can be the first row public electrode wire 2 in many public electrode wires 2, to reduce the shared space of described discharge cell, thereby is conducive to the making of narrow edge frame product.Conventionally, the area of array base palte is greater than the area to box substrate,, the first pleurapophysis of array base palte is for to box substrate, second side relative with described the first side side with box substrate is alignd, described " the first row " public electrode wire refers to from described the second side and starts article one public electrode wire of arranging.
Array base palte manufacture craft (as, friction, high pressure dust etc.) or use procedure in, on data line 1, easily produce static.In order to reduce or to remove the static on data line 1, between switch signal line 3 and at least one data line 1, can also be provided with static protective unit, the static on data line 1 can be released on the data line being connected with switch signal line 3 by described static protective unit.For example, when static on a certain data line 1 is larger, the static on this data line 1 can be released into switch signal line 3, thereby is released on other data lines 1 by switch signal line 3.In the utility model, described static protective unit is connected with same switch signal line 3 with described discharge cell, thereby has simplified the structure of circuit.
Further, as shown in Figures 2 and 3, described static protective unit can comprise the second thin film transistor (TFT) M
2with the 3rd thin film transistor (TFT) M
3, the second thin film transistor (TFT) M
2for N-type thin film transistor (TFT), and the 3rd thin film transistor (TFT) M
3for P type thin film transistor (TFT); Or, the second thin film transistor (TFT) M
2for P type thin film transistor (TFT), the 3rd thin film transistor (TFT) M
3for N-type thin film transistor (TFT).The second thin film transistor (TFT) M
2source electrode with drain electrode in one be connected with switch signal line 3, another one is connected with data line 1, the second thin film transistor (TFT) M
2grid be connected with switch signal line 3, the 3rd thin film transistor (TFT) M
3source electrode with drain electrode in one be connected with data line 1, another one is connected with switch signal line 3, the 3rd thin film transistor (TFT) M
3grid be connected with data line 1.
For example, as shown in Figure 3, the second thin film transistor (TFT) M
2for P type thin film transistor (TFT), the second thin film transistor (TFT) M
2source electrode be all connected with switch signal line 3 with grid, drain electrode be connected with data line 1; The 3rd thin film transistor (TFT) M
3for N-type thin film transistor (TFT), the 3rd thin film transistor (TFT) M
3source electrode be connected with switch signal line 3, drain and gate is all connected with data line 1.Static on data line 1 higher and be on the occasion of time, voltage on data line 1 is compared with the voltage in switch signal line 3, and the voltage on data line 1 is equivalent to high level, and the voltage in switch signal line is equivalent to low level, now, data line 1 is controlled the 3rd thin film transistor (TFT) M
3open, the static on data line 1 is by the 3rd thin film transistor (TFT) M
3be released into switch signal line 3; Static on data line 1 is higher and while being negative value, similarly, the voltage on data line 1 is equivalent to high level, and the voltage in switch signal line 3 is equivalent to low level, and now, switch signal line 3 is controlled the second thin film transistor (TFT) M
2open, the static on data line 1 is by the second thin film transistor (TFT) M
2be released into switch signal line 3.
Further, for to being convenient to reduce the static on every data line 1, as shown in Figure 3, between every data line 1 and switch signal line 3, all can be provided with described static protective unit.
For detect that liquid crystal display occurs in manufacture craft process various bad (as, moire, bright line etc.), as shown in Figure 4 and Figure 5, described array base palte can also comprise the test cell 10 being connected with described data line, this test cell 10 is for providing test signal to described data line, thereby pixel region corresponding with described data line in display panel is detected.
Further, for the ease of test cell 10, for described data line optionally provides signal, that is, in lcd panel test process, to described data line, provide test signal; After test finishes, no longer to described data line, provide test signal, as shown in Figure 4 and Figure 5, test cell 10 can comprise p-wire and at least one the 4th thin film transistor (TFT) M
4, each the 4th thin film transistor (TFT) M
4a corresponding data line, each the 4th thin film transistor (TFT) is all connected between corresponding data line and described p-wire, the 4th thin film transistor (TFT) M
4grid be connected with switch signal line 3, the 4th thin film transistor (TFT) M
4source electrode with drain electrode in one be connected with corresponding data line 1, another one is connected with p-wire.
Be understandable that, described p-wire is connected with testing power supply conventionally, with by described pixel region and optionally conducting of testing power supply.For example, the 4th thin film transistor (TFT) M
4grid be connected with switch signal line 3, the source electrode utmost point is connected with corresponding data line 1, drain electrode be connected with described p-wire.With the 4th thin film transistor (TFT) M
4for N-type thin film transistor (TFT) is example, when needs are tested liquid crystal display, described driving circuit output high level, inputs to the 4th thin film transistor (TFT) M by switch signal line 3 by high level
4grid, to open the 4th thin film transistor (TFT) M
4thereby, by described pixel electrode and described signal wire conducting; After test finishes, described driving circuit output low level, inputs to the 4th thin film transistor (TFT) M by switch signal line 3 by high level
4grid, to close the 4th thin film transistor (TFT) M
4thereby, described pixel electrode and described p-wire are disconnected.Meanwhile, described detecting unit is connected with switch signal line 3, has avoided for described detecting unit, switch signal line being set separately, thereby when detecting, has optimized the structure of array base palte.
Further, in the pixel region of described array base palte, be provided with red pixel electrode 7, green pixel electrode 8 and blue pixel electrode 9, red pixel electrode 7, green pixel electrode 8 and blue pixel electrode 9 are connected respectively at corresponding data line, for the reason of various bad generations in judgement test exactly, described p-wire can be included as red pixel electrode 7 and provides the first p-wire 4 of test signal, the second p-wire 5 of test signal is provided and provides the 3rd p-wire 6 of test signal for blue pixel electrode 9 for green pixel electrode 8.
It should be noted that, described red pixel electrode, green pixel electrode and blue pixel electrode do not refer to that the color of pixel electrode itself is for red, green and blue, and refer to the color of corresponding sub-pixel, that is, the color of the color film of sub-pixel correspondence position is red, green and blue.
Further, as shown in Figure 4 and Figure 5, between every data line and described p-wire, all can be provided with a 4th thin film transistor (TFT) M
4, to provide test signal to every data line.
The utility model is to a plurality of the 4th thin film transistor (TFT) M
4grid and the connected mode of switch signal line 3 do not do concrete restriction.
As a kind of embodiment of the present utility model, as shown in Figure 4, can be by a plurality of the 4th thin film transistor (TFT) M
4grid be connected with switch signal line 3 again after connecting in pairs, that is, the red pixel electrode of first pixel cell and green pixel electrode be two the 4th thin film transistor (TFT) M of correspondence respectively
4grid be connected, then be connected with switch signal line 3.
As another kind of embodiment of the present utility model, as shown in Figure 5, be positioned at red pixel electrode, green pixel electrode and the 4th thin film transistor (TFT) M corresponding to blue pixel electrode difference in same pixel region
4grid interconnect, i.e. the red pixel electrode of first pixel region, green pixel electrode and blue pixel electrode corresponding the 4th thin film transistor (TFT) M respectively
4grid be connected with switch signal line 3 again after interconnecting.
As on the other hand of the present utility model, a kind of display panel is provided, comprise array base palte, wherein, described array base palte is above-mentioned array base palte provided by the utility model.
In the utility model, described array base palte comprises discharge cell, described discharge cell can be by the described data line being connected with this discharge cell and optionally conducting of the described public electrode wire being connected with described discharge cell, thereby realize the corresponding memory capacitance rapid discharge of data line, reduce the generation of afterimage phenomena; On the other hand, described array base palte also comprises static protective unit and detecting unit, described discharge cell, described static protective unit and described detecting unit are all connected with switch signal line 3, thereby in the static on realizing the described data line of minimizing and display panel detection, have simplified the structure of described array base palte.
Be understandable that, above embodiment is only used to principle of the present utility model is described and the illustrative embodiments that adopts, yet the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (14)
1. an array base palte, comprise many data lines and many public electrode wires, it is characterized in that, described array base palte also comprises discharge cell, described at least one, described in data line and at least one, between public electrode wire, be provided with described discharge cell, described discharge cell can be by the data line being connected with this discharge cell and optionally conducting of the described public electrode wire being connected with described discharge cell.
2. array base palte according to claim 1, it is characterized in that, described array base palte also comprises driving circuit, described discharge cell comprises the first film transistor, the transistorized grid of described the first film is connected with the output terminal of described driving circuit, the transistorized source electrode of described the first film is connected with described data line with the one in drain electrode, and another one is connected with described public electrode wire, and described driving circuit can be exported the control signal that described the first film transistor is optionally opened.
3. array base palte according to claim 2, it is characterized in that, described array base palte also comprises the switch signal line of the output terminal that is connected to described driving circuit, the transistorized grid of described the first film is connected with described switch signal line, to be connected with the output terminal of described driving circuit by described switch signal line.
4. according to the array base palte described in any one in claims 1 to 3, it is characterized in that, described array base palte comprises a plurality of described discharge cells, between in many described public electrode wires one and every data line, is provided with a described discharge cell.
5. array base palte according to claim 4, is characterized in that, the public electrode wire being connected with described discharge cell is many first row public electrode wires in described public electrode wire.
6. array base palte according to claim 3, it is characterized in that, described in described switch signal line and at least one, between data line, be provided with static protective unit, the static on described data line can be released into described switch signal line by described static protective unit.
7. array base palte according to claim 6, it is characterized in that, described static protective unit comprises the second thin film transistor (TFT) and the 3rd thin film transistor (TFT), and described the second thin film transistor (TFT) is N-type thin film transistor (TFT), and described the 3rd thin film transistor (TFT) is P type thin film transistor (TFT); Or,
Described the second thin film transistor (TFT) is P type thin film transistor (TFT), and described the 3rd thin film transistor (TFT) is N-type thin film transistor (TFT);
The source electrode of described the second thin film transistor (TFT) is connected with described switch signal line with the one in drain electrode, another one is connected with described data line, the grid of described the second thin film transistor (TFT) is connected with described switch signal line, the source electrode of described the 3rd thin film transistor (TFT) is connected with described data line with the one in drain electrode, another one is connected with described switch signal line, and the grid of described the 3rd thin film transistor (TFT) is connected with described data line.
8. according to the array base palte described in any one in claim 6 or 7, it is characterized in that, between every described data line and described switch signal line, be provided with described static protective unit.
9. array base palte according to claim 1, is characterized in that, described array base palte also comprises the test cell being connected with described data line, and this test cell is for providing test signal to described data line.
10. array base palte according to claim 9, it is characterized in that, described test cell comprises p-wire and at least one the 4th thin film transistor (TFT), the corresponding data line of each the 4th thin film transistor (TFT), each the 4th thin film transistor (TFT) is all connected between corresponding described data line and described p-wire, the grid of described the 4th thin film transistor (TFT) is connected with described switch signal line, the source electrode of described the 4th thin film transistor (TFT) is connected with corresponding described data line with the one in drain electrode, and another one is connected with described p-wire.
11. array base paltes according to claim 10, it is characterized in that, in the pixel region of described array base palte, be provided with red pixel electrode, green pixel electrode and blue pixel electrode, described red pixel electrode, described green pixel electrode and described blue pixel electrode are connected with corresponding data line respectively, and described p-wire is included as described red pixel electrode and provides the first p-wire of test signal, the second p-wire of test signal is provided and provides the 3rd p-wire of test signal for described blue pixel electrode for described green pixel electrode.
12. array base paltes according to claim 10, is characterized in that, are provided with described the 4th thin film transistor (TFT) between every data line and described p-wire.
13. array base paltes according to claim 11, it is characterized in that, described test cell comprises a plurality of the 4th thin film transistor (TFT)s, be positioned at the described red pixel electrode of identical described pixel region, described green pixel electrode and described blue pixel electrode respectively the grid of corresponding described the 4th thin film transistor (TFT) interconnect.
14. 1 kinds of display panels, comprise array base palte, it is characterized in that, described array base palte is the array base palte described in any one in claim 1 to 13.
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|---|---|---|---|
| CN201420234346.3U CN203811952U (en) | 2014-05-08 | 2014-05-08 | Array substrate and display panel |
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| CN201420234346.3U CN203811952U (en) | 2014-05-08 | 2014-05-08 | Array substrate and display panel |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103995407A (en) * | 2014-05-08 | 2014-08-20 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN104297969A (en) * | 2014-10-28 | 2015-01-21 | 京东方科技集团股份有限公司 | Liquid crystal display panel, discharging method thereof and display device |
| CN104570417A (en) * | 2014-12-23 | 2015-04-29 | 上海天马微电子有限公司 | Liquid crystal display screen and electronic equipment |
| CN105467707A (en) * | 2016-01-29 | 2016-04-06 | 京东方科技集团股份有限公司 | Discharge circuit, array substrate, liquid crystal display panel and display device |
| CN108962163A (en) * | 2018-07-13 | 2018-12-07 | 京东方科技集团股份有限公司 | Display driver circuit, display panel and display device |
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2014
- 2014-05-08 CN CN201420234346.3U patent/CN203811952U/en not_active Expired - Lifetime
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103995407A (en) * | 2014-05-08 | 2014-08-20 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN103995407B (en) * | 2014-05-08 | 2016-08-24 | 京东方科技集团股份有限公司 | Array base palte and display floater |
| US9720297B2 (en) | 2014-05-08 | 2017-08-01 | Boe Technology Group Co., Ltd. | Array substrate for improving the speed of discharge of storage capacitance corresponding to a pixel electrode, and display panel having the same |
| CN104297969A (en) * | 2014-10-28 | 2015-01-21 | 京东方科技集团股份有限公司 | Liquid crystal display panel, discharging method thereof and display device |
| CN104570417A (en) * | 2014-12-23 | 2015-04-29 | 上海天马微电子有限公司 | Liquid crystal display screen and electronic equipment |
| CN104570417B (en) * | 2014-12-23 | 2019-05-28 | 上海天马微电子有限公司 | A kind of liquid crystal display and electronic equipment |
| CN105467707A (en) * | 2016-01-29 | 2016-04-06 | 京东方科技集团股份有限公司 | Discharge circuit, array substrate, liquid crystal display panel and display device |
| WO2017128780A1 (en) * | 2016-01-29 | 2017-08-03 | 京东方科技集团股份有限公司 | Discharge circuit, array substrate, liquid crystal display panel, and display device |
| CN105467707B (en) * | 2016-01-29 | 2019-08-09 | 京东方科技集团股份有限公司 | A kind of discharge circuit, array substrate, liquid crystal display panel and display device |
| US10564493B2 (en) | 2016-01-29 | 2020-02-18 | Boe Technology Group Co., Ltd. | Discharge circuit, array substrate, liquid crystal display panel and display device |
| CN108962163A (en) * | 2018-07-13 | 2018-12-07 | 京东方科技集团股份有限公司 | Display driver circuit, display panel and display device |
| US11087706B2 (en) | 2018-07-13 | 2021-08-10 | Hefei Boe Display Technology Co., Ltd. | Display driving circuit having source auxiliary circuit and gate auxiliary circuit and driving method thereof, display panel and display device |
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