CN203811771U - Chip test device - Google Patents
Chip test device Download PDFInfo
- Publication number
- CN203811771U CN203811771U CN201420220940.7U CN201420220940U CN203811771U CN 203811771 U CN203811771 U CN 203811771U CN 201420220940 U CN201420220940 U CN 201420220940U CN 203811771 U CN203811771 U CN 203811771U
- Authority
- CN
- China
- Prior art keywords
- chip
- chip carrier
- probe
- power interface
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The utility model discloses a chip test device, comprising a PCB circuit board and a power interface. The PCB circuit board is provided with a plurality of chip sockets. The plurality of chip sockets are arranged uniformly at interval from up to bottom on the PCB circuit board. The chip socket comprises a slot used for fixing a chip, and probe used to contact with chip pins. The probes are on two sides of the bottom of the slot and extend out of the chip socket. The parts of the probes extending out of the two sides of the chip socket are respectively connected with resistors. The resistors on a side of the chip sockets are respectively connected with the positive end of the power interface, and the resistors on the other side of the chip sockets are respectively connected with the negative end of the power interface. The chip test device makes chip test efficiency greatly improved.
Description
Technical field
The utility model relates to chip testing field, particularly a kind of apparatus for testing chip.
Background technology
When at present semi-conductor chip is tested, by artificial line, one by one the respective pins of chip is connected with testing tool, re-uses testing tool the various unit for electrical property parameters of chip are carried out to test record, test separately one by one, testing efficiency is low.
Utility model content
The purpose of this utility model is to overcome existing above-mentioned deficiency in prior art, and the apparatus for testing chip that a kind of testing efficiency is high is provided.
In order to realize foregoing invention object, the technical solution adopted in the utility model is:
A kind of apparatus for testing chip, comprise PCB circuit board and power interface, on described PCB circuit board, arrange some chip carrier sockets, described some chip carrier sockets on PCB circuit board from top to bottom evenly interval arrange, and this chip carrier socket comprises for the fixing slot of chip and probe for contacting with chip pin, described probe is positioned at the two bottom sides of described slot and stretches out this chip carrier socket, the part that described probe stretches out these chip carrier socket both sides connects respectively a resistance, the resistance that is positioned at this chip carrier socket one side is received respectively the anode of power interface, the resistance that is positioned at this chip carrier socket opposite side is received respectively the negative terminal of power interface.
Preferably, the probe on described chip carrier has multipair, and every a pair of probe is positioned at the two bottom sides of described slot and stretches out this chip carrier.
Preferably, in described slot, insert respectively the test board that a plurality of chips to be measured are installed.
compared with prior art, the beneficial effects of the utility model:
Apparatus for testing chip of the present utility model comprises PCB circuit board and power interface, on described PCB circuit board, arrange some chip carrier sockets, described some chip carrier sockets on PCB circuit board from top to bottom evenly interval arrange, and this chip carrier socket comprises for the fixing slot of chip and probe for contacting with chip pin, described probe is positioned at the two bottom sides of described slot and stretches out this chip carrier socket, the part that described probe stretches out these chip carrier socket both sides connects respectively a resistance, the resistance that is positioned at this chip carrier socket one side is received respectively the anode of power interface, the resistance that is positioned at this chip carrier socket opposite side is received respectively the negative terminal of power interface, during work, power interface energising, some chip carrier sockets insert the test board that chip to be measured is installed, can test a collection of chip simultaneously, testing efficiency improves greatly.
accompanying drawing explanation:
Fig. 1 is the apparatus for testing chip schematic diagram in the utility model embodiment;
Fig. 2 is the chip carrier socket structural representation in Fig. 1.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the utility model only limits to following embodiment, all technology realizing based on the utility model content all belong to scope of the present utility model.
Apparatus for testing chip as shown in Figure 1, comprise PCB circuit board 2 and power interface 1, on described PCB circuit board 2, arrange some chip carrier sockets 3, described some chip carrier sockets 3 on PCB circuit board from top to bottom evenly interval arrange, in figure with 2 behaviors examples explanations, 3 chip carrier sockets of every row, referring to Fig. 2, this chip carrier socket 3 comprises pedestal 301, on pedestal 301, have for the fixing slot 302 of chip and probe 303 for contacting with chip pin, described probe 303 is positioned at the two bottom sides of described slot 302 and stretches out this chip carrier socket 3, the part that described probe 303 stretches out these chip carrier socket 3 both sides connects respectively a resistance 4, the resistance 4 that is positioned at these chip carrier socket 3 one sides is received respectively the anode of power interface 1, the resistance 4 that is positioned at these chip carrier socket 3 opposite sides is received respectively the negative terminal of power interface 1.Probe 303 on described chip carrier socket 3 has multipair, take 3 pairs as example explanation in figure, and every a pair of probe 303 is positioned at the two bottom sides of described slot 302 and stretches out this chip carrier socket 3.The interior test board (not shown) that a plurality of chips to be measured are installed of inserting respectively of described slot 302, chip pin contacts with the copper conductor on test board, test board bottom has a plurality of conductive contact points, be connected with wire on it respectively and then realization is connected with chip pin, test board inserts after slot, and the conductive contact point on test board and probe in slot contact respectively realizes being electrically connected to of chip respective pins and chip carrier socket on proving installation.
Apparatus for testing chip of the present utility model comprises PCB circuit board 2 and power interface 1, on described PCB circuit board 2, arrange some chip carrier sockets 3, described some chip carrier sockets 3 on PCB circuit board 2 from top to bottom evenly interval arrange, and this chip carrier socket 3 comprises for the fixing slot of chip and probe for contacting with chip pin, described probe is positioned at the two bottom sides of described slot and stretches out this chip carrier socket, the part that described probe stretches out these chip carrier socket both sides connects respectively a resistance, the resistance that is positioned at this chip carrier socket one side is received respectively the anode of power interface, the resistance that is positioned at this chip carrier socket opposite side is received respectively the negative terminal of power interface, during work, power interface energising, some chip carrier sockets insert the test board that chip to be measured is installed, can test a collection of chip simultaneously, testing efficiency improves greatly.
By reference to the accompanying drawings embodiment of the present utility model is had been described in detail above, but the utility model is not restricted to above-mentioned embodiment, in the spirit and scope situation of claim that does not depart from the application, those skilled in the art can make various modifications or remodeling.
Claims (3)
1. an apparatus for testing chip, comprise PCB circuit board and power interface, it is characterized in that, on described PCB circuit board, arrange some chip carrier sockets, described some chip carrier sockets on PCB circuit board from top to bottom evenly interval arrange, and this chip carrier socket comprises for the fixing slot of chip and probe for contacting with chip pin, described probe is positioned at the two bottom sides of described slot and stretches out this chip carrier socket, the part that described probe stretches out these chip carrier socket both sides connects respectively a resistance, the resistance that is positioned at this chip carrier socket one side is received respectively the anode of power interface, the resistance that is positioned at this chip carrier socket opposite side is received respectively the negative terminal of power interface.
2. apparatus for testing chip according to claim 1, is characterized in that, the probe on described chip carrier has multipair, and every a pair of probe is positioned at the two bottom sides of described slot and stretches out this chip carrier.
3. apparatus for testing chip according to claim 1, is characterized in that, inserts respectively the test board that a plurality of chips to be measured are installed in described slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420220940.7U CN203811771U (en) | 2014-04-30 | 2014-04-30 | Chip test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420220940.7U CN203811771U (en) | 2014-04-30 | 2014-04-30 | Chip test device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203811771U true CN203811771U (en) | 2014-09-03 |
Family
ID=51450504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420220940.7U Expired - Fee Related CN203811771U (en) | 2014-04-30 | 2014-04-30 | Chip test device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203811771U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783662A (en) * | 2016-12-29 | 2017-05-31 | 江苏中科君芯科技有限公司 | For the pedestal of rapid evaluation igbt performance |
| CN109342928A (en) * | 2018-11-01 | 2019-02-15 | 南京工业大学 | A kind of apparatus for testing chip and method |
-
2014
- 2014-04-30 CN CN201420220940.7U patent/CN203811771U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783662A (en) * | 2016-12-29 | 2017-05-31 | 江苏中科君芯科技有限公司 | For the pedestal of rapid evaluation igbt performance |
| CN106783662B (en) * | 2016-12-29 | 2023-11-17 | 江苏中科君芯科技有限公司 | Base for rapidly evaluating performance of insulated gate bipolar transistor |
| CN109342928A (en) * | 2018-11-01 | 2019-02-15 | 南京工业大学 | A kind of apparatus for testing chip and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140903 Termination date: 20160430 |