CN203721727U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203721727U CN203721727U CN201320877890.5U CN201320877890U CN203721727U CN 203721727 U CN203721727 U CN 203721727U CN 201320877890 U CN201320877890 U CN 201320877890U CN 203721727 U CN203721727 U CN 203721727U
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- 239000000758 substrate Substances 0.000 title abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims description 69
- 238000009413 insulation Methods 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000002161 passivation Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 18
- 238000005516 engineering process Methods 0.000 abstract description 8
- 230000000903 blocking effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 113
- 238000000034 method Methods 0.000 description 35
- 239000000203 mixture Substances 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 15
- 239000010408 film Substances 0.000 description 13
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
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- 239000003990 capacitor Substances 0.000 description 6
- 239000012774 insulation material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910000544 Rb alloy Inorganic materials 0.000 description 1
- LADUOVJEPCTFNX-UHFFFAOYSA-N [Rb].[AlH3] Chemical compound [Rb].[AlH3] LADUOVJEPCTFNX-UHFFFAOYSA-N 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- JYMITAMFTJDTAE-UHFFFAOYSA-N aluminum zinc oxygen(2-) Chemical compound [O-2].[Al+3].[Zn+2] JYMITAMFTJDTAE-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
An embodiment of the utility model provides an array substrate and a display device and relates to the field of display technology. The array substrate includes multiple grid lines arranged in a crisscrossed manner and a data line. An etching blocking layer and a first transparent electrode are formed on the surface of the data line successively. A part of the data line away from the grid lines and the grid lines are formed on the surface of the transparent substrate in the same layer. The data line breaks in the grid line area provided with a source-drain metal layer pattern. The source-drain metal layer pattern is isolated from the grid lines electrically. The data line disposed on two sides of the grid lines are connected together electrically through the source-drain metal layer. According to the utility model, parasitic capacitance between the data line and the transparent electrode can be reduced, so that the quality of the display device can be improved.
Description
Technical field
The utility model relates to Display Technique field, relates in particular to a kind of array base palte and display unit.
Background technology
Along with TFT-LCD(Thin Film Transistor Liquid Crystal Display, Thin Film Transistor-LCD) development of Display Technique, various novel semi-conductor elements and the application technology in display unit thereof have also obtained tremendous progress thereupon.
In the middle of the manufacture process of existing display floater TFT, in order further to improve the aperture opening ratio of display floater, conventionally adopt transparent metal oxide materials (as tin indium oxide ITO) to make source-drain electrode and the data wire of TFT, a kind of like this array base palte can be as shown in Figure 1 along the cross section structure of data wire direction, the grid 11 and the gate insulation layer 12 that comprise the TFT that is formed on successively transparency carrier 10 surfaces, data wire 13 is formed on the surface of gate insulation layer 12, this data wire 13 adopts ITO material to make, the surface of data wire 13 is formed with etching barrier layer 14 and transparency electrode 15 successively.
Compare with traditional array base palte, a kind of like this array base palte of structure is made simple and is had a higher aperture opening ratio.But its weak point is, in array base palte as shown in Figure 1, between data wire 13 and transparency electrode 15, there is one section of long overlapping region, so, the in the situation that of energising, due to level difference, between data wire 14 and transparency electrode 15, will produce parasitic capacitance Cdc, in the moment of data wire 14 input drive signals, existence due to parasitic capacitance, on data wire 14, voltage signal variation from high to low can make the corresponding generation change in voltage of transparency electrode 15, thereby cause the unexpected reduction of liquid crystal voltage in pixel, make display frame flicker, data wire time delay and power consumption also will increase thereupon.
Utility model content
Embodiment of the present utility model provides a kind of array base palte and display unit, can reduce the parasitic capacitance between data wire and transparency electrode, improves the quality of display unit.
The one side of the utility model embodiment, provides a kind of array base palte, comprising: many grid lines that transverse and longitudinal is arranged in a crossed manner and data wire, and the surface of described data wire is formed with etching barrier layer and the first transparency electrode successively; The part away from described grid line of described data wire is formed on the surface of transparency carrier with layer with described grid line, described data wire disconnects in described grid region;
Described grid region has the pattern that metal level is leaked in source, and the pattern and the insulation of described grid line of metal level leaked in described source, and the described data wire that is positioned at described grid line both sides is electrically connected to by the pattern of described source leakage metal level.
Further, described array base palte also comprises:
The first insulating barrier, described the first insulating barrier covers the part away from described grid line of described grid line and described data wire, and in described grid region, the described data wire that is positioned at described grid line both sides partly exposes the surface at described the first insulating barrier;
In described grid region, the pattern of described source leakage metal level is formed on the surface of described the first insulating barrier.
Further, it is characterized in that, described array base palte also comprises:
The grid of TFT, the grid of described TFT and described grid line are made with layer;
Described the first insulating barrier is formed on the surface of the grid of described TFT, and at the channel region of described TFT, the grid part of described TFT is exposed the surface at described the first insulating barrier.
Further, described array base palte also comprises:
Be formed on successively the described gate insulation layer of gate surface of described TFT and the pattern of semiconductor active layer;
The pattern of described semiconductor active layer adopts the transparent metal oxide material that is characteristic of semiconductor to make.
Or described array base palte also comprises:
Be formed on the gate insulation layer of described the first surface of insulating layer;
Described etching barrier layer is formed on the surface of described gate insulation layer;
In described grid region, via hole runs through described etching barrier layer and described gate insulation layer, to expose described first insulating barrier of bottom and the described data wire of described grid line both sides.
In the utility model embodiment, described array base palte also comprises:
The second insulating barrier, described the second insulating barrier covers described grid line and described data wire;
In described grid region, the pattern of described source leakage metal level is formed on the surface of described the second insulating barrier, and the pattern of described source leakage metal level is electrically connected to the described data wire that is positioned at described grid line both sides respectively by via hole.
Further, described array base palte also comprises:
Be formed on the pattern of the passivation layer on described the first transparency electrode surface, the pattern covers of described passivation layer is positioned at the pattern of the source leakage metal level of described grid region;
And the second transparency electrode that is formed on described passivation layer surface.
Wherein, described the first transparency electrode is pixel electrode, and described the second transparency electrode is public electrode;
And described the first transparency electrode is planar structure, described the second transparency electrode is spaced list structure.
On the other hand, the utility model embodiment also provides a kind of display unit, and described display unit can comprise array base palte as above.
A kind of like this array base palte and display unit that the utility model embodiment provides, by data wire and grid line are made with layer, and data wire disconnects in grid region, the pattern that employing is arranged at the source leakage metal level of grid region is electrically connected to the data wire disconnecting, so, compared with prior art, on the basis that has guaranteed grid line and data wire quality, can significantly increase the spacing between data wire and transparency electrode, like this because the spacing between parallel plate capacitor two electrodes increases, capacitance is obviously reduced, thereby can effectively reduce the parasitic capacitance Cdc between data wire and transparency electrode, and then avoid the output leaping voltage that produces because parasitic capacitance is excessive bad, effectively improve display frame flicker, reduce data wire time delay and power consumption, improve the quality of display unit.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of a kind of array base palte in prior art;
The structural representation of a kind of array base palte that Fig. 2 provides for the utility model embodiment;
The structural representation of another array base palte that Fig. 3 provides for the utility model embodiment;
The schematic flow sheet of a kind of manufacturing method of array base plate that Fig. 4 provides for the utility model embodiment;
The schematic flow sheet of another manufacturing method of array base plate that Fig. 5 provides for the utility model embodiment;
Fig. 6 is for forming board structure partial top view after insulating layer pattern and A-A thereof to cutaway view;
Fig. 7 is for forming board structure partial top view after the grid of grid line, data wire and TFT and B-B thereof to cutaway view;
Fig. 8 is for forming the structural representation after insulation material layer;
Fig. 9 is for forming the board structure schematic diagram after the pattern of the first insulating barrier;
Figure 10 is for forming the board structure schematic diagram after gate insulation layer;
Figure 11 is for forming board structure partial top view after semiconductor active layer and C-C thereof to cutaway view;
Figure 12 is for forming the board structure schematic diagram after etching barrier layer;
Figure 13 is that substrate shown in Figure 12 forms board structure partial top view after via hole and D-D thereof to cutaway view;
Figure 14 is that board structure partial top view after the pattern of metal level and the source-drain electrode of TFT and E-E thereof are leaked to cutaway view in formation source;
Figure 15 is for forming board structure partial top view after the first transparency electrode and F-F thereof to cutaway view;
Figure 16 is for forming the board structure schematic diagram after passivation layer;
Figure 17 is for forming the board structure partial top view after the second transparency electrode.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The array base palte that the utility model embodiment provides, as shown in Figure 2, comprising: many grid lines 21 that transverse and longitudinal is arranged in a crossed manner and data wire 22, the surface of data wire 22 is formed with etching barrier layer 23 and the first transparency electrode 241 successively.Wherein, the part away from described grid line of data wire 22 is formed on the surface of transparency carrier 20 with layer with grid line 21, and data wire 22 disconnects in grid line 21 regions.
Concrete, grid line 21 and data wire 22 can adopt with layer metal material, by a composition technique, form respectively the pattern of corresponding grid line 21 or data wire 22 on the surface of transparency carrier 20.
Further, grid line 21 regions have the pattern 25 that metal level is leaked in source, and the pattern 25 and grid line 21 insulation of metal level leaked in this source, and the data wire 22 that is positioned at grid line 21 both sides leaks pattern 25 electrical connections of metal level by source.
A kind of like this array base palte that the utility model embodiment provides, by data wire and grid line are made with layer, and data wire disconnects in grid region, the pattern that employing is arranged at the source leakage metal level of grid region is electrically connected to the data wire disconnecting, so, compared with prior art, on the basis that has guaranteed grid line and data wire quality, can significantly increase the spacing between data wire and transparency electrode, like this because the spacing between parallel plate capacitor two electrodes increases, capacitance is obviously reduced, thereby can effectively reduce the parasitic capacitance Cdc between data wire and transparency electrode, and then avoid the output leaping voltage that produces because parasitic capacitance is excessive bad, effectively improve display frame flicker, reduce data wire time delay and power consumption, improve the quality of display unit.
Concrete, as shown in Figure 2, this array base palte can also comprise:
The first insulating barrier 26, this first insulating barrier 26 covers the part away from described grid line of grid line 21 and data wire 22, and in grid line 21 regions, data wire 22 parts that are positioned at grid line 21 both sides are exposed the surface at this first insulating barrier 26.
In grid line 21 regions, the pattern 25 of source leakage metal level is formed on the surface of the first insulating barrier 26.
Concrete, data wire 22 parts that are positioned at grid line 21 both sides in order to realize are exposed the surface at this first insulating barrier 26, can by composition technique, form the insulating layer pattern 261 with certain altitude in advance on the surface of transparency carrier 20, this insulating layer pattern 261 can be positioned at the both sides of grid line 21.On the surface that is formed with the substrate of insulating layer pattern 261, further form grid line 21 and data wire 22, its two segment data lines 22 that break all have one end to cover the surface of insulating layer pattern 261.Further by depositing insulating layer material at least to expose the data wire that is positioned at insulating layer pattern 261 surfaces, thereby finally form the first insulating barrier 26.
Certainly, above is only also the illustrating of the first insulating barrier 26 have above-mentioned feature to forming, and also can adopt other known techniques to form the first insulating barrier 26 of above-mentioned a kind of like this structure, and the utility model does not limit this.
A kind of like this array base palte of structure is compared with array base palte of the prior art, can significantly see, in the array base palte shown in Fig. 2, the space D between data wire 22 and the first transparency electrode 241 ' be far longer than the space D between data wire 13 and transparency electrode 15 in Fig. 1.Known according to parallel plate capacitor formula C=ε S/d, in order to reduce the capacitance between parallel pole, when other conditions are constant, can realize reducing of electric capacity by the spacing increasing between two electrodes.In the utility model embodiment, in order to effectively reduce the parasitic capacitance between data wire 22 and the first transparency electrode 241, can increase the spacing between data wire 22 and the first transparency electrode 241, compare with the spacing between two electrodes in prior art, capacitance between two electrodes reduces, thereby can effectively reduce the impact of the leaping voltage that parasitic capacitance produces.
It should be noted that, in the utility model embodiment, array base palte can also comprise the grid (not shown in Fig. 2) of TFT, and the grid of this TFT and grid line 21 are made with layer.
Wherein, the first insulating barrier 26 is formed on the surface of the grid of this TFT, and at the channel region of TFT, the grid part of this TFT is exposed the surface at the first insulating barrier 26.
So, by make the first insulating barrier 26 at the channel region of TFT, can raise the grid of the TFT that is positioned at this region, so that the channel region of TFT and not poor less than obvious section between the data wire of grid region, so, in the process of following process, can avoid owing to existing compared with poor generation of large section, opening circuit between the source-drain electrode of TFT and the pattern 25 of source leakage metal level, thereby improve the quality of display floater.
Further, array base palte can also comprise the gate insulation layer of the gate surface that is formed on successively TFT and the pattern of semiconductor active layer (not shown in Fig. 2).
Wherein, the pattern of semiconductor active layer can adopt the transparent metal oxide material that is characteristic of semiconductor to make.For example, metal-oxide film can comprise: IGZO(indium gallium zinc oxide), IGO(indium gallium oxide), ITZO(indium tin zinc oxide), AlZnO(aluminium zinc oxide) at least one.Adopt a kind of like this transparent metal oxide material to replace a-Si(amorphous silicon) or LTPS(low temperature polycrystalline silicon) semiconductor active layer of TFT formed, with respect to a-Si TFT or LTPS TFT, there is preparation temperature requirement low, the advantages such as mobility height, this technology can be applicable to that high frequency shows and high-resolution shows product, and with respect to LTPS TFT technology, has that equipment investment cost is low, operation guarantee low cost and other advantages.
In array base palte as shown in Figure 2, can also comprise:
Be formed on the gate insulation layer 27 on the first insulating barrier 26 surfaces.Etching barrier layer 23 is formed on the surface of gate insulation layer 27.
In grid line 21 regions, via hole runs through etching barrier layer 23 and gate insulation layer 27, to expose the first insulating barrier 26 of bottom and the data wire 22 of grid line 21 both sides.
So, can pass through in the region of this via hole the further pattern 25 of formation source leakage metal level of composition technique, so effectively the overlay area of the pattern 25 of metal level is leaked in restriction source.Adopt a kind of like this array base palte of structure, owing to further having increased, there are certain thickness the first insulating barrier 26 and gate insulation layer 27 structures between data wire 22 and the first transparency electrode 241, thereby can further increase the spacing between data wire 22 and the first transparency electrode 241, reduce the parasitic capacitance Cdc existing between data wire 22 and the first transparency electrode 241.
Or the structure of the array base palte that the utility model embodiment provides can also as shown in Figure 3, comprise:
The second insulating barrier 262, this second insulating barrier 262 covers grid line 21 and data wire 22.
In grid line 21 regions, the pattern 25 of source leakage metal level is formed on the surface of the second insulating barrier 262, and the pattern 25 of source leakage metal level is electrically connected to the data wire 22 that is positioned at grid line 21 both sides respectively by via hole.
In a kind of like this array base palte of structure, all the other structures all can be with reference to the array base palte shown in figure 2, be with the difference of the array base palte shown in Fig. 2, a kind of like this array base palte of structure is without form in advance the pattern 261 of insulating barrier on the surface of transparency carrier, thereby can simplify to a certain extent the manufacture craft of array base palte, reduce production difficulty.
In the utility model embodiment, the first insulating barrier 26 and the second insulating barrier 262 all can adopt the materials such as organic resin material with good insulation properties to make, and the utility model does not limit this.
It should be noted that, the TFT-LCD array base palte that the utility model embodiment provides goes for FFS(Fringe Field Switching, fringe field switching) type, AD-SDS(Advanced-Super Dimensional Switching, referred to as ADS, senior super dimension field switch) type, IPS(In Plane Switch, transverse electric field effect) type, TN(Twist Nematic, the twisted-nematic) production of the liquid crystal indicator of the type such as type.Wherein, ADS technology is by the longitudinal electric field formation multi-dimensional electric field of the parallel electric field that in same plane, pixel electrode edge produces and pixel electrode layer and the generation of public electrode interlayer, make in liquid crystal cell between pixel electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation conversion, thereby to have improved planar orientation be liquid crystal operating efficiency and increased light transmission efficiency.
Above-mentioned which kind of liquid crystal indicator all comprises color membrane substrates and the array base palte that box is shaped.Different, the public electrode of TN type display unit is arranged on color membrane substrates, and pixel electrode is arranged on array base palte; Public electrode and the pixel electrode of FFS type display unit, ADS type display unit and IPS type display unit are all arranged on array base palte.
Concrete, as shown in Figure 2, in the utility model embodiment, be to take the explanation that FFS type display unit carries out as example.Wherein, array base palte can also comprise:
Be formed on the pattern 28 of the passivation layer on the first transparency electrode 241 surfaces, the pattern 28 of this passivation layer covers the pattern 25 of the source leakage metal level that is positioned at grid line 21 regions.
And the second transparency electrode 242 that is formed on this passivation layer surface.
Wherein, the first transparency electrode 241 can be pixel electrode, and the second transparency electrode 242 can be public electrode, and this first transparency electrode 241 can be planar structure, and the second transparency electrode 242 can be spaced list structure.
In the array base palte of described FFS type display unit, the different layer of described public electrode and described pixel electrode arranges, and optional, the electrode that is positioned at upper strata comprises a plurality of strip electrodes, and the electrode that is positioned at lower floor can comprise a plurality of strip electrodes or for plate shaped.In the utility model embodiment, be the electrode that is positioned at lower floor be that plate shaped planar structure is the explanation that example is carried out.Wherein, different layer arranges at least two kinds of patterns, and at least two kinds of different layer settings of pattern refer to, at least double-layer films forms at least two kinds of patterns by composition technique respectively.For two kinds of different layer settings of pattern, refer to, by composition technique, by double-layer films, respectively form a kind of pattern.For example, the different layer setting of public electrode and pixel electrode refers to: by ground floor transparent conductive film, by composition technique, form lower electrode, by second layer transparent conductive film, by composition technique, form upper electrode, wherein, lower electrode is public electrode (or pixel electrode), and upper electrode is pixel electrode (or public electrode).
The array base palte of a kind of like this structure that the utility model embodiment provides goes for IPS type display unit equally, different from FFS type display unit is, described public electrode and described pixel electrode arrange with layer, described public electrode comprises a plurality of the first strip electrodes, described pixel electrode comprises a plurality of the second strip electrodes, and described the first strip electrode and described the second bar shaped electrode gap arrange.Wherein, with layer, arrange at least two kinds of patterns; At least two kinds of patterns refer to layer setting: same film is formed at least two kinds of patterns by composition technique.For example, public electrode and pixel electrode refer to layer setting: by same transparent conductive film, by composition technique, form pixel electrode and public electrode.Wherein, pixel electrode refers to the electrode for example, being electrically connected to data wire by switch element (, can be thin-film transistor), and public electrode refers to the electrode being electrically connected to public electrode wire.
The display unit that the utility model embodiment provides, comprises array base palte as above.
This array base palte specifically comprises many grid lines and the data wire that transverse and longitudinal is arranged in a crossed manner, and the surface of data wire is formed with etching barrier layer and the first transparency electrode successively.Wherein, data wire and grid line are made with layer, and data wire disconnects in grid region; In grid region, also have the pattern that metal level is leaked in source, the pattern and grid line insulation of metal level leaked in this source, and the data wire that is positioned at grid line both sides is electrically connected to by the pattern of this source leakage metal level.
It should be noted that display unit provided by the utility model can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer.
A kind of like this display unit that the utility model embodiment provides, comprise array base palte, by data wire and grid line are made with layer, and data wire disconnects in grid region, the pattern that employing is arranged at the source leakage metal level of grid region is electrically connected to the data wire disconnecting, so, compared with prior art, on the basis that has guaranteed grid line and data wire quality, can significantly increase the spacing between data wire and transparency electrode, like this because the spacing between parallel plate capacitor two electrodes increases, capacitance is obviously reduced, thereby can effectively reduce the parasitic capacitance Cdc between data wire and transparency electrode, and then avoid the output leaping voltage that produces because parasitic capacitance is excessive bad, effectively improve display frame flicker, reduce data wire time delay and power consumption, improve the quality of display unit.
The utility model embodiment also provides a kind of manufacturing method of array base plate, and the method as shown in Figure 4, comprising:
S401, on the surface of transparency carrier, with layer, form grid line and a data wire, data wire disconnects in grid region, and the part away from grid line of data wire is made with layer with grid line.
Concrete, grid line and data wire can adopt with layer metal material, by a composition technique, form respectively the pattern of corresponding grid line or data wire on the surface of transparency carrier.
S402, on the substrate that is formed with grid line and data wire, the pattern of metal level is leaked in corresponding grid region formation source, and the pattern that metal level is leaked in this source insulate with grid line, is positioned at the pattern that the data wire of grid line both sides leaks metal level by source and is electrically connected to.
A kind of like this array base palte and manufacture method thereof that the utility model embodiment provides, by data wire and grid line are made with layer, and data wire disconnects in grid region, the pattern that employing is arranged at the source leakage metal level of grid region is electrically connected to the data wire disconnecting, so, compared with prior art, on the basis that has guaranteed grid line and data wire quality, can significantly increase the spacing between data wire and transparency electrode, like this because the spacing between parallel plate capacitor two electrodes increases, capacitance is obviously reduced, thereby can effectively reduce the parasitic capacitance Cdc between data wire and transparency electrode, and then avoid the output leaping voltage that produces because parasitic capacitance is excessive bad, effectively improve display frame flicker, reduce data wire time delay and power consumption, improve the quality of display unit.
Further, the manufacturing method of array base plate that the utility model embodiment provides, as shown in Figure 5, specifically comprises:
S501, on the surface of transparency carrier, by composition technique, form insulating layer pattern, in grid region, insulating layer pattern is positioned at grid line both sides.
In the middle of the actual production process of array base palte, transparency carrier can be specifically that the transparent material that adopts glass or transparent resin etc. to have certain robustness is made.On transparency carrier, need to adopt a composition technique to form insulating layer pattern.
For example, can be first at surface-coated one deck of transparency carrier, there is certain thickness organic resin material, by thering is the mask of specific pattern, carry out the final insulating layer pattern 261 forming as shown in Figure 6 of exposure imaging.
Wherein, as shown in the vertical view of array base palte in Fig. 6, insulating layer pattern 261 can be respectively formed at the both sides of channel region and the grid line of TFT.
S502, on the surface that is formed with the substrate of insulating layer pattern, by composition technique, form grid line and data wire, data line bit covers the surface of insulating layer pattern in the end of grid line both sides.
For example, can adopt plasma reinforced chemical vapour deposition (PECVD), magnetron sputtering, thermal evaporation or other film build method being formed with on the substrate of insulating layer pattern, form metal level.Wherein, this metal level can be the single thin film that the metals such as molybdenum, aluminium, aluminium rubidium alloy, tungsten, chromium, copper form, and can be also the plural layers that above metallic multilayer forms.Surface at this metal level is formed with photoresist, by having, the mask plate of specific pattern carries out exposure imaging so that photoresist produces pattern, peel off the metal level that does not cover photoresist place, the surface of the final pattern at the second insulating barrier forms grid 71, grid line 21 and the data wire 22 of TFT, and its structure can be as shown in the vertical view of array base palte in Fig. 7.
S503, at the surface deposition of grid line and data wire, form insulation material layer.
For example, can there is certain thickness organic resin material at the surface-coated one deck that is formed with the substrate of grid line and data wire, as shown in Figure 8, to form insulation material layer 260.This insulation material layer 260 will cover grid line and data wire completely.
S504, employing cineration technics are processed insulation material layer, at least to expose the data wire that is positioned at insulating layer pattern surface, form the first insulating barrier.
As shown in Figure 9, this insulation material layer 260 is by the processing of cineration technics, and its thickness reduces integral body, until expose the surface of data wire, finally forms the first insulating barrier 26 of patterning.In the utility model embodiment, be that to adopt cineration technics be the explanation that example is carried out, should be appreciated that in order to expose the surface of data wire, can also adopt other various known composition technique, the utility model is not restricted this.
So, can form the first insulating barrier on the surface of the part away from grid line of grid line and data wire, in grid region, the described data wire that is positioned at grid line both sides partly exposes the surface at the first insulating barrier.
S505, on the surface of substrate that is formed with the pattern of the first insulating barrier, form gate insulation layer.
As shown in figure 10, visible, on the surface of substrate of pattern 26 that is formed with the first insulating barrier, be formed with the gate insulation layer 27 of thickness homogeneous.
S506, on the surface of the area of grid of the corresponding TFT of gate insulation layer, by composition PROCESS FOR TREATMENT, form the pattern of semiconductor active layer.
For example, can form the semiconductor active layer with characteristic of semiconductor at the substrate surface that is formed with said structure, by mask exposure, form the pattern 111 of the semiconductor active layer as shown in array base palte vertical view in Figure 11.
It should be noted that, in the utility model embodiment, the pattern 23 of semiconductor active layer can adopt the transparent metal oxide material that is characteristic of semiconductor to make.For example, metal-oxide film can comprise: at least one in IGZO, IGO, ITZO, AlZnO.Adopt a kind of like this transparent metal oxide material to replace a-Si(amorphous silicon) or LTPS(low temperature polycrystalline silicon) semiconductor active layer of TFT formed, with respect to a-Si TFT or LTPSTFT, there is preparation temperature requirement low, the advantages such as mobility height, this technology can be applicable to that high frequency shows and high-resolution shows product, and with respect to LTPS TFT technology, has that equipment investment cost is low, operation guarantee low cost and other advantages.
S507, on the surface that is formed with the substrate of semiconductor active layer, form etching barrier layer.
The pattern 23 of etching barrier layer can be as shown in figure 12, concrete, can be by applying or deposition-etch barrier layer being formed with on the substrate of said structure.
S508, on the surface of etching barrier layer, by composition PROCESS FOR TREATMENT, form the via hole that runs through etching barrier layer and gate insulation layer, to expose the first insulating barrier of bottom and the data wire of grid line both sides.
The board structure forming can be as shown in figure 13.
So, can pass through in the region of this via hole the further pattern 25 of formation source leakage metal level of composition technique, so effectively the overlay area of the pattern 25 of metal level is leaked in restriction source.Adopt a kind of like this array base palte of structure, owing to further having increased, there are certain thickness the first insulating barrier 26 and gate insulation layer 27 structures between data wire 22 and the first transparency electrode 241, thereby can further increase the spacing between data wire 22 and the first transparency electrode 241, reduce the parasitic capacitance Cdc existing between data wire 22 and the first transparency electrode 241.
S509, on the surface of the first insulating barrier, corresponding grid region is leaked the pattern of metal level by composition technique formation source.
The board structure that forms the pattern 25 of active leakage metal level can be as shown in figure 14.
S510, on the surface that is formed with the substrate of etching barrier layer, by composition PROCESS FOR TREATMENT, form the first transparency electrode.
The board structure that is formed with the first transparency electrode 241 can be as shown in figure 15
S511, on the surface of the first transparency electrode, by composition PROCESS FOR TREATMENT, form the pattern of passivation layer, the pattern of metal level is leaked in the source that the pattern covers of this passivation layer is positioned at grid region.
The board structure that is formed with the pattern 28 of passivation layer can be as shown in figure 16.
S512, on the surface of passivation layer, by composition PROCESS FOR TREATMENT, form the second transparency electrode.
The board structure vertical view that is formed with the second transparency electrode 242 can be as shown in figure 17, and its schematic cross-section along G-G direction is the array base-plate structure schematic diagram shown in Fig. 2.
Certainly, above is only also to take the explanation that the manufacture method of Fig. 2 carries out as example, in the utility model embodiment, can adopt array base palte as shown in Figure 3 equally, need to carry out certain adjustment to processing step accordingly.Wherein each independently production process all can be with reference to operation requirement of the prior art, the utility model does not limit this.
It should be noted that, be to take the explanation that FFS type display unit carries out as example in the utility model embodiment.Wherein, the first transparency electrode 241 can be pixel electrode, and the second transparency electrode 242 can be public electrode, and this first transparency electrode 241 can be planar structure, and the second transparency electrode 242 can be spaced list structure.
In the array base palte of described FFS type display unit, the different layer of described public electrode and described pixel electrode arranges, and optional, the electrode that is positioned at upper strata comprises a plurality of strip electrodes, and the electrode that is positioned at lower floor can comprise a plurality of strip electrodes or for plate shaped.In the utility model embodiment, be the electrode that is positioned at lower floor be that plate shaped planar structure is the explanation that example is carried out.Wherein, different layer arranges at least two kinds of patterns, and at least two kinds of different layer settings of pattern refer to, at least double-layer films forms at least two kinds of patterns by composition technique respectively.For two kinds of different layer settings of pattern, refer to, by composition technique, by double-layer films, respectively form a kind of pattern.For example, the different layer setting of public electrode and pixel electrode refers to: by ground floor transparent conductive film, by composition technique, form lower electrode, by second layer transparent conductive film, by composition technique, form upper electrode, wherein, lower electrode is public electrode (or pixel electrode), and upper electrode is pixel electrode (or public electrode).
The array base palte of a kind of like this structure that the utility model embodiment provides goes for the production of the various display unit array base paltes such as ADS type display unit, IPS type display unit or TN type display unit equally.Can expect, when the position of pixel electrode or public electrode or shape and structure change, by changing the correlation step in above-mentioned operation, can realize equally the production of various array of structures substrates, in the utility model embodiment, this not enumerated.
Adopt above-mentioned manufacturing method of array base plate, can significantly increase the spacing between data wire and transparency electrode, like this because the spacing between parallel plate capacitor two electrodes increases, capacitance is obviously reduced, thereby can effectively reduce the parasitic capacitance Cdc between data wire and transparency electrode, and then avoid the output leaping voltage that produces because parasitic capacitance is excessive bad, effectively improve display frame flicker, reduce data wire time delay and power consumption, improve the quality of display unit.
The above; it is only embodiment of the present utility model; but protection range of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, within all should being encompassed in protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of described claim.
Claims (9)
1. an array base palte, comprising: many grid lines that transverse and longitudinal is arranged in a crossed manner and data wire, and the surface of described data wire is formed with etching barrier layer and the first transparency electrode successively; It is characterized in that, the part away from described grid line of described data wire is formed on the surface of transparency carrier with layer with described grid line, and described data wire disconnects in described grid region;
Described grid region has the pattern that metal level is leaked in source, and the pattern and the insulation of described grid line of metal level leaked in described source, and the described data wire that is positioned at described grid line both sides is electrically connected to by the pattern of described source leakage metal level.
2. array base palte according to claim 1, is characterized in that, described array base palte also comprises:
The first insulating barrier, described the first insulating barrier covers the part away from described grid line of described grid line and described data wire, and in described grid region, the described data wire that is positioned at described grid line both sides partly exposes the surface at described the first insulating barrier;
In described grid region, the pattern of described source leakage metal level is formed on the surface of described the first insulating barrier.
3. array base palte according to claim 2, is characterized in that, described array base palte also comprises:
The grid of TFT, the grid of described TFT and described grid line are made with layer;
Described the first insulating barrier is formed on the surface of the grid of described TFT, and at the channel region of described TFT, the grid part of described TFT is exposed the surface at described the first insulating barrier.
4. array base palte according to claim 3, is characterized in that, described array base palte also comprises:
Be formed on successively the gate insulation layer of gate surface and the pattern of semiconductor active layer of described TFT;
The pattern of described semiconductor active layer adopts the transparent metal oxide material that is characteristic of semiconductor to make.
5. array base palte according to claim 2, is characterized in that, described array base palte also comprises:
Be formed on the gate insulation layer of described the first surface of insulating layer;
Described etching barrier layer is formed on the surface of described gate insulation layer;
In described grid region, via hole runs through described etching barrier layer and described gate insulation layer, to expose described first insulating barrier of bottom and the described data wire of described grid line both sides.
6. array base palte according to claim 1, is characterized in that, described array base palte also comprises:
The second insulating barrier, described the second insulating barrier covers described grid line and described data wire;
In described grid region, the pattern of described source leakage metal level is formed on the surface of described the second insulating barrier, and the pattern of described source leakage metal level is electrically connected to the described data wire that is positioned at described grid line both sides respectively by via hole.
7. according to the arbitrary described array base palte of claim 1-6, it is characterized in that, described array base palte also comprises:
Be formed on the pattern of the passivation layer on described the first transparency electrode surface, the pattern covers of described passivation layer is positioned at the pattern of the source leakage metal level of described grid region;
And the second transparency electrode that is formed on described passivation layer surface.
8. array base palte according to claim 7, is characterized in that, described the first transparency electrode is pixel electrode, and described the second transparency electrode is public electrode;
And described the first transparency electrode is planar structure, described the second transparency electrode is spaced list structure.
9. a display unit, is characterized in that, described display unit comprises the array base palte as described in as arbitrary in claim 1-8.
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| CN201320877890.5U CN203721727U (en) | 2013-12-26 | 2013-12-26 | Array substrate and display device |
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| CN201320877890.5U CN203721727U (en) | 2013-12-26 | 2013-12-26 | Array substrate and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730474A (en) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730474A (en) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN103730474B (en) * | 2013-12-26 | 2016-03-30 | 京东方科技集团股份有限公司 | A kind of array base palte and manufacture method, display unit |
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