CN203708219U - 3.4G digital phase-locking frequency multiplier for CPT clock - Google Patents
3.4G digital phase-locking frequency multiplier for CPT clock Download PDFInfo
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- CN203708219U CN203708219U CN201420074957.6U CN201420074957U CN203708219U CN 203708219 U CN203708219 U CN 203708219U CN 201420074957 U CN201420074957 U CN 201420074957U CN 203708219 U CN203708219 U CN 203708219U
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- APTZNLHMIGJTEW-UHFFFAOYSA-N pyraflufen-ethyl Chemical compound C1=C(Cl)C(OCC(=O)OCC)=CC(C=2C(=C(OC(F)F)N(C)N=2)Cl)=C1F APTZNLHMIGJTEW-UHFFFAOYSA-N 0.000 description 2
- 229910052701 rubidium Inorganic materials 0.000 description 2
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical group [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 2
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Abstract
The utility model discloses a 3.4G digital phase-locking frequency multiplier for a CPT clock, and mainly solves the problem in the prior art that a CPT clock with high performance is hard to realize with the existing digital phase-locking frequency multiplier. The 3.4G digital phase-locking frequency multiplier used for the CPT clock comprises a phase-locked loop chip, a loop filter, a voltage-controlled oscillator, a power divider, an attenuator, an quadrature mixer, a voltage-controlled temperature-compensation crystal oscillator, an FPGA, and two paths of D/A converters, wherein an input end of the loop filter is connected with the phase-locked loop chip, an input end of the voltage-controlled oscillator is connected with the loop filter, an input end of the power divider is connected with the voltage-controlled oscillator, input ends of the attenuator and the quadrature mixer are respectively connected with the power divider, output ends of the voltage-controlled temperature-compensation crystal oscillator and the FPGA are respectively connected with the phase-locked loop chip, input ends of the two paths of D/A converters are connected with the FPGA, output ends are connected with the quadrature mixer, an output end of the quadrature mixer is connected with the phase-locked loop chip, and the output end of the voltage-controlled temperature-compensation crystal oscillator is connected with the FPGA. Through the technical scheme, the 3.4G digital phase-locking frequency multiplier achieves the purposes of good technical index, high digitalization degree and convenient implementation, and has very high practical value and popularization value.
Description
Technical field
The utility model relates to a kind of frequency multiplier, specifically, relates to a kind of 3.4G digital phase-locked frequency multiplier device for CPT clock.
Background technology
CPT (Coherent Population Trapping) clock is the New type atom frequency marking of utilizing laser and atom generation coherence resonance mechanism, because this atomic clock no longer needs microwave cavity, thereby volume to reduce degree unrestricted in theory, represent the direction of miniaturization atomic clock development, also due to the advantage in volume, power consumption, CPT clock is the army's of being widely used in code receiver, hand-held navigator, submarine equipment etc., in occupation of the application of high-end crystal oscillator, market prospects are very wide, thereby receive much concern.According to the function of Component units, CPT clock can be divided into physical system and electronic system simply, and wherein, physical system plays the effect of atom frequency discrimination, is mainly made up of laser tube, 1/4 polarizer, absorption bubble, C field and photocell; Electronic system, except temperature control, also locks laser frequency by Current Negative Three-Point Capacitance, feeds back locking microwave frequency by voltage negative, is mainly made up of Microwave Frequency Multiplier Circuit, servo circuit and power circuit.
In above-mentioned, the effect of Microwave Frequency Multiplier Circuit is the 3.41734375GHz microwave signal that the output frequency of standard VCXO is obtained to the hyperfine thunderbolt frequency of CPT clock 1/2 rubidium atom by frequency synthesis.The traditional microlock frequency multiplication mode of CPT clock is to adopt fractional frequency division phase-locked, and frequency modulation(FM) recently realizes by cyclomorphosis fractional frequency division, and the advantage of this mode is that circuit volume is little, low in energy consumption.But this scheme is because the substrate of making an uproar mutually of fractional frequency division is poor, therefore phase noise is compared with the phase-locked obvious deterioration of integral frequency divisioil, thereby causes the short steady index of CPT clock poor.In addition, because the resolution of the phase-locked chip of general integrated fractional frequency division is only less than the precision of 25, therefore make CPT clock output frequency accuracy meticulous not, and then limited to a certain extent the application of CPT clock.
In sum, although traditional fractional frequency division phase lock circuitry adopts the advantage having in volume and power consumption, but because there is larger gap in the microwave multiple-frequency source that adopts this circuit to produce in phase noise and two indexs of frequency resolution, therefore CPT clock complete machine index is had to larger deterioration, thereby be difficult to realize high performance CPT clock.
Utility model content
The purpose of this utility model is to provide a kind of 3.4G digital phase-locked frequency multiplier device for CPT, there is larger gap in the microwave multiple-frequency source that mainly solves the digital phase-locked frequency multiplier circuit generation existing in prior art in phase noise and two indexs of frequency resolution, therefore CPT clock complete machine index is had to larger deterioration, thereby be difficult to realize the problem of high performance CPT clock.
To achieve these goals, the technical solution adopted in the utility model is as follows:
A kind of 3.4G digital phase-locked frequency multiplier device for CPT clock, comprise phase-locked loop chip, the loop filter that input is connected with phase-locked loop chip, the voltage controlled oscillator that input is connected with loop filter, the power splitter that input is connected with voltage controlled oscillator, the attenuator that input is connected with power splitter respectively and orthogonal mixer, the Voltage-Controlled Temperature Compensated Crystal Oscillator that output is connected with phase-locked loop chip respectively and FPGA, input is connected with FPGA, the two-way D/A converter that output is connected with orthogonal mixer, the output of described orthogonal mixer is connected with phase-locked loop chip, the output of described Voltage-Controlled Temperature Compensated Crystal Oscillator is connected with FPGA.
Further, described phase-locked loop chip comprises the phase discriminator that input is connected with Voltage-Controlled Temperature Compensated Crystal Oscillator, output is connected with loop filter, input respectively with the loop divider that orthogonal mixer is connected with FPGA, output is connected with phase discriminator, this phase discriminator and loop divider are integrated in phase-locked loop chip.
Specifically, described FPGA comprises selector switch, the timing sequence generating circuit that output is all connected with selector switch and two-way frequency register, the phase accumulator that input is connected with selector switch, the phase truncation processor that input is connected with phase accumulator, the input of described timing sequence generating circuit and phase accumulator is all connected with Voltage-Controlled Temperature Compensated Crystal Oscillator.
As preferably, described phase-locked loop chip is HMC704; Described voltage controlled oscillator is HMC389; Described orthogonal mixer is HMC495.
Compared with prior art, the utlity model has following beneficial effect:
(1) the utility model is by the ingenious setting to phaselocking frequency multiplier, use less device blocks reached phase noise low, spuious little, frequency resolution is high, be easy to the features such as debugging, can be used for making high-performance CPT clock, cost performance is higher, realistic demand, there is substantive distinguishing features and progress, be applicable to large-scale promotion application.
Accompanying drawing explanation
Fig. 1 is system block diagram of the present utility model.
Fig. 2 is the internal frame diagram of FPGA in the utility model.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail, and execution mode of the present utility model includes but not limited to the following example.
Embodiment
For there is larger gap in the microwave multiple-frequency source that solves the digital phase-locked frequency multiplier circuit generation existing in prior art in phase noise and two indexs of frequency resolution, therefore CPT clock complete machine index is had to larger deterioration, thereby be difficult to realize the problem of high performance CPT clock, as shown in Figure 1, the utility model discloses a kind of 3.4G digital phase-locked frequency multiplier device for CPT clock, comprise be connected the successively orthogonal mixer of (output that is the former is connected with the latter's input) of output, loop divider, phase discriminator, loop filter, voltage controlled oscillator, power splitter and attenuator, wherein, the output of power splitter is also connected with orthogonal mixer, the input of orthogonal mixer is also connected with two-way D/A converter, two-way D/A converter input be connected with FPGA, the output of this FPGA is connected with loop divider, input is connected with 20M Voltage-Controlled Temperature Compensated Crystal Oscillator, the output of this 20M Voltage-Controlled Temperature Compensated Crystal Oscillator is connected with phase discriminator.
Wherein, phase discriminator and loop divider are integrated in phase-locked loop chip, FPGA is by output successively two-way frequency register, selector switch, phase accumulator and the phase truncation processor of connected (output that is the former is connected with the latter's input), and the timing sequence generating circuit that output is connected with selector switch, input is connected with 20M Voltage-Controlled Temperature Compensated Crystal Oscillator, this phase accumulator is also connected with the output of 20M Voltage-Controlled Temperature Compensated Crystal Oscillator.
In the time of application, preferably voltage controlled oscillator output signal frequency range is 3.35 ~ 3.55GHz, and this microwave signal is divided into two-way through power splitter, and a road is directly exported to CPT clock laser physics system as CPT clock Laser Modulation with microwave source after attenuator decay, another road is delivered to orthogonal mixer HMC495, with mutually orthogonal by the two paths of signals of FPGA and two D/A converter generations, centre frequency is that the low-frequency modulation signal of 2.65625MHz carries out orthogonal mixing and obtains near radiofrequency signal 3.42GHz, this signal feeds back to phase-locked loop chip HMC704 again, and through the loop divider frequency division of this chip internal near 20MHz, then carry out phase demodulation with another road signal from 20M Voltage-Controlled Temperature Compensated Crystal Oscillator, the phase error signal of phase discriminator output is delivered to the tuning end of voltage controlled oscillator HMC389 after loop filter filtering, its output signal frequency is locked on the hyperfine thunderbolt frequency of CPT clock 1/2 rubidium atom 3.41734375GHz.
As shown in Figure 2, in FPGA inside, be similar to DDS principle and produce the digital signal that two-way frequency is fine-tuning, phase clock differs 90 degree, the orthogonal digital signal of this two-way converts to after analog signal because phase delay is basically identical by the identical D/A converter of circuit performance, therefore phase place still can keep orthogonal, thereby guarantee the spectral purity of orthogonal mixer output signal, guaranteed that 3.4G DPLL digital phase-locked loop can wrong not lock.Preferably adopt 32 phase place stepping words, show that thus minimum frequency fine setting absolute value is 20MHz/2
32, i.e. 0.004566Hz, the minimum frequency fine setting relative value of 3.41734375GHz microwave multiple-frequency output is 1.362E-12 relatively.
In this programme, that FPGA realizes by the frequency of changing periodically the orthogonal low frequency signal of output two-way to the modulation of 3.41734375GHz microwave source, so just save special FM circuit, in addition, because the hardware resource that is used for producing orthogonal low-frequency modulation signal can share a slice FPGA with other digital control circuit of whole CPT clock, therefore with respect to general DDS circuit, can save largely hardware spending.Moreover, the orthogonal low-frequency modulation signal of two-way adopts digital waveform producing method to form fabulous quadrature in phase degree in various frequencies, 90 of simulation degree merit parallel circuits have higher phase accuracy relatively, can guarantee mirror image sideband rejection in orthogonal mixer output radiofrequency signal.
In sum, 3.4G digital phase-locked frequency multiplier utensil have phase noise low, spuious little, frequency resolution is high, be easy to the features such as debugging, can be used for making high-performance CPT clock.
According to above-described embodiment, just can realize well the utility model.
Claims (4)
1. the 3.4G digital phase-locked frequency multiplier device for CPT clock, it is characterized in that, comprise phase-locked loop chip, the loop filter that input is connected with phase-locked loop chip, the voltage controlled oscillator that input is connected with loop filter, the power splitter that input is connected with voltage controlled oscillator, the attenuator that input is connected with power splitter respectively and orthogonal mixer, the Voltage-Controlled Temperature Compensated Crystal Oscillator that output is connected with phase-locked loop chip respectively and FPGA, input is connected with FPGA, the two-way D/A converter that output is connected with orthogonal mixer, the output of described orthogonal mixer is connected with phase-locked loop chip, the output of described Voltage-Controlled Temperature Compensated Crystal Oscillator is connected with FPGA.
2. a kind of 3.4G digital phase-locked frequency multiplier device for CPT clock according to claim 1, it is characterized in that, described phase-locked loop chip comprises the phase discriminator that input is connected with Voltage-Controlled Temperature Compensated Crystal Oscillator, output is connected with loop filter, input respectively with the loop divider that orthogonal mixer is connected with FPGA, output is connected with phase discriminator, this phase discriminator and loop divider are integrated in phase-locked loop chip.
3. a kind of 3.4G digital phase-locked frequency multiplier device for CPT clock according to claim 2, it is characterized in that, described FPGA comprises selector switch, the timing sequence generating circuit that output is all connected with selector switch and two-way frequency register, the phase accumulator that input is connected with selector switch, the phase truncation processor that input is connected with phase accumulator, the input of described timing sequence generating circuit and phase accumulator is all connected with Voltage-Controlled Temperature Compensated Crystal Oscillator.
4. a kind of 3.4G digital phase-locked frequency multiplier device for CPT clock according to claim 3, is characterized in that, described phase-locked loop chip is HMC704; Described voltage controlled oscillator is HMC389; Described orthogonal mixer is HMC495.
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| CN201420074957.6U CN203708219U (en) | 2014-02-21 | 2014-02-21 | 3.4G digital phase-locking frequency multiplier for CPT clock |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104410410A (en) * | 2014-11-27 | 2015-03-11 | 江汉大学 | Pulse signal source device |
| CN105158604A (en) * | 2015-08-25 | 2015-12-16 | 贵州航天计量测试技术研究所 | QFN packaged phase-locked chip test device |
| CN105827240A (en) * | 2016-03-14 | 2016-08-03 | 成都天奥电子股份有限公司 | Low-phase-noise 6.8GHz frequency source applied to rubidium atomic clock |
| CN105915215A (en) * | 2016-01-25 | 2016-08-31 | 江汉大学 | Frequency phase-locked loop PLL generation apparatus |
| CN109391266A (en) * | 2018-12-28 | 2019-02-26 | 陕西烽火电子股份有限公司 | A kind of hybrid frequency synthesizer based on orthogonal modulation |
| CN109560812A (en) * | 2019-01-17 | 2019-04-02 | 上海华测导航技术股份有限公司 | A kind of frequency transformation of external reference clock and phase noise optimize circuit |
-
2014
- 2014-02-21 CN CN201420074957.6U patent/CN203708219U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104410410A (en) * | 2014-11-27 | 2015-03-11 | 江汉大学 | Pulse signal source device |
| CN104410410B (en) * | 2014-11-27 | 2017-09-01 | 江汉大学 | A kind of pulse signal source device |
| CN105158604A (en) * | 2015-08-25 | 2015-12-16 | 贵州航天计量测试技术研究所 | QFN packaged phase-locked chip test device |
| CN105915215A (en) * | 2016-01-25 | 2016-08-31 | 江汉大学 | Frequency phase-locked loop PLL generation apparatus |
| CN105827240A (en) * | 2016-03-14 | 2016-08-03 | 成都天奥电子股份有限公司 | Low-phase-noise 6.8GHz frequency source applied to rubidium atomic clock |
| CN109391266A (en) * | 2018-12-28 | 2019-02-26 | 陕西烽火电子股份有限公司 | A kind of hybrid frequency synthesizer based on orthogonal modulation |
| CN109560812A (en) * | 2019-01-17 | 2019-04-02 | 上海华测导航技术股份有限公司 | A kind of frequency transformation of external reference clock and phase noise optimize circuit |
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