CN203658400U - A probe card general board for a digital-analog hybrid chip wafer level test - Google Patents
A probe card general board for a digital-analog hybrid chip wafer level test Download PDFInfo
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- CN203658400U CN203658400U CN201320860520.0U CN201320860520U CN203658400U CN 203658400 U CN203658400 U CN 203658400U CN 201320860520 U CN201320860520 U CN 201320860520U CN 203658400 U CN203658400 U CN 203658400U
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- 238000012360 testing method Methods 0.000 title claims abstract description 32
- 239000000523 sample Substances 0.000 title abstract description 12
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- 238000013461 design Methods 0.000 abstract description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000011161 development Methods 0.000 abstract description 2
- 239000011111 cardboard Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003278 mimic effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
The utility model relates to a probe card general board for a digital-analog hybrid chip wafer level test. The probe card general board for the digital-analog hybrid chip wafer level test is characterized in that as for the probe card general board, analog signals are increased; the number of board layers is increased; ground holes are increased; and protective wires are added to analog signal lines. A J750 test system designed by the patent includes an MSO module probe card general board, so that design manufacturing costs and exploitation time of digital-analog hybrid integrated circuit wafer test probe card boards can be reduced; technical risks of hardware development for new product tests are reduced; and the production efficiency is raised.
Description
Technical field
The utility model relates to a kind of public plate of exploration card of digital-to-analogue hybrid chip wafer-level test, belongs to integrated circuit testing art field.
Background technology
At present, in SIC (semiconductor integrated circuit) manufacturing process, after wafer production completes, before wafer cutting encapsulation, need to test wafer, in order that before wafer cutting encapsulation, integrated circuit lead is tested, the packaging cost of the tube core of avoiding losing efficacy.In On-Wafer Measurement, need to have used probe, the effect of probe is for the path that contacts of micron precision is provided between test machine and tested wafer, thereby tests.Probe mainly comprises probe and printed circuit board (PCB) (PCB), probe provides electrically interconnected between wafer and PCB, pcb board provides the electrical interconnects between probe and test machine, thereby has completed the path that contacts between test machine and tested wafer, as shown in Figure 1.Under normal circumstances, every kind of test machine can design a general public plate, to reduce the Design and manufacture cost of PCB.J750 is the digital test machine that a fundamental clock frequency is 50MHZ, and it can realize digital-to-analogue mixed signal test by installing a MSO template additional.Because hybrid digital-analog integrated circuit is high to the public plate requirement of exploration card, impedance Control is bad, the bad meeting of signal integrity causes simulated performance to decline.Nobody designs and produces always on the market, causes some design corporation's On-Wafer Measurement stage to abandon simulating partial test.Therefore, be badly in need of the public plate of a digital-to-analogue hybrid chip wafer sort exploration card for J750 test machine of design and solve the problems referred to above.
Utility model content
The utility model is for solving the problems of the technologies described above, and solution is as follows:
Flaggy number is increased to 14 layers, increases hole, ground, analog signal line is added to protective wire;
The public plate of described exploration card increases protective wire in analog signal line outside, and places ground connection via hole and receive ground level more as far as possible at shielding line;
The public plate of described exploration card is taked symmetrical structure, simulating signal and digital signal as far as possible away from, simulating signal ground floor and the 3rd layer, digital signal ten, 12,14 layers;
The public plate of described exploration card increases hole, ground in blank space as far as possible;
The public plate of described exploration card increases the distance between centers of tracks of signal wire, and digital signal is at least 3 times of live width, and simulating signal is 5～10 times of live width;
The public plate of described exploration card is for J750 test machine, and test machine includes MSO module.
accompanying drawing explanation
Below in conjunction with accompanying drawing and specific embodiments, the utility model is described further:
The location drawing of the public plate of Fig. 1 exploration card
The former schematic diagram of the public plate of Fig. 2 exploration card
Fig. 3 adds ground hole schematic diagram
The original technology of Fig. 4 is ten layers of structure
Fig. 5 utility model technology is 14 layers of structure
The protective wire of Fig. 6 artificial line
Embodiment
Be described in further detail in connection with accompanying drawing with regard to the utility model below: at this, schematic description and description of the present utility model is for explaining, but not as to restriction of the present utility model.
Redesign test philosophy figure, placement-and-routing again, increase simulation part on numerical portion basis, by increasing auxiliary protection circuit, thereby improve the design of signal integrity, main method comprises:
Simulating signal is increased to protective wire; as shown in Figure 6; simulating signal is different from digital signal; its amplitude is continuous, emphasis be performance, so simulating signal is disturbed than digital signal is easy; for this reason in the design concept figure stage; just increase protective wire design, the simulating signal of J750 test machine is increased to shielding line, thereby guaranteed that protected simulating signal is subject to very littlely even can not being interfered.
Layer structure reasonable in design, first, in order to guarantee the requirement of exploration card plate to PCB flatness, what take is symmetrical structure.Secondly, in order at utmost to reduce the interference of digital signal to simulating signal, simulating signal and digital signal do not design at same layer, and simulating signal is ground floor and the 3rd layer, digital signal ten, 12,14 layers; Final layer structure is as Fig. 5;
Increase hole, ground, thereby increased the connecting path between each ground level, play effect stably, as Fig. 3;
Increase the distance between centers of tracks of signal wire, digital signal is at least 3 times of live width as far as possible, and simulating signal is 5-10 times of live width;
Other design proposal adopts prior art, if digital circuit part is as far as possible away from mimic channel, the bypass of tested tube core or decoupling capacitor should be tried one's best and be placed near chip under test end, power supply Force and Sense line carry out short circuit near tested tube core power end as far as possible, power protection line (Guard line) is around Force and the Sense line of power supply, the DG8 line of each test module as far as possible near tested tube core hold and chip ground short circuit, use continual ground level, plane is connected to separately systematically link in analog, power and ground is as far as possible close to each other, digitally with in analog separate, signal wire is as far as possible short, and carry out isometric processing etc.
The technique effect that the utility model reaches is: the J750 test macro of this patent design can be saved design and manufacture cost and the development time of hybrid digital-analog integrated circuit wafer sort exploration card plate containing the public plate of MSO module exploration card; and reduced the technical risk that new product testing hardware is developed, improve production efficiency.
Claims (3)
1. the public plate of the exploration card of digital-to-analogue hybrid chip wafer-level test, is characterized in that,
Flaggy number is 14 layers,
Simulating signal and digital signal are symmetrical structure, described simulating signal and described digital signal as far as possible away from, described simulating signal ground floor and the 3rd layer, described digital signal ten, 12,14 layers,
By as far as possible many blank spaces that are arranged on of hole, ground,
Protective wire is arranged on described simulating signal outside, and being arranged on shielding line more than being tried one's best in hole, described ground, and receives ground level.
2. the public plate of the exploration card of a kind of digital-to-analogue hybrid chip wafer-level test according to claim 1, is characterized in that, the distance between centers of tracks of described signal wire is increased, and described digital signal is at least 3 times of live width, and described simulating signal is 5-10 times of live width.
3. the public plate of the exploration card of a kind of digital-to-analogue hybrid chip wafer-level test according to claim 1 and 2, is characterized in that, the public plate of described exploration card is for J750 test machine, and described test machine comprises MSO module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320860520.0U CN203658400U (en) | 2013-12-25 | 2013-12-25 | A probe card general board for a digital-analog hybrid chip wafer level test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320860520.0U CN203658400U (en) | 2013-12-25 | 2013-12-25 | A probe card general board for a digital-analog hybrid chip wafer level test |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203658400U true CN203658400U (en) | 2014-06-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320860520.0U Expired - Lifetime CN203658400U (en) | 2013-12-25 | 2013-12-25 | A probe card general board for a digital-analog hybrid chip wafer level test |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203658400U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108037331A (en) * | 2017-11-20 | 2018-05-15 | 中国电子科技集团公司第五十五研究所 | Suitable for the exploration card and designing and manufacturing method of Digital Analog Hybrid Circuits On-wafer measurement |
| CN113238145A (en) * | 2021-06-16 | 2021-08-10 | 无锡中微腾芯电子有限公司 | Digital-analog hybrid integrated circuit testing device and testing method |
-
2013
- 2013-12-25 CN CN201320860520.0U patent/CN203658400U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108037331A (en) * | 2017-11-20 | 2018-05-15 | 中国电子科技集团公司第五十五研究所 | Suitable for the exploration card and designing and manufacturing method of Digital Analog Hybrid Circuits On-wafer measurement |
| CN108037331B (en) * | 2017-11-20 | 2020-08-11 | 中国电子科技集团公司第五十五研究所 | Probe card suitable for digital-analog hybrid circuit on-chip test and design and manufacturing method |
| CN113238145A (en) * | 2021-06-16 | 2021-08-10 | 无锡中微腾芯电子有限公司 | Digital-analog hybrid integrated circuit testing device and testing method |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140618 |