CN203590182U - Analog switch circuit and electrical device with same - Google Patents
Analog switch circuit and electrical device with same Download PDFInfo
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- CN203590182U CN203590182U CN201320688910.4U CN201320688910U CN203590182U CN 203590182 U CN203590182 U CN 203590182U CN 201320688910 U CN201320688910 U CN 201320688910U CN 203590182 U CN203590182 U CN 203590182U
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Abstract
The utility model provides an analog switch circuit (1), comprising an NMOS transistor (M1) which is connected with a drain electrode of an input terminal (IN), a source electrode and a drain electrode which are respectively connected with grid electrodes of a power node (VDD) and the NMOS transistor (M1), and a PMOS transistor (SW1) which is connected with a grid electrode of a control terminal (CTRL), a PMOS transistor (QP) which is provide with a drain electrode connected with a datum node (VSS), and a source electrode and a grid electrode which are connected with the NMOS transistor (M1). The circuit also comprises a constant voltage circuit (21) which is connected with a grid electrode of the NMOS transistor (M1) and a source electrode of the PMOS transistor (QP), and the constant voltage circuit generates constant voltage (VC) which is lower than difference of withstand voltage between the grid electrode and the source electrode and interpolar voltage of the grid electrode and the source electrode of the NMOS transistor (M1).
Description
Technical field
The utility model relates to analog switching circuit and possesses its electric equipment.
Background technology
The various structures of analog switching circuit were proposed.For example JP 2007-295209 communique discloses possesses 2 MOS transistor being connected in series and for the grid of these MOS transistor being carried out to the analog switching circuit of the protective circuit of overvoltage protection.
In the disclosed analog switching circuit of JP 2007-295209 communique, between input terminal and lead-out terminal, be connected in series 1MOS transistor and 2MOS transistor.1MOS transistor and the transistorized grid of 2MOS are jointly connected to the 1st switch control terminal.1MOS transistor and the transistorized reverse grid of 2MOS (back gate) are connected to the 2nd switch control terminal.The 2nd switch control terminal is 1MOS transistor and the transistorized tie point of 2MOS.Impedance means (for example resistance) is connected between the 1st switch control terminal and the 2nd switch control terminal.The electric current of resistance is flow through in control circuit control, so that the voltage between terminals of resistance is no more than between 1MOS transistor and transistorized each gate-to-source of 2MOS is withstand voltage.
But, in the disclosed analog switching circuit of JP 2007-295209 communique, at 1MOS transistor and the upper contact resistance of the transistorized tie point of 2MOS (the 2nd switch control terminal).Therefore, the electric current flowing through in this resistance, by above-mentioned tie point, is mixed into and flows through in 1MOS transistor and the transistorized electric current of 2MOS.Thus, the electric current of inputting at input terminal is different with current value from the electric current of lead-out terminal output.Therefore, in the disclosed analog switching circuit of JP 2007-295209 communique, likely signal transmission correctly between input terminal and lead-out terminal.
Utility model content
The purpose of this utility model is, provide transistorized control electrode carried out to overvoltage protection, and between input terminal and lead-out terminal the analog switching circuit of signal transmission correctly.
According to a scheme of the present utility model, analog switching circuit comprises: input terminal; Lead-out terminal; Control terminal; The first transistor～three transistor; And constant voltage circuit.The first transistor of the first conductivity type has: the first electrode of electrical connection input terminal; The second electrode of electrical connection lead-out terminal; And control electrode.The transistor seconds of the second conductivity type has: the first electrode and the second electrode that are electrically connected respectively the control electrode of the first voltage node and the first transistor; And the control electrode of electrical connection control terminal.The 3rd transistor of the second conductivity type has: the first electrode; The second electrode of electrical connection second voltage node; And the control electrode of the second electrode of electrical connection the first transistor.Control electrode and the 3rd transistorized first electrode of constant voltage circuit electrical connection the first transistor, generate constant voltage.Between the first voltage node and second voltage node, there is potential difference.Constant voltage is determined littlely than the control electrode of the first transistor and the second interelectrode difference withstand voltage and the 3rd transistorized control electrode and the first interelectrode voltage.
Preferably, analog switching circuit also comprises the 4th transistor of the first conductivity type.The 4th transistor has: the first electrode and the second electrode that are electrically connected with the second electrode of lead-out terminal and the first transistor respectively; And the control electrode being electrically connected with the control electrode of the first transistor.
Preferably, analog switching circuit also comprises: the first electric charge is removed circuit, and the control electrode of electrical connection the first transistor, in the situation that transistor seconds ends, removes the electric charge of the control electrode of the first transistor; And second electric charge remove circuit, electrical connection the 3rd transistorized control electrode, in the situation that transistor seconds ends, remove the electric charge of the 3rd transistorized control electrode.
Preferably, analog switching circuit also comprises: the first electric charge is removed circuit, control electrode and the 4th transistorized control electrode of electrical connection the first transistor, in the situation that transistor seconds ends, remove the control electrode of the first transistor and the electric charge of the 4th transistorized control electrode; And second electric charge remove circuit, electrical connection the 3rd transistorized control electrode, in the situation that transistor seconds ends, remove the electric charge of the 3rd transistorized control electrode.
Preferably, the first electric charge is removed the 5th transistor that circuit comprises the first conductivity type.The second electric charge is removed the 6th transistor that circuit comprises the first conductivity type.Analog switching circuit also possesses the 5th transistor and the 6th transistor of first conductivity type of respectively doing for oneself.The 5th transistor has: be electrically connected respectively the second electrode of transistor seconds and the first electrode of second voltage node and the second electrode; And the control electrode of electrical connection control terminal.The 6th transistor has: the first electrode and the second electrode that are electrically connected respectively the 3rd transistorized control electrode and second voltage node; And the control electrode of electrical connection control terminal.
Preferably, constant voltage circuit comprises: N-shaped transistor; And there is the first resistance of being connected in series and the series circuit of the second resistance.N-shaped transistor has: be electrically connected respectively the control electrode of the first transistor and the first electrode and second electrode of the 3rd transistorized the first electrode; And control electrode.Between transistorized the first electrode of N-shaped and the second electrode, connect series circuit.The transistorized control electrode of N-shaped is electrically connected the tie point of the first resistance and the second resistance.
Preferably, constant voltage circuit comprises Zener diode.Zener diode has and is electrically connected respectively the control electrode of the first transistor and negative electrode and the anode of the 3rd transistorized the first electrode.
Preferably, constant voltage circuit also comprises Zener diode.Zener diode has and is electrically connected respectively the control electrode of the first transistor and negative electrode and the anode of the 3rd transistorized the first electrode.
According to another program of the present utility model, electric equipment possesses: analog switching circuit; To the transtation mission circuit of analog switching circuit transmitted signal; Acceptance is from the receiving circuit of the signal of analog switching circuit; And the control circuit of control simulation switching circuit.Analog switching circuit possesses: the input terminal of electrical connection transtation mission circuit; The lead-out terminal of electrical connection receiving circuit; The control terminal of electrical connection control circuit; The first transistor～three transistor; And constant voltage circuit.The first transistor of the first conductivity type has: the first electrode being electrically connected with input terminal; The second electrode; And control electrode.The transistor seconds of the second conductivity type has: the first electrode and the second electrode that are electrically connected respectively the control electrode of the first voltage node and the first transistor; And the control electrode of electrical connection control terminal.The 3rd transistor of the second conductivity type has: the first electrode; The second electrode of electrical connection second voltage node; And the control electrode of the second electrode of electrical connection the first transistor.Control electrode and the 3rd transistorized first electrode of constant voltage circuit electrical connection the first transistor, generate constant voltage.Between the first voltage node and second voltage node, there is potential difference.Constant voltage is determined littlely than the control electrode of the first transistor and the second interelectrode difference withstand voltage and the 3rd transistorized control electrode and the first interelectrode voltage.
According to the utility model, can carry out overvoltage protection to transistorized control electrode, and between input terminal and lead-out terminal signal transmission correctly.
Above and other object of the present utility model, feature, scheme and advantage, from detailed explanation below associated understand relevant of the present utility model of the accompanying drawing adding, understand fairly obvious.
Accompanying drawing explanation
Fig. 1 is the block diagram that represents the schematic configuration of the electric equipment of the analog switching circuit that possesses execution mode of the present utility model.
Fig. 2 is the circuit diagram that represents the structure of the analog switching circuit of execution mode 1 of the present utility model.
Fig. 3 is timing (timing) figure for the action of the analog switching circuit shown in key diagram 2.
Fig. 4 is the circuit diagram that represents to comprise another structure of the constant voltage circuit of the analog switching circuit shown in Fig. 2.
Fig. 5 is the circuit diagram of the 3rd transistorized another structure of comprising of the analog switching circuit shown in presentation graphs 2.
Fig. 6 is the circuit diagram that represents the structure of the analog switching circuit of execution mode 2 of the present utility model.
Fig. 7 is the timing diagram for the action of the analog switching circuit shown in key diagram 6.
Fig. 8 is the circuit diagram that represents the structure of the analog switching circuit of execution mode 3 of the present utility model.
Fig. 9 is the timing diagram for the action of the analog switching circuit shown in key diagram 8.
Figure 10 is the circuit diagram that represents the structure of the analog switching circuit of execution mode 4 of the present utility model.
Embodiment
Below, with reference to accompanying drawing, explain execution mode of the present utility model.Have again, to identical in figure or considerable part additional same numeral, not its explanation repeatedly.
[execution mode 1]
Fig. 1 is the block diagram that represents the schematic configuration of the electric equipment of the analog switching circuit that possesses execution mode of the present utility model.With reference to Fig. 1, electric equipment 100 comprises: motor M; Inverter circuit 101; Comparator circuit 102; Logical circuit 103; And analog switching circuit 1～3.Inverter circuit 101 comprises switch Q1～Q6 and resistance R.Have, inverter circuit 101, comparator circuit 102 and logical circuit 103 are respectively examples of ' transtation mission circuit ' of the present utility model, ' receiving circuit ' and ' control circuit ' again.The structure of ' electric equipment ' of the present utility model is not limited to the structure shown in Fig. 1.
In inverter circuit 101, be provided with and comprise the switch Q1 that is connected in series and the series circuit of switch Q2.This series circuit is connected between the voltage node (following, to be called datum node) that the voltage node of supply voltage VDD (following, to be called power supply node) is provided and reference potential VSS is provided.Supply voltage VDD is for example 24V.Reference potential VSS is for example earthing potential.But the magnitude of voltage of these voltage nodes is not defined as above-mentioned value.
Similarly, comprise the series circuit of the switch Q3 that is connected in series and switch Q4 and comprise the switch Q5 that is connected in series and the series circuit of switch Q6 is connected between power supply node and datum node.Contact resistance R between the tie point of switch Q2, Q4, Q6 and datum node.Have again, resistance R also can be set.
Motor M is for example 3 phase brushless electric machines.U phase line, V phase line and the W phase line of motor M is electrically connected respectively the mid point between mid point and switch Q5 and the switch Q6 between mid point, switch Q3 and the switch Q4 between switch Q1 and switch Q2.In addition,, in the U of motor M phase line, V phase line and W phase line, be electrically connected respectively the input terminal IN (with reference to Fig. 2) of analog switching circuit 1～3.The lead-out terminal OUT (with reference to Fig. 2) of analog switching circuit 1～3 is electrically connected the in-phase input terminal of comparator circuit 102.The reversed input terminal of comparator circuit 102 is accepted the midpoint potential COM of motor M.Comparator circuit 102 compares the voltage of in-phase input terminal and midpoint potential COM, output control signal.This control signal is imported into logical circuit 103.Have again, also can exchange the input to the reversed input terminal in comparator circuit 102 and the input to in-phase input terminal.In addition, also can between the U of motor M phase line, V phase line and W phase line and the input terminal IN of analog switching circuit 1～3, distinguish contact resistance.
The control signal of logical circuit 103 based on from comparator circuit 102, will output to inverter circuit 101 for the control signal of control switch Q1～Q6 independently of one another.Inverter circuit 101 generates alternating electromotive force by the break-make of switch Q1～Q6, and the alternating electromotive force of generation is outputed to motor M.In addition, logical circuit 103 outputs to control signal G1～G3 respectively the control terminal CTRL (with reference to Fig. 2) of analog switching circuit 1～3.Analog switching circuit 1～3 is based on control signal G1～G3, respectively the connection between U phase line, V phase line and W phase line and the comparator circuit 102 of conversion motor M.Below, analog switching circuit 1 in analog switching circuit 1～3 is described typically.The structure of analog switching circuit 2,3 is same with the structure of analog switching circuit 1.
Fig. 2 is the circuit diagram that represents the structure of the analog switching circuit 1 of execution mode 1 of the present utility model.See figures.1.and.2, analog switching circuit 1 comprises: input terminal IN; Lead-out terminal OUT; Control terminal CTRL; N (N-type) MOS transistor (the first transistor) M1; P (P type) MOS transistor (transistor seconds) SW1; PMOS transistor (the 3rd transistor) QP; Nmos pass transistor (the 4th transistor) M2; Constant voltage circuit 21; And electric charge is removed circuit 31,32.Diode D1, D2 are respectively the parasitic diodes of nmos pass transistor M1, M2.
Mid point (with reference to Fig. 1) between input terminal IN electrical connection switch Q1 and switch Q2.The in-phase input terminal of lead-out terminal OUT electrical connection comparator circuit 102 (with reference to Fig. 1).Control terminal CTRL electrical connection logical circuit 103 (with reference to Fig. 1), accepts control signal G1.
The source electrode electric connection of power supply node of PMOS transistor SW1.The grid of PMOS transistor SW1 is accepted control signal G1 from control terminal CTRL.
The drain electrode of each grid electrical connection PMOS transistor SW1 of nmos pass transistor M1, M2.Reverse grid (not shown) at nmos pass transistor M1, M2 is upper, is electrically connected respectively the source electrode of nmos pass transistor M1, M2.The drain electrode electrical connection input terminal IN of nmos pass transistor M1.The drain electrode electrical connection lead-out terminal OUT of nmos pass transistor M2.The source electrode of nmos pass transistor M1, M2 is electrically connected to each other.Thus, the anode of diode D1, D2 is electrically connected to each other, and becomes reverse just towards each other.Therefore, can prevent in the situation that nmos pass transistor M1, M2 end separately current flowing between input terminal IN and lead-out terminal OUT.
The drain electrode electrical connection datum node of PMOS transistor QP.The source electrode of the grid electrical connection nmos pass transistor M1 of PMOS transistor QP.On the grid of nmos pass transistor M1, M2 and the grid of PMOS transistor QP, connect respectively electric charge and remove circuit 31,32.In the situation that PMOS transistor SW1 ends, each circuit that electric charge is removed circuit 31,32 is removed the electric charge of the transistorized grid connecting in each electric charge is removed circuit.Thus, can make nmos pass transistor M1, M2 and PMOS transistor QP cut-off.
The grid of one end electrical connection nmos pass transistor M1 of constant voltage circuit 21.The source electrode of the other end electrical connection PMOS transistor QP of constant voltage circuit 21.Constant voltage circuit 21 generates constant voltage VC between these two ends.More particularly, constant voltage circuit 21 comprises: nmos pass transistor Tr; And resistance R a, Rb.Drain electrode-voltage between source electrodes of nmos pass transistor Tr, according to voltage between gate-to-source, is determined with the ratio of resistance R a and resistance R b.By the resistance value of adjusting resistance Ra, Rb, between drain electrode-voltage between source electrodes and gate-to-source, voltage is defined in suitable scope.
Between the grid of nmos pass transistor M1, M2 and source electrode, be provided with constant voltage circuit 21.Therefore, between each gate-to-source of nmos pass transistor M1, M2, voltage is clamped to constant voltage VC by constant voltage circuit 21.The constant voltage VC that constant voltage circuit 21 generates is determined littlely than the difference of voltage VGS between the gate-to-source of the withstand voltage and PMOS transistor QP between each gate-to-source of nmos pass transistor M1, M2.Therefore, in supply voltage VDD when variation in the situation that of PMOS transistor SW1 conducting,, even if or the in the situation that of nmos pass transistor M1 conducting during the voltage VIN variation of input terminal IN, each grid that also can pair nmos transistor M1, M2 carries out overvoltage protection.
Have again, in execution mode 1, power supply node correspondence ' the first voltage node ' of the present utility model, datum node correspondence ' second voltage node '.In addition the transistor of nmos pass transistor and PMOS transistor respectively corresponding ' the first conductivity type ' of the present utility model and ' the second conductivity type '.In nmos pass transistor, drain electrode and source electrode respectively corresponding ' the first electrode ' of the present utility model and ' the second electrode '.On the other hand, in PMOS transistor, source electrode and drain electrode respectively corresponding ' the first electrode ' and ' the second electrode '.Regardless of transistorized conductivity type, grid is corresponding ' control electrode ' of the present utility model all.
Fig. 3 is the timing diagram for the action of the analog switching circuit 1 shown in key diagram 2.With reference to Fig. 2 and Fig. 3, in control signal G1, corresponding to the rotation of the rotor (not shown) of motor M (with reference to Fig. 1), repeatedly during the H in 1/3 cycle (" height ") level and during L (" the low ") level in 2/3 cycle.With 0, represent moment as the zero hour through official hour after control signal G1 is imported into control terminal CTRL.
Below, jointly, between gate-to-source, voltage refers to the current potential using the current potential of source electrode as the grid of benchmark for nmos pass transistor and PMOS transistor.Therefore, between the gate-to-source in nmos pass transistor, voltage exceedes threshold voltage of the grid in the situation that of H level.On the other hand, between the gate-to-source in PMOS transistor, voltage exceedes threshold voltage of the grid in the situation that of L level.
Carving from the outset the moment of having passed through t1, the current potential of control signal G1 is H level from L level conversion.Therefore, PMOS transistor SW1 is cut off.Thus, on each grid of nmos pass transistor M1, M2, be not applied to supply voltage VDD.Therefore, between the gate-to-source of nmos pass transistor M1, M2, voltage is L level from H level conversion.Therefore, nmos pass transistor M1, M2 are cut off.That is, analog switching circuit 1 is converted to nonconducting state from conducting state.
Now, on the grid of PMOS transistor QP, be not applied to the voltage VIN of input terminal IN.Therefore, between the gate-to-source of PMOS transistor QP voltage VGS lower than threshold voltage of the grid (H level).Therefore, PMOS transistor QP is cut off.
Carving from the outset the moment of having passed through t2, the level of control signal G1 is L level from H level conversion.Therefore, PMOS transistor SW1 is switched on.Thus, on each grid of nmos pass transistor M1, M2, be applied in supply voltage VDD.Therefore, between the gate-to-source of nmos pass transistor M1, M2, voltage is H level from L level conversion.Therefore, nmos pass transistor M1, M2 are switched on.That is, analog switching circuit 1 is converted to conducting state from nonconducting state.
Now, the voltage VIN of the voltage of the grid of PMOS transistor QP and input terminal IN is roughly equal.Therefore, between the gate-to-source of PMOS transistor QP, voltage VGS is (VDD-VC-VIN).This magnitude of voltage exceedes the threshold voltage of the grid (L level) of PMOS transistor QP.Therefore, PMOS transistor QP is switched on.By PMOS transistor QP conducting, the electric current flowing into constant voltage circuit 21 from power supply node flows to datum node.Thus, can prevent that this electric current from sneaking in the electric current flowing through between nmos pass transistor M1, M2.
Carve the moment of having passed through t3 from the outset, the level of control signal G1 is H level from L level conversion.The action of analog switching circuit 1 is now same with carving the action of having passed through in moment of t1 from the outset, so not detailed explanation repeatedly.
As more than, according to present embodiment, between the grid of nmos pass transistor M1, M2 and source electrode, be provided with constant voltage circuit 21.Therefore grid that, can pair nmos transistor M1, M2 carries out overvoltage protection.
As the disclosed structure of JP 2007-295209 communique, also consider to use resistance to replace PMOS transistor QP.Resistance is parallel-connected to constant voltage circuit 21 between the grid of nmos pass transistor M1 and source electrode.Even this structure, grid that also can pair nmos transistor M1, M2 carries out overvoltage protection.But the electric current that flows through resistance is blended in the electric current that flows through nmos pass transistor M1, M2.On the other hand, according to present embodiment, the electric current flowing through between source electrode-drain electrode of PMOS transistor QP is not blended in the electric current that flows through nmos pass transistor M1, M2.Therefore, according to present embodiment, can be between input terminal IN and lead-out terminal OUT signal transmission correctly.
Have again, illustrated that analog switching circuit 1 possesses the situation of two nmos pass transistors.But, even if the structure of nmos pass transistor M1 is only set in analog switching circuit 1, also can be suitable for the utility model.In this case, the source electrode of nmos pass transistor M1 electrical connection lead-out terminal OUT.
[variation]
The structure of the each several part of analog switching circuit 1 is not limited to the structure shown in Fig. 2.Even analog switching circuit has the structure different from Fig. 2, also can obtain the effect same with the structure shown in Fig. 2.
Fig. 4 is the circuit diagram of another structure of the constant voltage circuit that comprises of the analog switching circuit 1 shown in presentation graphs 2.With reference to Fig. 4 (A), analog switching circuit 1 possesses constant voltage circuit 22 and replaces constant voltage circuit 21.Constant voltage circuit 22 comprises Zener diode ZD.Zener diode ZD has negative electrode and the anode of the source electrode of the grid (with reference to Fig. 2) that is electrically connected respectively nmos pass transistor M1 and PMOS transistor QP.Withstand voltage little than between each gate-to-source of nmos pass transistor M1, M2 of voltage VGS sum between the gate-to-source of the puncture voltage VBR of Zener diode ZD and PMOS transistor QP.By this structure, each grid that also can pair nmos transistor M1, M2 carries out overvoltage protection.
With reference to Fig. 4 (B), analog switching circuit 1 also can possess constant voltage circuit 23 and replace constant voltage circuit 21.In constant voltage circuit 23, the increase sharply of defence supply voltage VDD, connects Zener diode ZD in constant voltage circuit 21.
The constant voltage VC that constant voltage circuit 21 generates is less than the puncture voltage VBR of Zener diode ZD.Therefore, between the gate-to-source of nmos pass transistor M1, M2, each voltage of voltage, is clamped to constant voltage VC by constant voltage circuit 21 conventionally.On the other hand, withstand voltage low than between drain electrode-source electrode of nmos pass transistor Tr of puncture voltage VBR.In the situation that supply voltage VDD increases sharp, Zener diode ZD is breakdown.Thus, can protect nmos pass transistor Tr.
Fig. 5 is the circuit diagram of another structure of the PMOS transistor QP that comprises at the analog switching circuit 1 shown in Fig. 2.With reference to Fig. 5 (A), analog switching circuit 1 possesses PNP transistor Qa and replaces PMOS transistor QP.With reference to Fig. 5 (B), PNP transistor Qa, the Qb that also can use Darlington to connect (Darlington connection) replaces PMOS transistor QP.Using in the transistorized situation of PNP, also same with PMOS transistor, can prevent from sneaking into the electric current from beyond input terminal IN in the electric current that flows through nmos pass transistor M1, M2.
[execution mode 2]
According to execution mode 2, compared with execution mode 1, realize the analog switching circuit that is converted at high speed nonconducting state from conducting state.
Fig. 6 is the circuit diagram that represents the structure of the analog switching circuit of execution mode 2 of the present utility model.With reference to Fig. 6, electric charge is removed circuit 31 and is comprised nmos pass transistor (the 5th transistor) SW2 and resistance R 2.Electric charge is removed circuit 32 and is comprised nmos pass transistor (the 6th transistor) SW3 and resistance R 3.In this respect, analog switching circuit 12 is different from the analog switching circuit 1 (with reference to Fig. 2) of execution mode 1.Have, resistance R 2, R3 are current limliting resistance again.Therefore, resistance R 2, R3 also can be set.
The drain electrode of nmos pass transistor SW2 is electrically connected with the drain electrode of PMOS transistor SW1.The source electrode separately of nmos pass transistor SW2, SW3, respectively by resistance R 2, R3, is electrically connected datum node.The grid of the drain electrode electrical connection PMOS transistor QP of nmos pass transistor SW3.Each grid of nmos pass transistor SW2, SW3 is accepted control signal G1 from control terminal CTRL.The structure in addition of analog switching circuit 12, is identical with the structure of analog switching circuit 1, so not detailed explanation repeatedly.
Fig. 7 is the timing diagram for the action of the analog switching circuit 12 shown in key diagram 6.Fig. 7 and Fig. 3 contrast.
With reference to Fig. 6 and Fig. 7, to carve from the outset the moment of having passed through t1, the level of control signal G1 is H level from L level conversion.Therefore, PMOS transistor SW1 is cut off.On the other hand, nmos pass transistor SW2, SW3 are switched on.Therefore, the grid of nmos pass transistor M1, M2 pulled down to reference potential VSS.Thus, compared with execution mode 1, the conversion speed from conducting to cut-off of nmos pass transistor M1, M2 becomes large.
Now, the source electrode of PMOS transistor QP and grid all pulled down to reference potential VSS.Therefore, between the gate-to-source of PMOS transistor QP voltage VGS lower than threshold voltage of the grid.Therefore, PMOS transistor QP is cut off.
Carving from the outset the moment of having passed through t2, the level of control signal G1 is L level from H level conversion.Therefore, PMOS transistor SW1 is switched on.On the other hand, nmos pass transistor SW2, SW3 are cut off.Thus, the grid of nmos pass transistor M1, M2 by move supply voltage VDD to.Therefore, between the gate-to-source of nmos pass transistor M1, M2, voltage is H level from L level conversion.Therefore, nmos pass transistor M1, M2 are switched on.
Now, the voltage of the grid of PMOS transistor QP and voltage VIN are roughly equal.Therefore, between the gate-to-source of PMOS transistor QP, voltage VGS is (VDD-VC-VIN).This magnitude of voltage exceedes the threshold voltage of the grid of PMOS transistor QP.Therefore, PMOS transistor QP is switched on.
Carving from the outset the moment of having passed through t3, the level of control signal G1 is H level from L level conversion.The action of analog switching circuit 12 now, is same with the action of carving from the outset in the moment of having passed through t1, so not detailed explanation repeatedly.
According to execution mode 2, in the situation that analog switching circuit 12 is converted to nonconducting state from conducting state, nmos pass transistor SW2, SW3 conducting separately.Therefore, each grid of nmos pass transistor M1, M2 pulled down to reference potential VSS.Thus, from the conducting of nmos pass transistor M1, M2, to the conversion speed of cut-off, increase.In addition, the conducting resistance of nmos pass transistor SW2, SW3 is less than the transistorized conducting resistance of PMOS of formed objects.Therefore the PMOS transistor that, nmos pass transistor SW2, SW3 compare formed objects can be removed electric charge at high speed.Therefore, remove and in circuit, use compared with the transistorized situation of PMOS with electric charge, nmos pass transistor M1, M2 can be ended at high speed.Therefore,, according to execution mode 2, compared with execution mode 1, analog switching circuit can be converted to nonconducting state at high speed from conducting state.
[execution mode 3]
In execution mode 1,2, in the conducting state of analog switching circuit and the conversion of nonconducting state, use nmos pass transistor.But, also can use PMOS transistor to replace nmos pass transistor.
Fig. 8 is the circuit diagram that represents the structure of the analog switching circuit of execution mode 3 of the present utility model.With reference to Fig. 8, analog switching circuit 13 possesses PMOS transistor M3, M4 and replaces nmos pass transistor M1, M2.Diode D3, D4 are respectively the parasitic diodes of PMOS transistor M3, M4.In addition, analog switching circuit 13 possesses nmos pass transistor SW4, QN replacement PMOS transistor SW1, QP.In execution mode 3, PMOS transistor M3, M4 respectively corresponding ' the first transistor ' of the present utility model, ' the 4th transistor '.Nmos pass transistor SW4, QN respectively corresponding ' transistor seconds ', ' the 3rd transistor '.
In addition, in present embodiment 3, contrary with execution mode 1, datum node correspondence ' the first voltage node ' of the present utility model, power supply node correspondence ' second voltage node '.In addition the transistor of PMOS transistor and nmos pass transistor respectively corresponding ' the first conductivity type ' of the present utility model and ' the second conductivity type '.In this respect, analog switching circuit 13 is different from the analog switching circuit 1 (with reference to Fig. 2) of execution mode 1.
The drain electrode of each grid electrical connection nmos pass transistor SW4 of PMOS transistor M3, M4.The source electrode electrical connection datum node of nmos pass transistor SW4.The source electrode electrical connection input terminal IN of PMOS transistor M3.The source electrode electrical connection lead-out terminal OUT of PMOS transistor M4.The drain electrode of PMOS transistor M3, M4 is electrically connected to each other.Thus, the anode of diode D3, D4 is electrically connected to each other, and becomes reverse just towards each other.Therefore, can prevent when PMOS transistor M3, M4 end current flowing between input terminal IN and lead-out terminal OUT.
The drain electrode electric connection of power supply node of nmos pass transistor QN.One end of the source electrode electrical connection constant voltage circuit 21 of nmos pass transistor QN.The drain electrode of the grid electrical connection PMOS transistor M3 of nmos pass transistor QN.The other end electrical connection PMOS transistor M3 of constant voltage circuit 21, the grid of M4.The structure in addition of analog switching circuit 13, is identical with the structure (with reference to Fig. 2) of the analog switching circuit 1 of execution mode 1, so not detailed explanation repeatedly.
Fig. 9 is the timing diagram for the action of the analog switching circuit 13 shown in key diagram 8.Fig. 9 and Fig. 3 contrast.
With reference to Fig. 8 and Fig. 9, to carve from the outset the moment of having passed through t1, the level of control signal G1 is H level from L level conversion.Therefore, nmos pass transistor SW4 is switched on.Thus, the voltage of each grid of PMOS transistor M3, M4 and reference potential VSS are roughly equal.Therefore, between the gate-to-source of PMOS transistor M3, M4, voltage is L level from H level conversion.Therefore, PMOS transistor M3, M4 are switched on.That is, analog switching circuit 13 is converted to conducting state from nonconducting state.
Now, the voltage VIN of the voltage of the grid of nmos pass transistor QN and input terminal IN is roughly equal.Therefore, between the gate-to-source of nmos pass transistor QN, voltage VGS is (VIN-VC-VSS).This magnitude of voltage exceedes the threshold voltage of the grid (H level) of nmos pass transistor QN.Therefore, nmos pass transistor QN is switched on.
Carving from the outset the moment of having passed through t2, the level of control signal G1 is L level from H level conversion.Therefore, nmos pass transistor SW4 is cut off.Thus, between each gate-to-source of PMOS transistor M3, M4, voltage is H level from L level conversion.Therefore, PMOS transistor M3, M4 are cut off.That is, analog switching circuit 13 is converted to nonconducting state from conducting state.
Now, on the grid of nmos pass transistor QN, be not applied to voltage VIN.Therefore, between the gate-to-source of nmos pass transistor QN voltage VGS lower than threshold voltage of the grid (L level).Therefore, nmos pass transistor QN is cut off.
Carving from the outset the moment of having passed through t3, the current potential of control signal G1 is H level from L level conversion.The action of analog switching circuit 13 now, is same with the action of carving from the outset in the moment of having passed through t1, so not detailed explanation repeatedly.
According to execution mode 3, having used in the transistorized analog switching circuit of PMOS, also can carry out overvoltage protection to the transistorized grid of those PMOS.In addition, can prevent from sneaking into the electric current from beyond input terminal IN in the electric current that flows through PMOS transistor M3, M4.
[execution mode 4]
Having used in the transistorized analog switching circuit of PMOS, with execution mode 2 similarly, can be converted at high speed nonconducting state from conducting state.
Figure 10 is the circuit diagram that represents the structure of the analog switching circuit of execution mode 4 of the present utility model.With reference to Figure 10, electric charge is removed circuit 31 and is comprised PMOS transistor SW5 and resistance R 5.Electric charge is removed circuit 32 and is comprised PMOS transistor SW6 and resistance R 6.In execution mode 4, PMOS transistor SW5, SW6 respectively corresponding ' the 5th transistor ' of the present utility model, ' the 6th transistor '.In this respect, analog switching circuit 14 is different from the analog switching circuit 13 (with reference to Fig. 8) of execution mode 3.
The drain electrode of PMOS transistor SW5 is electrically connected with the drain electrode of nmos pass transistor SW4.The source electrode separately of PMOS transistor SW5, SW6 is respectively by resistance R 5, R6, electric connection of power supply node.The grid of the drain electrode electrical connection nmos pass transistor QN of PMOS transistor SW6.Each grid of PMOS transistor SW5, SW6 is accepted control signal G1 from control terminal CTRL.The structure in addition of analog switching circuit 14 is identical with the structure (with reference to Fig. 8) of the analog switching circuit 13 of execution mode 3, so not detailed explanation repeatedly.
In addition, with the action of analog switching circuit 13 analog switching circuit 14 relatively, identical with the action of analog switching circuit 1 (with reference to Fig. 2) analog switching circuit 12 relatively (Fig. 7 with reference to), so not detailed explanation repeatedly.
Have again, in execution mode 2～4, also can carry out the distortion same with variation (with reference to Fig. 4 and Fig. 5) about execution mode 1.In this case, to the bipolar transistor in Fig. 5, can suitably adopt NPN transistor or PNP transistor.
Execution mode of the present utility model has been described, but should have thought that this disclosed execution mode is all illustration rather than restrictive in all respects.Scope of the present utility model represents by the scope of claim, is intended to comprise all changes in the meaning equal with the scope of claim and scope.
Claims (9)
1. an analog switching circuit, is characterized in that, comprising:
Input terminal;
Lead-out terminal;
Control terminal;
The first transistor of the first conductivity type, have the described input terminal of electrical connection the first electrode, be electrically connected the second electrode and the control electrode of described lead-out terminal;
The transistor seconds of the second conductivity type, has the 1st electrode and second electrode of the control electrode that is electrically connected respectively the first voltage node and described the first transistor and is electrically connected the control electrode of described control terminal;
The 3rd transistor of described the second conductivity type, has: the first electrode; Electrical connection has the second electrode of the second voltage node of potential difference with respect to described the first voltage node; And be electrically connected the control electrode of the second electrode of described the first transistor; And
Constant voltage circuit, be electrically connected control electrode and described the 3rd transistorized first electrode of described the first transistor, generate than the little constant voltage of difference of the control electrode of described the first transistor and the second interelectrode withstand voltage and described the 3rd transistorized control electrode and the first interelectrode voltage.
2. analog switching circuit as claimed in claim 1, is characterized in that, also comprises:
The 4th transistor of described the first conductivity type,
Described the 4th transistor has: the 1st electrode and the second electrode that are electrically connected with the second electrode of described lead-out terminal and described the first transistor respectively; And the control electrode being electrically connected with the control electrode of described the first transistor.
3. analog switching circuit as claimed in claim 1, is characterized in that, also comprises:
The first electric charge is removed circuit, is electrically connected the control electrode of described the first transistor, the in the situation that of described transistor seconds cut-off, removes the electric charge of the control electrode of described the first transistor; And
The second electric charge is removed circuit, is electrically connected described the 3rd transistorized control electrode, the in the situation that of described transistor seconds cut-off, removes the electric charge of described the 3rd transistorized control electrode.
4. analog switching circuit as claimed in claim 2, is characterized in that, also comprises:
The first electric charge is removed circuit, be electrically connected control electrode and described the 4th transistorized control electrode of described the first transistor, the in the situation that of described transistor seconds cut-off, remove the control electrode of described the first transistor and the electric charge of described the 4th transistorized control electrode; And
The second electric charge is removed circuit, is electrically connected described the 3rd transistorized control electrode, the in the situation that of described transistor seconds cut-off, removes the electric charge of described the 3rd transistorized control electrode.
5. analog switching circuit as claimed in claim 4, is characterized in that,
Described the first electric charge is removed the 5th transistor that circuit comprises described the first conductivity type,
Described the second electric charge is removed the 6th transistor that circuit comprises described the first conductivity type,
Described the 5th transistor has: be electrically connected respectively the second electrode of described transistor seconds and the first electrode of described second voltage node and the second electrode; And be electrically connected the control electrode of described control terminal,
Described the 6th transistor has: the first electrode and the second electrode that are electrically connected respectively described the 3rd transistorized control electrode and described second voltage node; And be electrically connected the control electrode of described control terminal.
6. as the analog switching circuit as described in any one in claim 1 to 5, it is characterized in that,
Described constant voltage circuit comprises: N-shaped transistor; And there is the first resistance of being connected in series and the series circuit of the second resistance,
Described N-shaped transistor has: be electrically connected respectively the control electrode of described the first transistor and the first electrode and second electrode of described the 3rd transistorized the first electrode; And control electrode,
Between transistorized the first electrode of described N-shaped and the second electrode, connect described series circuit,
The transistorized control electrode of described N-shaped is electrically connected the tie point of described the 1st resistance and the second resistance.
7. as the analog switching circuit as described in any one in claim 1 to 5, it is characterized in that,
Described constant voltage circuit comprises Zener diode,
Described Zener diode has and is electrically connected respectively the control electrode of described the first transistor and negative electrode and the anode of described the 3rd transistorized the first electrode.
8. analog switching circuit as claimed in claim 6, is characterized in that,
Described constant voltage circuit also comprises Zener diode,
Described Zener diode has and is electrically connected respectively the control electrode of described the first transistor and negative electrode and the anode of described the 3rd transistorized the first electrode.
9. an electric equipment, is characterized in that, comprising:
Analog switching circuit;
Transtation mission circuit, to described analog switching circuit transmitted signal;
Receiving circuit, accepts the signal from described analog switching circuit; And
Control circuit, controls described analog switching circuit,
Described analog switching circuit comprises:
Input terminal, is electrically connected described transtation mission circuit;
Lead-out terminal, is electrically connected described receiving circuit;
Control terminal, is electrically connected described control circuit;
The first transistor of the first conductivity type, has: be electrically connected described input terminal the first electrode, be electrically connected the second electrode of described lead-out terminal; And control electrode;
The transistor seconds of the second conductivity type, has: the first electrode and the second electrode that are electrically connected respectively the control electrode of the first voltage node and described the first transistor; And be electrically connected the control electrode of described control terminal;
The 3rd transistor of described the second conductivity type, has: the first electrode, electrical connection have the second electrode of the second voltage node of potential difference with respect to described the first voltage node; And be electrically connected the control electrode of the second electrode of described the first transistor; And
Constant voltage circuit, be electrically connected control electrode and described the 3rd transistorized first electrode of described the first transistor, generate than the little constant voltage of difference of the control electrode of described the first transistor and the second interelectrode withstand voltage and described the 3rd transistorized control electrode and the first interelectrode voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012242500A JP6023551B2 (en) | 2012-11-02 | 2012-11-02 | Analog switch circuit and electric device including the same |
| JP2012-242500 | 2012-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203590182U true CN203590182U (en) | 2014-05-07 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320688910.4U Expired - Fee Related CN203590182U (en) | 2012-11-02 | 2013-11-04 | Analog switch circuit and electrical device with same |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP6023551B2 (en) |
| CN (1) | CN203590182U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112688678A (en) * | 2019-10-18 | 2021-04-20 | 艾普凌科有限公司 | Analog switch |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509781B2 (en) * | 2001-03-20 | 2003-01-21 | Koninklijke Philips Electronics N.V. | Circuit and method for controlling a dynamic, bi-directional high voltage analog switch |
| US6836159B2 (en) * | 2003-03-06 | 2004-12-28 | General Electric Company | Integrated high-voltage switching circuit for ultrasound transducer array |
| JP4618164B2 (en) * | 2005-09-20 | 2011-01-26 | 株式会社デンソー | Switch circuit |
| JP2007295209A (en) * | 2006-04-25 | 2007-11-08 | Renesas Technology Corp | Analog switch circuit |
| US9453886B2 (en) * | 2011-04-21 | 2016-09-27 | Renesas Electronics Corporation | Switch circuit, selection circuit, and voltage measurement device |
-
2012
- 2012-11-02 JP JP2012242500A patent/JP6023551B2/en not_active Expired - Fee Related
-
2013
- 2013-11-04 CN CN201320688910.4U patent/CN203590182U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112688678A (en) * | 2019-10-18 | 2021-04-20 | 艾普凌科有限公司 | Analog switch |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2014093635A (en) | 2014-05-19 |
| JP6023551B2 (en) | 2016-11-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140507 Termination date: 20171104 |