CN203480500U - Multi-light-microprocessor program downloading device based on I2C bus - Google Patents
Multi-light-microprocessor program downloading device based on I2C bus Download PDFInfo
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- CN203480500U CN203480500U CN201320650908.8U CN201320650908U CN203480500U CN 203480500 U CN203480500 U CN 203480500U CN 201320650908 U CN201320650908 U CN 201320650908U CN 203480500 U CN203480500 U CN 203480500U
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Abstract
The utility model discloses a multi-light-microprocessor program downloading device based on an I2C bus. The multi-light-microprocessor program downloading device is mainly composed of an ARM microprocessor, an eight-channel analog switch, a display system and an SFP socket, wherein the eight-channel analog switch, the display system and the SFP socket are respectively connected with the ARM microprocessor. The multi-light-microprocessor program downloading device further comprises a connector circuit, the connector circuit is respectively connected with the ARM microprocessor and the SFP socket, the eight-channel analog switch is connected with the SFP socket, and light microprocessors DS4830A are connected to the SFP socket. The multi-light-microprocessor program downloading device is reasonable in design, a traditional e-writer and a JTAG emulator are replaced, a program can be downloaded to the multiple light microprocessors DS4830A at a time, the working strength of the production and operation staff is greatly lightened, the manufacturing technology is optimized, and the production efficiency is improved.
Description
Technical field
The utility model relates to program downloading apparatus field, specifically, is the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus.
Background technology
Concerning traditional microprocessor, download (upgrading) executable program and generally adopt program burn writing device or JTAG emulator, in large-scale production, use such equipment investment large, high to operating personnel's technical requirement.And the optical transceiver module (SFP optical transceiver module) of the light microcontroller DS4830A of use Mei Xin semiconductor company (MAXIM) is because the area of PCBA is little, the connector of arranging JTAG emulator in Design PCB is difficult, also inconvenient before chip and components and parts paster in addition, first use fever writes light microprocessor DS4830A to be carried out to programming or the download of program.
Except traditional program downloading mode, also there is the self initializing program (BOOTLOADER) making with light microprocessor DS4830A to carry out program download.But be generally, that a host computer coordinates an evaluation board downloading to download a light microprocessor DS4830A.
The mode device therefor investment that adopts program burn writing device or JTAG emulator to download is large,, and use the self initializing program (BOOTLOADER) of existing smooth microprocessor DS4830A to carry out program download, there is the shortcoming that production efficiency is low in the shortcoming high to operating personnel's technical requirement.
Utility model content
The purpose of this utility model is to provide the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus, reasonable in design, replace traditional fever writes and JTAG emulator, and once can download in a plurality of smooth microprocessor DS4830A, greatly alleviated production operation personnel's working strength, optimize production technology, improved production efficiency.
The utility model is achieved through the following technical solutions: the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus, mainly by ARM microprocessor, and the 8 tunnels analogy switches that are connected with ARM microprocessor respectively, display system, SFP socket form, also comprise interface circuit, described interface circuit is connected with SFP socket with arm processor respectively, 8 tunnels analogy switches described in it are connected with SFP socket, are connected with light microprocessor DS4830A on described SFP socket.
Its principle of work and effect: (1) is plugged on the SFP optical transceiver module of the light microprocessor DS4830A with not downloading on SFP socket.The I2C interface of light microprocessor DS4830A has been connected in the I2C bus of ARM microprocessor and interface circuit by the I2C interface of SFP socket.(2) ARM microprocessor is controlled the reset pin (RST) of light microprocessor DS4830A by controlling 8 tunnels analogy switches, the mode of operation of all light microprocessor DS4830A is switched to normal condition, and by all eight duties that light microprocessor DS4830A enters its self initializing program (BOOTLOADER).The BOOTLOADER state of light microprocessor is deposited in and in the register of ARM microprocessor, in display system, show (DS4830A has two kinds of patterns: reset mode and normal condition) simultaneously.(3) host computer computer expert crosses the register of the I2C bus inquiry ARM microprocessor of interface circuit, after all smooth microprocessor processes normal conditions, host computer is called in the executable code of light microprocessor DS4830A, and utilize the self initializing program (BOOTLOADER) of light microprocessor to carry out program download by I2C bus, after the program that completes is downloaded, light microprocessor DS4830A redirect is exited BOOTLOADER and is entered Application Status.(4) after redirect completes, ARM microprocessor on device carries out the control of analog switch by 8 tunnels analogy switches, successively the mode of operation of each light microprocessor DS4830A is switched to normal condition, and other light microprocessor of seven is switched to reset mode, check so whether this light microprocessor in normal condition normally downloads.Operate so successively all light microprocessor DS4830A of poll and whether correctly download, and show by display system the state of downloading.
For better realizing the utility model, described ARM microprocessor is connected with SFP socket with sda line by the scl line of I2C bus, interface circuit described in it is connected with ARM microprocessor with sda line by I2C bus scl line, and the interface circuit described in it is connected with SFP socket with sda line by I2C bus scl line.
Its principle of work and effect: I2C bus, by for transmitting the sda line of data and the universal serial bus forming for the scl line of transmit clock signal, can transmit and receive data.Can be between CPU and controlled IC, to carry out two-way transmission between IC and IC, quick mode bit rate is up to 400kbit/s, and fast mode Hs pattern bit rate is up to 3.4Mbit/s.Variously by control circuit, be all connected in parallel in this bus, but the number of only putting through just as telephone set separately could be worked, so each circuit and module have unique address, in the transmitting procedure of information, in I2C bus and each modular circuit connecing be primary controller (or controlled device), be again transmitter (or receiver), this depends on the function that it will complete.The control signal that CPU sends is divided into address code and controlled quentity controlled variable two parts, and address code is used for addressing, connects and needs the circuit controlled, determines the kind of controlling; The amount that controlled quentity controlled variable determines the classification (as contrast, brightness etc.) of this adjustment and needs to adjust.Like this, although each control circuit hang in same bus, independent of one another, uncorrelated mutually.I2C bus is total three types signal in transmitting data procedures, they respectively: commencing signal, end signal and answer signal.Commencing signal: when scl line is high level, sda line to low transition, starts to transmit data by high level.End signal: when scl line is high level, sda line to high level saltus step, finishes to transmit data by low level.Answer signal: receive the IC of data after receiving 8bit data, send specific low level pulse to the IC that sends data, represent to have received data.CPU sends after a signal to controlled cell, waits for that controlled cell sends an answer signal, and CPU receives after answer signal, makes the judgement that whether continues transmission of signal according to actual conditions.If do not receive answer signal, by being judged as controlled cell, break down.When using the utility model, according to I2C data transmission principle, utilize scl line and sda line to carry out the data transmission between ARM microprocessor, SFP socket glazing microprocessor DS4830A, interface circuit etc.
For better realizing the utility model, described interface circuit is LPT/I2C interface circuit and USB/I2C interface circuit.LPT/I2C interface circuit can be converted into LPT reading and writing data I2C reading and writing data, and USB/I2C interface circuit can be converted into I2C reading and writing data by usb data read-write.
For better realizing the utility model, described LPT/I2C interface circuit master chip adopts can realize the 74HC245 chip that LPT read-write is converted into I2C read-write, and described USB/I2C interface circuit master chip adopts can realize the CH341 chip that USB read-write is converted into I2C read-write.Routine data is connected to the DB25 passage of LPT/I2C interface circuit by DB25 connecting line, then by 74HC245 chip, LPT LPT read-write is converted into the read-write of I2C bus.Routine data is connected to the USB mouth of USB/I2C interface circuit by USB connecting line, then by CH341 chip, USB read-write is converted into the read-write of I2C bus.Wherein LPT LPT and USB mouth interlock, and a certain moment can only a kind of communication modes of choice for use.
For better realizing the utility model, described display system preferably adopts LED display system.The power dissipation ratio of LED display system and LCD display system is approximately 1:10, and higher refresh rate makes LED aspect video, have better performance performance, the wide visual angle that reaches 160 ° can be provided, can show various words, numeral, coloured image and animation information, also can play the colour-video signals such as TV, video recording, VCD, DVD, the broadcast of can also networking of several display screens.The individual element reaction velocity of organic LED display screen is 1000 times of LCD liquid crystal display, also can look after and not miss, and adapt to the low temperature of 40 degrees below zero under high light.
For better realizing the utility model, the master chip of 8 described tunnels analogy switches adopts 2 ADG888.8 tunnels analogy switches use two ADG888 to realize, and are controlled the switch of 8 tunnels analogy switches by ARM microprocessor, and analog switch is controlled the reset RST pin of light microprocessor DS4830A.Because the reset of light microprocessor is Low level effective, in use, when switch connection, the reset RST pin of light microprocessor is pulled down to ground, makes this light microprocessor DS4830A in reset mode.As switch disconnects, this light microprocessor is in running order.
For better realizing the utility model, it is the ARM7 process chip of ADUC7020 that described ARM microprocessor preferably adopts model.
ADUC7020 is fully-integrated 1 MSPS, 12 Bit Data Acquisition Systems, integrated high-performance hyperchannel ADC, 16/32 MCU and Flash/EE storer in single-chip.ADC has the nearly 12 single-ended inputs in tunnel.Also can provide in addition 4 tunnel inputs multiplexing with 4 DAC output pins.ADC can work under single-ended mode or difference input pattern.ADC input voltage range is 0 V to VREF.The peripheral hardware setting of ADC that low drift bandgap voltage reference, temperature sensor and voltage comparator are perfect.These devices produce the inside high frequency clock signal of 41.78MHz by a sheet internal oscillator and phaselocked loop (PLL).This clock signal is carried out relaying by a programmable clock frequency divider, produces therein MCU kernel clock work speed.Microcontroller kernel is ARM7TDMI, and it is 16/32 RISC machines, and peak performance reaches as high as 41 MIPS.Embedded has 8 KB SRAM and the non-volatile Flash/EE storer of 62 KB.ARM7TDMI kernel is considered as a linear array by all storeies and register.
For better realizing the utility model, described SFP socket number is 8.In use, 8 SFP sockets can insert 8 light microprocessor DS4830A simultaneously, once carry out the program of 8 light microprocessor DS4830A and download.
For better realizing the utility model, on described interface circuit, be connected with host computer.Host computer transmits the program of the required download of light microprocessor DS4830A by interface circuit.
The utility model compared with prior art, has the following advantages and beneficial effect:
(1) the utility model is reasonable in design, replace traditional fever writes and JTAG emulator, and once can download in a plurality of smooth microprocessor DS4830A, greatly alleviated production operation personnel's working strength, optimize production technology, improved production efficiency.
(2) data that the utility model can transmit host computer are carried out LPT reading and writing data and are converted into I2C reading and writing data, usb data read-write is converted into I2C reading and writing data, wherein LPT LPT and USB mouth interlock, be that a certain moment can only a kind of communication modes of choice for use, thereby reach conveniently with connecting between host computer.
(3) the utility model can reach the program download of 8 light microprocessor DS4830A simultaneously.
(4) the utility model is chip used is all existing mature technology product with ARM microprocessor model, can reach the work of efficient stable in actual applications, due to its integrated characteristic, have advantages of that energy consumption is little, thereby when downloading, only need to power by interface circuit, can make the utility model normal operation.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present utility model.
Wherein: 1-ARM microprocessor, 2-SFP socket, 3-8 tunnels analogy switch, 4-display system, 5-interface circuit, 6-SDA line, 7-SCL line, 8-host computer.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but embodiment of the present utility model is not limited to this.
Embodiment:
The program downloading apparatus of a plurality of smooth microprocessors based on I2C bus, as shown in Figure 1, mainly by ARM microprocessor 1, and the 8 tunnels analogy switches 3 that are connected with ARM microprocessor 1 respectively, display system 4, SFP socket 2 form, also comprise interface circuit 5, described interface circuit 5 is connected with SFP socket 2 with arm processor 1 respectively, and 8 tunnels analogy switches 3 described in it are connected with SFP socket 2, are connected with light microprocessor DS4830A on described SFP socket 2.
Its principle of work and effect: (1) is plugged on the SFP optical transceiver module of the light microprocessor DS4830A with not downloading on SFP socket.The I2C interface of the I2C interface of light microprocessor DS4830A by SFP socket has been connected to (2) ARM microprocessor in the I2C bus of ARM microprocessor and interface circuit and by controlling 8 tunnels analogy switches, has controlled the reset pin (RST) of light microprocessor DS4830A, the mode of operation of all light microprocessor DS4830A is switched to normal condition, and by all eight duties that light microprocessor DS4830A enters its self initializing program (BOOTLOADER).The BOOTLOADER state of light microprocessor is deposited in and in the register of ARM microprocessor, in display system, show (DS4830A has two kinds of patterns: reset mode and normal condition) simultaneously.(3) host computer computer expert crosses the register of the I2C bus inquiry ARM microprocessor of interface circuit, after all smooth microprocessor processes normal conditions, host computer is called in the executable code of light microprocessor DS4830A, and utilize the self initializing program (BOOTLOADER) of light microprocessor to carry out program download by I2C bus, after the program that completes is downloaded, light microprocessor DS4830A redirect is exited BOOTLOADER and is entered Application Status.(4) after redirect completes, ARM microprocessor on device carries out the control of analog switch by 8 tunnels analogy switches, successively the mode of operation of each light microprocessor DS4830A is switched to normal condition, and other light microprocessor of seven is switched to reset mode, check so whether this light microprocessor in normal condition normally downloads.Operate so successively all light microprocessor DS4830A of poll and whether correctly download, and show by display system the state of downloading.For better realizing the utility model, as shown in Figure 1, described ARM microprocessor 1 connects with SFP socket 2 by I2C line, the interface circuit 5 described in it by I2C line, be connected on ARM microprocessor 1 and SFP socket 2 on.
For better realizing the utility model, as shown in Figure 1, described ARM microprocessor 1 is connected with SFP socket 2 with sda line 7 by the scl line 7 of I2C bus, interface circuit 5 described in it is connected with ARM microprocessor 1 with sda line 6 by the scl line 7 of I2C bus, and the interface circuit 5 described in it is also connected with SFP socket 2 with sda line 6 by the scl line 7 of I2C bus.
Its principle of work and effect: I2C bus, by for transmitting the sda line of data and the universal serial bus forming for the scl line of transmit clock signal, can transmit and receive data.Can be between CPU and controlled IC, to carry out two-way transmission between IC and IC, quick mode bit rate is up to 400kbit/s, and fast mode Hs pattern bit rate is up to 3.4Mbit/s.Variously by control circuit, be all connected in parallel in this bus, but the number of only putting through just as telephone set separately could be worked, so each circuit and module have unique address, in the transmitting procedure of information, in I2C bus and each modular circuit connecing be primary controller (or controlled device), be again transmitter (or receiver), this depends on the function that it will complete.The control signal that CPU sends is divided into address code and controlled quentity controlled variable two parts, and address code is used for addressing, connects and needs the circuit controlled, determines the kind of controlling; The amount that controlled quentity controlled variable determines the classification (as contrast, brightness etc.) of this adjustment and needs to adjust.Like this, although each control circuit hang in same bus, independent of one another, uncorrelated mutually.I2C bus is total three types signal in transmitting data procedures, they respectively: commencing signal, end signal and answer signal.Commencing signal: when scl line is high level, sda line to low transition, starts to transmit data by high level.End signal: when scl line is high level, sda line to high level saltus step, finishes to transmit data by low level.Answer signal: receive the IC of data after receiving 8bit data, send specific low level pulse to the IC that sends data, represent to have received data.CPU sends after a signal to controlled cell, waits for that controlled cell sends an answer signal, and CPU receives after answer signal, makes the judgement that whether continues transmission of signal according to actual conditions.If do not receive answer signal, by being judged as controlled cell, break down.When using the utility model, according to I2C data transmission principle, utilize scl line and sda line to carry out the data transmission between ARM microprocessor, SFP socket glazing microprocessor DS4830A, interface circuit etc.
For better realizing the utility model, as shown in Figure 1, described interface circuit 5 is LPT/I2C interface circuit and USB/I2C interface circuit.LPT/I2C interface circuit can be converted into LPT reading and writing data I2C reading and writing data, and USB/I2C interface circuit can be converted into I2C reading and writing data by usb data read-write.
For better realizing the utility model, as shown in Figure 1, described LPT/I2C interface circuit master chip adopts can realize the 74HC245 chip that LPT read-write is converted into I2C read-write, and described USB/I2C interface circuit master chip adopts can realize the CH341 chip that USB read-write is converted into I2C read-write.Routine data and power supply data are connected to the DB25 passage of LPT/I2C interface circuit by DB25 connecting line, then by 74HC245 chip, LPT LPT read-write is converted into the read-write of I2C bus.Routine data and power supply data are connected to the USB mouth of USB/I2C interface circuit by USB connecting line, then by CH341 chip, USB read-write is converted into the read-write of I2C bus.Wherein LPT LPT and USB mouth interlock, and a certain moment can only a kind of communication modes of choice for use.
For better realizing the utility model, as shown in Figure 1, described display system 4 preferably adopts LED display system.The power dissipation ratio of LED display system and LCD display system is approximately 1:10, and higher refresh rate makes LED aspect video, have better performance performance, the wide visual angle that reaches 160 ° can be provided, can show various words, numeral, coloured image and animation information, also can play the colour-video signals such as TV, video recording, VCD, DVD, the broadcast of can also networking of several display screens.The individual element reaction velocity of organic LED display screen is 1000 times of LCD liquid crystal display, also can look after and not miss, and adapt to the low temperature of 40 degrees below zero under high light.
For better realizing the utility model, as shown in Figure 1, the master chip of 8 described tunnels analogy switches 3 adopts 2 ADG888.8 tunnels analogy switches use two ADG888 to realize, and are controlled the switch of 8 tunnels analogy switches by ARM microprocessor, and analog switch is controlled the reset RST pin of light microprocessor DS4830A.Because the reset of light microprocessor is Low level effective, in use, when switch connection, the reset RST pin of light microprocessor is pulled down to ground, makes this light microprocessor DS4830A in reset mode.As switch disconnects, this light microprocessor is in normal condition.
For better realizing the utility model, as shown in Figure 1, described ARM microprocessor 1 preferably adopts the ARM7 process chip that model is ADUC7020.
ADUC7020 is fully-integrated 1 MSPS, 12 Bit Data Acquisition Systems, integrated high-performance hyperchannel ADC, 16/32 MCU and Flash/EE storer in single-chip.ADC has the nearly 12 single-ended inputs in tunnel.Also can provide in addition 4 tunnel inputs multiplexing with 4 DAC output pins.ADC can work under single-ended mode or difference input pattern.ADC input voltage range is 0 V to VREF.The peripheral hardware setting of ADC that low drift bandgap voltage reference, temperature sensor and voltage comparator are perfect.These devices produce the inside high frequency clock signal of 41.78MHz by a sheet internal oscillator and phaselocked loop (PLL).This clock signal is carried out relaying by a programmable clock frequency divider, produces therein MCU kernel clock work speed.Microcontroller kernel is ARM7TDMI, and it is 16/32 RISC machines, and peak performance reaches as high as 41 MIPS.Embedded has 8 KB SRAM and the non-volatile Flash/EE storer of 62 KB.ARM7TDMI kernel is considered as a linear array by all storeies and register.
For better realizing the utility model, as shown in Figure 1, described SFP socket (2) number is 8.In use, 8 SFP sockets can insert 8 with the SFP optical transceiver module of light microprocessor DS4830A simultaneously, download like this with regard to once carrying out the program of 8 light microprocessor DS4830A.
For better realizing the utility model, as shown in Figure 1, on described interface circuit (5), be connected with host computer 8.Host computer transmits the program of the required download of light microprocessor DS4830A by interface circuit.
The utility model is reasonable in design, replace traditional fever writes and JTAG emulator, and once can download in a plurality of smooth microprocessors (DS4830A), greatly alleviated production operation personnel's working strength, optimize production technology, improved production efficiency.
The above; it is only preferred embodiment of the present utility model; not the utility model is done to any pro forma restriction, any simple modification, equivalent variations that every foundation technical spirit of the present utility model is done above embodiment, within all falling into protection domain of the present utility model.
Claims (9)
1. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus, it is characterized in that: mainly by ARM microprocessor (1), and the 8 tunnels analogy switches (3) that are connected with ARM microprocessor (1) respectively, display system (4), SFP socket (2) form; Also comprise interface circuit (5), described interface circuit (5) respectively same arm processor (1) is connected with SFP socket (2), 8 tunnels analogy switches (3) described in it are connected with SFP socket (2), on described SFP socket (2), are connected with light microprocessor DS4830A.
2. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus according to claim 1, it is characterized in that: described ARM microprocessor (1) is connected with SFP socket (2) with sda line (6) by the scl line (7) of I2C bus, interface circuit described in it (5) is connected with ARM microprocessor (1) with sda line (6) by the scl line (7) of I2C bus, and the interface circuit described in it (5) is also connected with SFP socket (2) with sda line (6) by the scl line (7) of I2C bus.
3. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus according to claim 1 and 2, is characterized in that: described interface circuit (5) is LPT/I2C interface circuit and USB/I2C interface circuit.
4. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus according to claim 3, it is characterized in that: described LPT/I2C interface circuit master chip adopts can realize the 74HC245 chip that LPT read-write in parallel port is converted into the read-write of I2C bus, described USB/I2C interface circuit master chip adopts can realize the CH341 chip that USB read-write is converted into the read-write of I2C bus.
5. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus according to claim 1, is characterized in that: described display system (4) adopts LED display system.
6. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus according to claim 1, is characterized in that: the master chip of 8 described tunnels analogy switches (3) adopts 2 ADG888.
7. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus according to claim 1 and 2, is characterized in that: described ARM microprocessor (1) adopts the ARM7 process chip that model is ADUC7020.
8. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus according to claim 1 and 2, is characterized in that: described SFP socket (2) number is 8.
9. the program downloading apparatus of a plurality of smooth microprocessors based on I2C bus according to claim 1 and 2, is characterized in that: on described interface circuit (5), be connected with host computer (8).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708552A (en) * | 2015-11-18 | 2017-05-24 | 研祥智能科技股份有限公司 | Programming method, apparatus and system for digital power supply |
| CN108599861A (en) * | 2018-07-27 | 2018-09-28 | 深圳市极致兴通科技有限公司 | A kind of general active light module writes yard device and equipment |
-
2013
- 2013-10-22 CN CN201320650908.8U patent/CN203480500U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708552A (en) * | 2015-11-18 | 2017-05-24 | 研祥智能科技股份有限公司 | Programming method, apparatus and system for digital power supply |
| CN108599861A (en) * | 2018-07-27 | 2018-09-28 | 深圳市极致兴通科技有限公司 | A kind of general active light module writes yard device and equipment |
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