CN203457162U - Terrestrial digital television broadcast spectrum sensing system - Google Patents

Abstract

The utility model discloses a terrestrial digital television broadcast spectrum sensing system. A data output terminal of a radiofrequency receiving module is connected with a data input terminal of a central controlling and processing module through an analog-digital conversion module. A data output terminal of a radiofrequency emitting module is connected with another data input terminal of the central controlling and processing module through a digital-analog conversion module. A local oscillator output terminal of the central controlling and processing module is connected with local oscillator control terminals of the radiofrequency receiving module and the radiofrequency emitting module. Through a simplified system hardware structure, the system of the utility model realizes rapid switching of terrestrial digital television broadcast frequency bands and achieves the aims of ensuring the spectrum sensing speed while saving processor resources. By employing an FPGA as a processor to flexibly control local oscillator frequency output, the terrestrial digital television broadcast full-band coverage is enabled and acquired signals are windowed. A coordinate rotation digital computer (CORDIC) algorithm is used to realize FFT processing, and the sensing of the terrestrial digital television broadcast frequency bands is achieved by adopting an FFT-based energy detection algorithm.

Description

Ground digital television broadcast frequency spectrum perception system

Technical field

The utility model belongs to communication technical field, is specifically related to a kind of ground digital television broadcast (DVB-T) frequency spectrum perception system.

Background technology

Along with the development of radio communication service, available frequency spectrum resource growing tension, limited frequency spectrum resource becomes the bottleneck of restriction wireless communication technology development gradually.Therefore, save frequency spectrum resource and improve the availability of frequency spectrum by a key areas that is future wireless system development.Yet at current spectrum authorization, distribute under system, frequency spectrum resource dog-eat-dog in some specific frequency range, unauthorized user can not take other and authorize the no frequency range of frequency range, has caused the availability of frequency spectrum lower.The in the situation that deficient and utilance being low at frequency spectrum resource, in order to change traditional frequency spectrum resource method of salary distribution, make full use of idle frequency spectrum resource on time domain and spatial domain, people have proposed cognitive radio technology.

One of important application of cognitive radio is frequency spectrum perception, and because ground digital television broadcast frequency range is a pith of people's amusement and recreation, its band limits is 50Mhz-878Mhz.In use, when often watching ground digital television broadcast, people just take a part of frequency range wherein, and for other frequency ranges, in idle condition.Do not disturbing on the basis of authorized user, if the frequency range in idle can be fully utilized, will improve greatly the availability of frequency spectrum.Therefore, the research of the frequency spectrum perception technology of ground digital television broadcast signal has become the study hotspot of cognition wireless electrical domain.

The realization of the frequency spectrum perception signal processing circuit of ground digital television broadcast signal is generally based on MCU chip, dsp chip or fpga chip at present.The mode of operation of DSP in essence with traditional C PU instruction fetch, the modes such as decoding and execution are identical, are subject to the restriction of instruction cycle, sequencing control a little less than, and complicated for computing, the algorithm that amount of calculation is large is often difficult to meet real-time demand.FPGA has the advantages such as powerful parallel processing Neng Li ﹑ fast operation, this Di of Cheng ﹑ reliability are high, flexible in programming, its inner integrated a large amount of distributed RAM is used for realizing logical design, block RAM is for data high-speed storage, PLL is for the management of clock, embedded multiplier is for the processing of digital signal, high-speed transceiver is for data communication etc., the design of streamline simultaneously can be dwindled processing time delay, improve the maximum operating frequency that FPGA can reach, have advantages of that the chips such as DSP are incomparable.

In the Chinese patent application that is CN1885742A at publication number " a kind of hardware terminal of cognitive radio experiment system ", what system adopted is the bi-processor architecture of DSP-FPGA, adopt frequency spectrum perception algorithm that baseband signal reasonable distribution is processed to DSP and FPGA, take full advantage of the advantage separately of DSP and FPGA.But because system is difficult to meet the requirement of real-time and the processing speed of frequency spectrum perception system, and hardware configuration is more complicated, to realize very difficultly, cost is very high, is unfavorable for business promotion.

Utility model content

Technical problem to be solved in the utility model is to provide a kind of ground digital television broadcast frequency spectrum perception system, it is to simplify system hardware structure, realize ground digital television broadcast frequency range and switch fast, when guaranteeing frequency spectrum perception speed, saving processor resource is object.

For addressing the above problem, the utility model is achieved through the following technical solutions:

Based on the designed ground digital television broadcast frequency spectrum perception system of above-mentioned ground digital television broadcast frequency spectrum sensing method, mainly by power unit and the radio-frequency transmissions receiving unit and the data processing division that are connected with power unit, be grouped into; Wherein radio-frequency transmissions receiving unit comprises Receiver Module and radiofrequency emitting module; Data processing section comprises center control processing module, analog-to-digital conversion module and D/A converter module; The data input pin that the data output end of Receiver Module is controlled processing module through number conversion module with center is connected; The data input pin that the data output end of radiofrequency emitting module is controlled processing module through D/A converter module with center is connected; The local oscillator output of center control processing module connects respectively the local oscillator control end of Receiver Module and radiofrequency emitting module.

In such scheme, it is programmable logic controller (PLC) (FPGA) that processing module is controlled at described center.

Compared with prior art, the utlity model has following characteristics:

1, by take FPGA, as processor, control flexibly local frequency and export, ground digital television broadcast full frequency band is covered, the signal gathering is carried out to windowing, adopt computer rotational coordinates (Cordic) algorithm to realize FFT and process, and use and realized the perception to ground digital television broadcast frequency range based on FFT energy detection algorithm;

2, the inner integrated a large amount of distributed RAM of FPGA are used for realizing logical design, block RAM is for data storage, PLL is for the management of clock, embedded multiplier is used for processing of digital signal etc., therefore native system has advantages of that powerful parallel processing Neng Li ﹑ fast operation, this Di of Cheng ﹑ reliability are high, flexible in programming;

3, adopt FPGA as the uniprocessor structure of core control processor, send reception with radio frequency and combine, compare multi-processor structure, simplified system configuration, saved hardware resource and cost, reduced the energy consumption of system;

4, this frequency spectrum perception system is divided the whole frequency range of DVB-T, can effectively detect the use of radio-frequency spectrum Mid Frequency and promptly utilize interim no frequency, and not disturbing the communication between other authorized users;

5, at perception algorithm, adopt the energy measuring based on FFT, use improved Cordic algorithm to realize answering in FFT computing and take advantage of, both guaranteed data processing speed, saved again system resource, whole algorithm complex is low, consumes shortly during detection, realizes simple.

Accompanying drawing explanation

Fig. 1 is ground digital television broadcast frequency spectrum perception system embodiment general frame block diagram;

Fig. 2 is FPGA Central Control Module structured flowchart;

Fig. 3 is the block diagram of the energy detection algorithm based on FFT;

Fig. 4 is that Cordic algorithm is realized the structured flowchart that FFT processes.

Embodiment

Referring to Fig. 1, a kind of ground digital television broadcast frequency spectrum perception system, is mainly grouped into by power unit and the radio-frequency transmissions receiving unit and the data processing division that are connected with power unit; Wherein radio-frequency transmissions receiving unit comprises Receiver Module and radiofrequency emitting module; Data processing section comprises center control processing module, analog-to-digital conversion module and D/A converter module; The data input pin that the data output end of Receiver Module is controlled processing module through number conversion module with center is connected; The data input pin that the data output end of radiofrequency emitting module is controlled processing module through D/A converter module with center is connected; The local oscillator output that processing module is controlled at center connects the local oscillator control end of Receiver Module and radiofrequency emitting module through a vibration module.

The structure of radiofrequency emitting module is same as the prior art or close.Receiver Module includes DVB-T reception antenna, and low pass filter, low noise amplifier and processing circuitry of intermediate frequency, make signal be fixed on L Mhz(1<L<8 by double conversion) in frequency band range.Be that processing circuitry of intermediate frequency is controlled under its local oscillator effect the signal of radio frequency reception is fixed on to L Mhz(1<L<8 at FPGA) in frequency band range and to the DVB-T signal receiving, carry out power amplification.When the signal to noise ratio of radio frequency receiving signal is lower, gained signal power is smaller, and receives the signal to noise ratio of signal when larger, and gained signal power is larger.The power of sending into the input signal of data processing section after intermediate-freuqncy signal preliminary treatment is at least greater than an A/D quantization level, and signal amplitude will be unified as far as possible.In the utility model preferred embodiment, the local oscillator module of radiofrequency emitting module and Receiver Module is used the ADF4351 phase-locked loop chip of ADI company, realizes low noise, quick lock in output frequency.

It is on-site programmable gate array FPGA (Field Programmable Gate Array) that processing module is controlled at center.In the utility model preferred embodiment, the CycloneII EP2C8Q240C8N chip of the ALTERA company of processing module FPGA employing is controlled at center, inner integrated a large amount of distributed RAM for realize logical design, block RAM for data high-speed storage, PLL for the management of clock, embedded multiplier for the processing of digital signal, high-speed transceiver for data communication etc., there is the advantages such as powerful parallel processing Neng Li ﹑ fast operation, this Di of Cheng ﹑ reliability are high, flexible in programming.

Processing module FPGA is controlled at center, as shown in Figure 2, comprises clock module, Data Control module, local oscillator control module, perception algorithm module and frequency spectrum state information module.Clock module is coordinated modules normal operation, and Data Control module connects local oscillator control module, perception algorithm module, frequency spectrum state information module; Local oscillator control module output control word connects radio-frequency head local frequency generation module, and signal access perception algorithm module, perception algorithm module that analog-to-digital conversion module gathers radio frequency reception connect frequency spectrum state information module.Radio-frequency transmitter receives signal through accessing analog-to-digital conversion module AD after intermediate frequency preliminary treatment, is converted to the perception algorithm module of digital signal access FPGA, and perception algorithm module result is delivered to frequency spectrum state information module, obtains finally detecting the information of frequency range.Frequency spectrum state information module information frequency range, when the free time, is converted to analog signal by digital-to-analogue conversion by digital signal by the band information detecting, and the analog signal of DA conversion chip is launched through the transmitter of radio frequency, otherwise, control transmitter in resting state.

The local frequency generation module of Receiver Module is in FPGA, under the effect of local oscillator control module, to produce g the local frequency that frequency range is corresponding, wherein g=(878-50)/L.

The Data Control module of processing module is controlled according to the logical sequence of the local oscillator control module of its connection of pll clock management coordination in FPGA, perception algorithm module and frequency spectrum state information module in center, guarantees each submodule co-ordination.In system, need the work clock of different frequency to drive corresponding operating circuit, the phase-locked loop pll of FPGA is processed accordingly to outside input clock.PLL provides advanced Clock management ability, the sampled clock signal of for example local oscillator external clock output, AD, DA work.

Center is controlled the control word of the local oscillator control module of processing module and is sent into the local oscillator in radio-frequency module with the clock frequency of 10Mhz, drive the AD conversion chip of modulus, D/A converter module to gather radiofrequency signal simultaneously, after perception algorithm finishes each time, according to court verdict, control the output of local frequency control word.

The perception algorithm module of processing module is controlled at center, as shown in Figure 3, and to the radiofrequency signal x gathering _i(n) carry out windowing w (n), use the FFT that Cordic algorithm is realized to process Y _i(w), the data after FFT conversion are carried out to a square summation and be averaged, obtain the energy value E of collection signal, compare with default threshold values λ, obtain final testing result.

Described Cordic algorithm is realized FFT process, as shown in Figure 4, address generating module is under sequencing control, produce the write signal of first memory, after first memory is write completely, data are read and export butterfly front end computing module to, and address generating module, under sequencing control, produces the write signal of second memory simultaneously.Angle memory module reads angle and outputs to Cordic algoritic module under sequencing control, the result of butterfly front end computing module outputs to Cordic algoritic module, result through the output of Cordic algorithm is fed through mould correction module, when then the result after proofreading and correct being sent into first memory again, sequencing control produces the write signal of first memory, the input data of usining as next stage butterfly computation.Sequencing control produces the read signal of second memory, data handling procedure in deduplication storage 1, and the read-write operation of first memory and second memory hockets, until butterfly computation finishes.

Address above mentioned generation module, for producing and be counted as between the count block of N (256≤N≤2048) under the sequencing control that is 50M at clock, makes orderly the carrying out of read-write energy of memory data.

Above-mentioned the first and second memory modules are the dual port RAM core producing with QuartusII, and storage depth is N (256≤N≤2048), by control, is read and write and is enabled, and reads respectively.

Each butterfly structure of above-mentioned butterfly front end computing module completes primary iteration computing

$X_m\left(k\right)=X_{m-1}\left(k\right)+X_{m-1}\left(j\right)W_{N,}^r$

$X_m\left(j\right)=X_{m-1}\left(k\right)-X_{m-1}\left(j\right)W_N^r,$

In formula, m represents m row iteration, k, and j is data place line number.In the time of under sequencing control, the X of gained will be calculated _m-1(k) writing the input data as next stage in RAM aligns with the result of calculating through mould correction module.

Above-mentioned Cordic algoritic module: Cordic algoritic module is realized by Verilog language in FPGA, input signal is after initialization, send into Cordic computing module simultaneously, adopt 16 valid data positions and a high-order sign bit as input, adopt rotary mode, flowing water linear operation, carries out 16 iteration and realizes multiplier function.

Above-mentioned angle memory module produces with mif file and preserves with matlab software, then after Quartus II software is opened, saves as the type of hex file, and hex file now imports in the ROM of FPGA generation again.Data Control module reads the parameter in ROM with certain clock cycle by address.

Above-mentioned mould correction module, by the iterative approach mould correction factor of 16 times, is decomposed into mould correction factor K

wherein ε ∈ { 1; + 1}, α=16, iteration K ≈ 0.60725, Cordic algoritic module output data are multiplied by K correction factor, send into memory module.

The frequency spectrum state information module that processing module is controlled at center be in detection DVB-T frequency band signals process, and frequency spectrum perception algorithm testing result is detection signal while not existing, and makes transmitter in running order, and by i(i ∈ { 1 in the DVB-T detecting; G}) the idle information of section frequency spectrum is delivered to transmitter, when detection signal does not exist, makes transmitter in resting state.

Claims (2)

1. ground digital television broadcast frequency spectrum perception system, is characterized in that: mainly by power unit and the radio-frequency transmissions receiving unit and the data processing division that are connected with power unit, be grouped into; Wherein radio-frequency transmissions receiving unit comprises Receiver Module and radiofrequency emitting module; Data processing section comprises center control processing module, analog-to-digital conversion module and D/A converter module; The data input pin that the data output end of Receiver Module is controlled processing module through number conversion module with center is connected; The data input pin that the data output end of radiofrequency emitting module is controlled processing module through D/A converter module with center is connected; The local oscillator output of center control processing module connects respectively the local oscillator control end of Receiver Module and radiofrequency emitting module.

2. ground digital television broadcast frequency spectrum perception system according to claim 1, is characterized in that: it is programmable logic controller (PLC) that processing module is controlled at described center.

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