CN203445119U - Integrated bi-directional ultra-low capacitance TVS device - Google Patents
Integrated bi-directional ultra-low capacitance TVS device Download PDFInfo
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Abstract
The utility model provides an integrated bi-directional ultra-low capacitance TVS device. The integrated bi-directional ultra-low capacitance TVS device comprises a first-conductivity type substrate, a first-conductivity type epitaxial layer located on the first-conductivity type substrate, a second-conductivity type buried layer located in the first-conductivity type epitaxial layer, a second-conductivity type epitaxial layer located on the first-conductivity type epitaxial layer, isolation structures, a first-conductivity type isolation structure, a second-conductivity type well, a second-conductivity type injection region, a first-conductivity type injection region, a first meal wire and a second metal wire, wherein the first-conductivity type epitaxial layer and the second-conductivity type epitaxial layer form a diode D2, the isolation structures penetrate the second-conductivity type epitaxial layer such that a first area, a second area and a third area can be formed, the first-conductivity type isolation structure is located inside the first area and is connected with the first-conductivity type substrate, the second-conductivity type well is located in the third area, the second-conductivity type injection region is located in the first area, the second-conductivity type injection region and the first-conductivity type isolation structure form a diode Z1, the first-conductivity type injection region is located in the second area and the second-conductivity type well, the first-conductivity type injection region and the second-conductivity type epitaxial layer form a diode D1, the first-conductivity type injection region and the second-conductivity type well form a diode Z2, the first metal wire is connected with the diode Z1 and the diode D1, and the second metal wire is connected with the diode D1 and the diode Z2. With the integrated bi-directional ultra-low capacitance TVS device adopted, package defects can be avoided, and the quality of device can be improved.
Description
Technical field
The utility model relates to technical field of manufacturing semiconductors, particularly the two-way ultra-low capacitance TVS of a kind of integrated form device.
Background technology
With respect to one-way ultra-low capacitance TVS device; two-way ultra-low capacitance TVS device is owing to having the feature of the electrical I-V curve of the routine (see figure 1) almost symmetry of positive and negative both direction; thereby in actual applications,, energy is the both direction of protective circuit simultaneously, so range of application is wider.Common, in two-way ultra-low capacitance TVS device, power supply electric capacity over the ground can be less than 0.3pF, and the ESD ability of positive and negative both direction can reach and is greater than 8kV.The structure of two-way ultra-low capacitance TVS device in the market roughly has three classes.
The first kind is connected from, the duplicate one-way ultra-low capacitance TVS device of performance two components according to the mode of Fig. 2.Due to VDD-to-VSS two ends full symmetric, can realize two-way ultra-low capacitance performance.But this structure has the following disadvantages:
1, need two groups of chip series connection, cost is higher;
2,, for less packaging body, two groups of chip cannot encapsulate simultaneously;
When 3, electric current is flowed through VDD-to-VSS two ends, because needs are through three diodes, power consumption is larger, easily reduces the peak current ability of device.
Equations of The Second Kind is directly the tunnel ends of the one-way ultra-low capacitance TVS device of two passages to be drawn, respectively as power end and ground end (see figure 3), due to two tunnel ends full symmetrics, can realize two-way ultra-low capacitance performance, but this structure has the following disadvantages:
1, two tunnel ends must be drawn from front simultaneously, thereby cause chip area larger, and cost is higher on the one hand, is not suitable on the other hand less packaging body;
While 2, encapsulating, two tunnel ends must each be made a call to a wires, and cost is higher;
When 3, electric current is flowed through passage two ends (VDD-to-VSS two ends), because needs are through three diodes, power consumption is larger, easily reduces the peak current ability of device.
The 3rd class is that two groups of one-way ultra-low capacitance TVS devices are formed in parallel according to the mode of Fig. 4, from the power Vcc I-V curve of GND over the ground, forward and reverse characteristic almost symmetry, but the electric capacity of the electric capacity of system line well below the common double of identical voltage to TVS diode.
The two-way ultra-low capacitance TVS device being combined by two groups of one-way ultra-low capacitance TVS devices, its power Vcc is the capacitance C of GND over the ground
tcan be expressed as:
Here C
d1and C
d2all less, C
z1and C
z2all than the above two large orders of magnitude, so the electric capacity after diode D1 and diode Z1 series connection is equal to the electric capacity of diode D1 substantially; Electric capacity after diode D2 and diode Z2 series connection is equal to the electric capacity of diode D2 substantially.And the electric capacity of whole circuit is also just equal to the electric capacity sum of diode D1 and diode D2 substantially.
When power Vcc adds positive potential, when ground GND adds negative potential: because diode D2 puncture voltage is higher, diode Z1 puncture voltage is lower, so diode Z1 takes the lead in puncturing, the power Vcc over the ground reverse breakdown voltage of GND can be expressed as:
V
BR=Vf
D1+V
Z1
Vf wherein
d1forward voltage drop for diode D1.
When power Vcc adds negative potential, when ground GND adds positive potential: because diode D1 puncture voltage is higher, diode Z2 puncture voltage is lower, so diode Z2 takes the lead in puncturing, ground GND can be expressed as the reverse breakdown voltage of power Vcc:
V
BR=Vf
D2+V
Z2
Vf wherein
d2forward voltage drop for diode D2.
If the puncture voltage of two diodes of visible Z1 and Z2 is substantially the same, the forward and reverse characteristic of two-way ultra-low capacitance TVS device combining is equivalent to a common bidirectional diode substantially, and its reverse breakdown voltage is controlled by the puncture voltage of Z1 and two diodes of Z2 mainly; Electric capacity is mainly subject to C
d1and C
d2control, so in order to realize ultra-low capacitance, reality is exactly to reduce C
d1and C
d2; Simultaneously power Vcc over the ground the positive and negative direction ESD ability reality of GND be to be also equal to respectively the forward ESD ability of D1, two diodes of D2 (reverse breakdown voltage of Z1 and two diodes of Z2 is lower, generally between 3.3V～7.0V, its reverse ESD ability is very high, can not consider).So in order to realize high ESD ability, reality is exactly to improve the forward ESD ability of D1, two diodes of D2.
The two-way ultra-low capacitance TVS device performance of the 3rd class formation is more outstanding, but because it is formed in parallel by two groups of one-way ultra-low capacitance TVS devices, still has the certain defect in encapsulation.Therefore, provide the two-way ultra-low capacitance TVS of a kind of integrated form device to become this area problem demanding prompt solution.
Utility model content
The purpose of this utility model is to provide the two-way ultra-low capacitance TVS of a kind of integrated form device, to solve two-way ultra-low capacitance TVS device of the prior art, by two groups of one-way ultra-low capacitance TVS devices, is formed in parallel, and has the problem of the certain defect in encapsulation.
For solving the problems of the technologies described above, the utility model provides the two-way ultra-low capacitance TVS of a kind of integrated form device, and the two-way ultra-low capacitance TVS of described integrated form device comprises:
The first conductivity type substrate;
Be formed at the first conductive type epitaxial layer in described the first conductivity type substrate;
Be formed at the second conduction type buried regions in described the first conductive type epitaxial layer;
Be formed at the second conductive type epitaxial layer on described the first conductive type epitaxial layer, described the first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Isolation structure, described isolation structure runs through described the second conductive type epitaxial layer, and in described the second conductive type epitaxial layer, formed first area, second area and the 3rd region;
Be formed at the first conduction type isolation in described first area, described the first conduction type isolation is connected with described the first conductivity type substrate;
Be formed at the second conductive type of trap in described the 3rd region;
Be formed at the second conduction type injection region in described first area, described the second conduction type injection region is connected with described the first conduction type isolation, and described the second conduction type injection region and described the first conduction type isolation form diode Z1;
Be formed at the first conduction type injection region in described second area and the second conductive type of trap, wherein, the first conduction type injection region in described second area and the second conductive type epitaxial layer form diode D1, and the first conduction type injection region in described the second conductive type of trap and the second conductive type of trap form diode Z2; And
The first metal wire that connects described diode Z1 and diode D1, connects the second metal wire of described diode D1 and diode Z2.
Optionally, in the two-way ultra-low capacitance TVS of described integrated form device, described the first conduction type is that P type, described the second conduction type are N-type; Or described the first conduction type is that N-type, described the second conduction type are P type.
Optionally, in the two-way ultra-low capacitance TVS of described integrated form device, the resistivity of described the first conductivity type substrate is 0.005 Ω .cm～0.2 Ω .cm.
Optionally, in the two-way ultra-low capacitance TVS of described integrated form device, the resistivity of described the first conductive type epitaxial layer is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer is 6.0 μ m～14.0 μ m.
Optionally, in the two-way ultra-low capacitance TVS of described integrated form device, the resistivity of described the second conductive type epitaxial layer is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer is 6.0 μ m～12.0 μ m.
Optionally, in the two-way ultra-low capacitance TVS of described integrated form device, described the first conductivity type substrate is held with being, and described the second metal wire is connected with power end.
In the two-way ultra-low capacitance TVS of the integrated form device providing at the utility model, formed two-way ultra-low capacitance TVS device is integrated structure, thereby has avoided the defect in encapsulation, has improved device quality.
Accompanying drawing explanation
Fig. 1 is the forward and reverse I-V curve of two-way ultra-low capacitance TVS device;
Fig. 2 is the two-way ultra-low capacitance TVS of first kind circuit diagram;
Fig. 3 is the two-way ultra-low capacitance TVS of Equations of The Second Kind circuit diagram;
Fig. 4 is the two-way ultra-low capacitance TVS of the 3rd class circuit diagram;
Fig. 5～16th, the generalized section of the formed device of manufacture method of the two-way ultra-low capacitance TVS of the integrated form device of the utility model embodiment.
Embodiment
Below in conjunction with the drawings and specific embodiments, the two-way ultra-low capacitance TVS of the integrated form the utility model proposes device is described in further detail.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of aid illustration the utility model embodiment lucidly.
The present embodiment provides the two-way ultra-low capacitance TVS of a kind of integrated form manufacture method of device, comprising:
S10: the first conductivity type substrate is provided;
S11: form the first conductive type epitaxial layer in described the first conductivity type substrate;
S12: form the second conduction type buried regions in described the first conductive type epitaxial layer;
S13: form the second conductive type epitaxial layer on described the first conductive type epitaxial layer, described the first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
S14: form isolation structure, described isolation structure runs through described the second conductive type epitaxial layer, and in described the second conductive type epitaxial layer, form first area, second area and the 3rd region;
S15: form the first conduction type isolation in described first area, and described the first conduction type isolation is connected with described the first conductivity type substrate;
S16: form the second conductive type of trap in described the 3rd region;
S17: form the second conduction type injection region in described first area, described the second conduction type injection region is connected with described the first conduction type isolation, and described the second conduction type injection region and described the first conduction type isolation form diode Z1;
S18: all form the first conduction type injection region in described second area and the second conductive type of trap, wherein, the first conduction type injection region in described second area and the second conductive type epitaxial layer form diode D1, and the first conduction type injection region in described the second conductive type of trap and the second conductive type of trap form diode Z2;
S19: form the first metal wire and the second metal wire, wherein, described the first metal wire connects described diode Z1 and diode D1, and described the second metal wire connects described diode D1 and diode Z2.
Concrete, please refer to Fig. 5～16, it is the generalized section of the formed device of manufacture method of the two-way ultra-low capacitance TVS of the integrated form device of the utility model embodiment.
As shown in Figure 5, provide the first conductivity type substrate 10, described the first conductivity type substrate 10 can be P type substrate, can be also N-type substrate.In the present embodiment, described the first conduction type is P type, and follow-up the second conduction type relating to is N-type.In other embodiment of the application, can be also that the first conduction type is N-type, the second conduction type is P type.The resistivity of described the first conductivity type substrate 10 is 0.005 Ω .cm～0.2 Ω .cm.
Then, as shown in Figure 6, in described the first conductivity type substrate 10, form the first conductive type epitaxial layer 11, described the first conductive type epitaxial layer 11 is P type epitaxial loayer, and it can generate by chemical vapor deposition method.Preferably, the resistivity of described the first conductive type epitaxial layer 11 is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer 11 is 6.0 μ m～14.0 μ m.For example, the resistivity of described the first conductive type epitaxial layer 11 is 2.2 Ω .cm, 2.4 Ω .cm, 2.7 Ω .cm, 3.0 Ω .cm, 3.3 Ω .cm, 3.5 Ω .cm or 3.7 Ω .cm; The thickness of described the first conductive type epitaxial layer 11 is 6.5 μ m, 7.0 μ m, 7.5 μ m, 8.0 μ m, 9.0 μ m, 10.0 μ m, 11.5 μ m, 12.5 μ m or 13.5 μ m.
As shown in Figure 7, in described the first conductive type epitaxial layer 11, form the second conduction type buried regions 12, described the second conduction type buried regions 12 is n type buried layer.Concrete, can form described the second conduction type buried regions 12 by following technique: in described the first conductive type epitaxial layer 11, inject antimony ion, the implantation dosage of described antimony ion is 2.0E15～6.0E15; Described antimony ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.For example, in described the first conductive type epitaxial layer 11, inject antimony ion, the implantation dosage of described antimony ion is 4.0E15; Described antimony ion is carried out to annealing process, and the temperature of described annealing process is 1225 ℃; The time of described annealing process is 4.0h.
As shown in Figure 8, on described the first conductive type epitaxial layer 11, form the second conductive type epitaxial layer 13, described the second conductive type epitaxial layer 13 is N-type epitaxial loayer, and described the first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 form diode D2.Preferably, the resistivity of described the second conductive type epitaxial layer 13 is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer 13 is 6.0 μ m～12.0 μ m.For example, the resistivity of described the second conductive type epitaxial layer 13 is 26 Ω .cm, 27 Ω .cm, 28 Ω .cm, 29 Ω .cm, 30 Ω .cm, 31 Ω .cm, 32 Ω .cm, 33 Ω .cm or 34 Ω .cm; The thickness of described the second conductive type epitaxial layer 13 is 7.5 μ m, 8.2 μ m, 9.6 μ m, 10.5 μ m or 11.2 μ m.Wherein, the large I of the capacitance of described diode D2 is achieved by adjusting the area of described the first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13, and this application is repeated no more.
Then, as shown in Figure 9, form groove 14, described groove 14 runs through described the second conductive type epitaxial layer 13, and forms first area A, second area B and the 3rd region C in described the second conductive type epitaxial layer 13.Preferably, the degree of depth of described groove 14 is that 10 μ m～20 μ m, cross-sectional width are 1.5 μ m～3.0 μ m.For example, the degree of depth of described groove 14 is 12 μ m, 13 μ m, 15 μ m, 17 μ m or 19 μ m; The cross-sectional width of described groove 14 is 1.7 μ m, 1.9 μ m, 2.2 μ m, 2.5 μ m, 2.7 μ m or 2.9 μ m.
Then, as shown in figure 10, in described groove 14, fill polysilicon, form isolation structure 15, be that described isolation structure 15 runs through described the second conductive type epitaxial layer 13, and form first area A, second area B and the 3rd region C in described the second conductive type epitaxial layer 13.
Then, as shown in figure 11, form the first conduction type isolation 16 in described first area A, described the first conduction type isolation 16 is the isolation of P type, and described the first conduction type isolation 16 is connected with described the first conductivity type substrate 10.Concrete, can form the first conduction type isolation 16 by following technique: B Implanted ion in described first area A, the implantation dosage of described boron ion is 2.0E14～4.5E15; Described boron ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.For example, B Implanted ion in described first area, the implantation dosage of described boron ion is 2.0E15; Described boron ion is carried out to annealing process, and the temperature of described annealing process is 1220 ℃; The time of described annealing process is 2.5h.
As shown in figure 12, in described the 3rd region C, form the second conductive type of trap 17, described the second conductive type of trap 17 is N-type trap.Concrete, described the second conductive type of trap 17 can form by following technique: in described the 3rd region C, inject phosphonium ion, the implantation dosage of described phosphonium ion is 1.0E14～5.0E14.
As shown in figure 13, in described first area A, form the second conduction type injection region 18, described the second 18WeiNXing injection region, conduction type injection region, described the second conduction type injection region 18 is connected with described the first conduction type isolation 16, and described the second conduction type injection region 18 forms diode Z1 with described the first conduction type isolation 16.Concrete, described the second conduction type injection region 18 can form by following technique: in described first area A, inject phosphonium ion, the implantation dosage of described phosphonium ion is 1.0E15～1.0E16; Described phosphonium ion is carried out to annealing process for the first time, and the temperature of described annealing process is for the first time 1100 ℃～1200 ℃; The time of described annealing process is for the first time 10s～20s; Described phosphonium ion is carried out to annealing process for the second time, and the temperature of described annealing process is for the second time 800 ℃～900 ℃; The time of described annealing process is for the second time 30min～60min.The low pressure diode that is 3.3V～7.0V by the formed diode Z1 of above-mentioned technique.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the phosphorus impurities that activates all injections, when guaranteeing to form good ohmic contact, also reduces the reverse leakage current of diode Z1; Annealing process also can be called low temperature boiler tube annealing process for the second time, its objective is junction depth and the puncture voltage of controlling diode Z1, guarantees that puncture voltage is in 3.3V-7.0V left and right.
Then, as shown in figure 14, in described second area B and the second conductive type of trap 17, all form the first conduction type injection region, wherein, the first conduction type injection region 19a in described second area B and the second conductive type epitaxial layer 13 form diode D1, and the first conduction type injection region 19b in described the second conductive type of trap 17 and the second conductive type of trap 17 form diode Z2.Concrete, by following technique, form the first conduction type injection region: equal B Implanted ion in described second area B and the second conductive type of trap 17, the implantation dosage of described boron ion is 1.0E15～1.0E16; Described boron ion is carried out to annealing process for the first time, and the temperature of described annealing process is for the first time 1100 ℃～1200 ℃; The time of described annealing process is for the first time 10s～20s; Described boron ion is carried out to annealing process for the second time, and the temperature of described annealing process is for the second time 800 ℃～900 ℃; The time of described annealing process is for the second time 30min～60min.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the boron impurity that activates all injections, when guaranteeing to form good ohmic contact, also reduces the reverse leakage current of diode Z2; Annealing process also can be called low temperature boiler tube annealing process for the second time; its objective is the junction depth of controlling on the one hand diode D1; guarantee that junction depth, in 0.5 about μ m-1.0 μ m, controls junction depth and the puncture voltage of diode Z2 on the other hand, guarantee that puncture voltage is in 3.3V-7.0V left and right.
Then, as shown in figure 16, form the first metal wire 21a and the second metal wire 21b, wherein, described the first metal wire 21a connects described diode Z1 and diode D1, and described the second metal wire 21b connects described diode D1 and diode Z2.Concrete, can on described the second conductive type epitaxial layer 13, form dielectric layer 20 with reference to Figure 15, described dielectric layer 20 exposes diode Z1, diode D1 and diode Z2; Then, can, with reference to Figure 16, by deposited metal, form the first metal wire 21a and the second metal wire 21b.
In the present embodiment, described the first conductivity type substrate 10 is held with being, and described the second metal wire 21b is connected with power end.The first conductivity type substrate 10 is directly as the electrode of ground connection GND, thereby do not need to draw ground connection GND electrode, so not only can dwindle the size of chip, meet the more encapsulation of small size, while encapsulating in addition, the first conductivity type substrate 10 is directly drawn as GND electrode, can reduce by 1 wires, greatly reduce packaging cost.
Please continue to refer to Figure 16, the manufacture method by the two-way ultra-low capacitance TVS of above-mentioned integrated form device has formed the two-way ultra-low capacitance TVS of following integrated form device, specifically comprises:
The first conductivity type substrate 10;
Be formed at the first conductive type epitaxial layer 11 in described the first conductivity type substrate 10;
Be formed at the second conduction type buried regions 12 in described the first conductive type epitaxial layer 11;
Be formed at the second conductive type epitaxial layer 13 on described the first conductive type epitaxial layer 11, described the first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 form diode D2;
Be formed at the first conduction type isolation 16 in described first area A, described the first conduction type isolation 16 is connected with described the first conductivity type substrate 10;
Be formed at the second conductive type of trap 17 in described the 3rd region C;
Be formed at the second conduction type injection region 18 in described first area A, described the second conduction type injection region 18 is connected with described the first conduction type isolation 16, and described the second conduction type injection region 18 forms diode Z1 with described the first conduction type isolation 16;
Be formed at the first conduction type injection region in described second area B and the second conductive type of trap 17, wherein, the first conduction type injection region 19a in described second area B and the second conductive type epitaxial layer 13 form diode D1, and the first conduction type injection region 19b in described the second conductive type of trap 17 and the second conductive type of trap 17 form diode Z2; And
The the first metal wire 21a that connects described diode Z1 and diode D1, connects the second metal wire 21b of described diode D1 and diode Z2.
In the integrated form two-way ultra-low capacitance TVS device and manufacture method thereof providing at the present embodiment, formed two-way ultra-low capacitance TVS device is integrated structure, thereby has avoided the defect in encapsulation, has improved device quality.
Foregoing description is only the description to the utility model preferred embodiment; the not any restriction to the utility model scope; any change, modification that the those of ordinary skill in the utility model field is done according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (6)
1. the two-way ultra-low capacitance TVS of an integrated form device, is characterized in that, comprising:
The first conductivity type substrate;
Be formed at the first conductive type epitaxial layer in described the first conductivity type substrate;
Be formed at the second conduction type buried regions in described the first conductive type epitaxial layer;
Be formed at the second conductive type epitaxial layer on described the first conductive type epitaxial layer, described the first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Isolation structure, described isolation structure runs through described the second conductive type epitaxial layer, and in described the second conductive type epitaxial layer, formed first area, second area and the 3rd region;
Be formed at the first conduction type isolation in described first area, described the first conduction type isolation is connected with described the first conductivity type substrate;
Be formed at the second conductive type of trap in described the 3rd region;
Be formed at the second conduction type injection region in described first area, described the second conduction type injection region is connected with described the first conduction type isolation, and described the second conduction type injection region and described the first conduction type isolation form diode Z1;
Be formed at the first conduction type injection region in described second area and the second conductive type of trap, wherein, the first conduction type injection region in described second area and the second conductive type epitaxial layer form diode D1, and the first conduction type injection region in described the second conductive type of trap and the second conductive type of trap form diode Z2; And
The first metal wire that connects described diode Z1 and diode D1, connects the second metal wire of described diode D1 and diode Z2.
2. the two-way ultra-low capacitance TVS of integrated form as claimed in claim 1 device, is characterized in that, described the first conduction type is that P type, described the second conduction type are N-type; Or described the first conduction type is that N-type, described the second conduction type are P type.
3. the two-way ultra-low capacitance TVS of integrated form as claimed in claim 1 or 2 device, is characterized in that, the resistivity of described the first conductivity type substrate is 0.005 Ω .cm～0.2 Ω .cm.
4. the two-way ultra-low capacitance TVS of integrated form as claimed in claim 1 or 2 device, is characterized in that, the resistivity of described the first conductive type epitaxial layer is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer is 6.0 μ m～14.0 μ m.
5. the two-way ultra-low capacitance TVS of integrated form as claimed in claim 1 or 2 device, is characterized in that, the resistivity of described the second conductive type epitaxial layer is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer is 6.0 μ m～12.0 μ m.
6. the two-way ultra-low capacitance TVS of integrated form as claimed in claim 1 or 2 device, is characterized in that, described the first conductivity type substrate is held with being, and described the second metal wire is connected with power end.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185783A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN105185782A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN107301991A (en) * | 2016-04-14 | 2017-10-27 | 力祥半导体股份有限公司 | Multi-channel transient voltage suppressor |
-
2013
- 2013-09-16 CN CN201320574868.3U patent/CN203445119U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185783A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN105185782A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN105185782B (en) * | 2015-08-20 | 2018-05-11 | 北京燕东微电子有限公司 | Capacitive diode assembly and its manufacture method |
| CN105185783B (en) * | 2015-08-20 | 2018-08-24 | 北京燕东微电子有限公司 | Capacitive diode assembly and its manufacturing method |
| CN107301991A (en) * | 2016-04-14 | 2017-10-27 | 力祥半导体股份有限公司 | Multi-channel transient voltage suppressor |
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