CN203434601U - Phase shift full bridge over-current self-protection circuit based on CPLD - Google Patents

Abstract

The utility model discloses a phase shift full bridge over-current self-protection circuit based on a CPLD, comprising a DSP controller, a CPLD programmable controller and a current sampling and comparison circuit. The CPLD programmable controller generates four ways of complementary PWM signals with dead time; five I/O ports of the CPLD programmable controller are respectively in connection with the output of four ways of PWM signals outputted by the DSP controller and the current sampling and comparison circuit, and the CPLD programmable controller can output four ways of complementary PWM signals with overcurrent protection and dead time through four I/O ports. The period self-protection circuit is simple and practical, can realize overcurrent fault protection with least PWM signals to reduce design cost, and meanwhile can eliminate transformer magnetic biasing caused by continuous fault protection.

Description

A kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD

Technical field

The utility model relates to phase-shifting full-bridge switch power technology field, is specifically related to a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD.

Background technology

Phase whole-bridging circuit, as the soft switch circuit of a comparative maturity, is usually used in middle large power, electrically source circuit.The conventional IGBT of full-bridge circuit is as switching tube, when there is over current fault, IGBT can bear moment overcurrent general no more than 10us of time, if only process over current fault by dsp controller, certainly will burn IGBT.Drive IGBT Si road PWM generally by dsp controller, to be produced, the 4 road pwm signals of exporting due to dsp controller are complementary between two, so when there is over current fault, cannot make IGBT all turn-off simultaneously, cannot meet real work requirement simultaneously.Moreover conventional overcurrent period protection can cause voltage bias phenomenon at circuit working during at continuous over current fault, affect device lifetime.

Utility model content

The deficiency existing for prior art; the utility model discloses a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD; when there is over current fault; the complete shut-down that can realize switching tube with minimum pwm signal breaks and eliminates the bias phenomenon that transformer produces when there is continuous over current fault; improve dsp controller utilance; cost-saving, this control method is reliable, circuit simple, be easy to realization.

The utility model is for achieving the above object, and the technical scheme adopting is as follows:

A phase-shifting full-bridge overcurrent self-protection circuit of CPLD, comprising: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit thereof; Described dsp controller produces 4 tunnels with Dead Time and complementary pwm signal between two: the first input pwm signal, the second input pwm signal, the 3rd input pwm signal, the 4th input pwm signal; 5 I/O mouths of described CPLD programmable logic device are connected with the output of 4 road pwm signals, current sample and the comparison circuit thereof of dsp controller output respectively, and export that 4 tunnels have overcurrent protection and with Dead Time and the pwm signal of complementation between two by its 4 I/O mouths: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal.

The first described input pwm signal, the second input pwm signal, the 3rd input pwm signal (PWM3), the 4th input pwm signal form 4 road phase-shifting full-bridge pwm signals, wherein the second input pwm signal is oppositely obtained by the first input pwm signal, and the 4th input pwm signal is oppositely obtained by the 3rd input pwm signal (PWM3).

As preferably, described dsp processor is selected Texas Instruments's 2000 series DSP controllers.

As preferably, described CPLD Programmable Logic Controller is selected the MAX7000 series CPLD Programmable Logic Controller of altera corp.

Described current sample and comparison circuit thereof, comprising: Hall current sensor P, 16 resistance R ₁-R ₁₆, 7 capacitor C ₁-C ₇, 4 diode D ₁-D ₄with 2 operational amplifier U ₁and U ₂; The current signal of described current sample and comparison circuit sampling thereof is the electric current that flows through IGBT, and when overcurrent appears in IGBT, the output of current sample and comparison circuit 1 thereof is output as low level; When IGBT electric current is normal, the output of current sample and comparison circuit 1 thereof is output as high level on the contrary.

Described a kind of phase-shifting full-bridge overcurrent self-protection circuit's based on CPLD control method is: when over current fault appears in circuit; the output of current sample and comparison circuit 1 thereof is output as low level; when CPLD programmable logic device detects this low level, export immediately 4 roads and be low level pwm signal: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal; thereby turn-off 4 IGBT of full-bridge circuit, and the state of latch fault first input pwm signal while occurring.

When the electric current of IGBT recovers normal, if the first input pwm signal that while there is over current fault, CPLD programmable logic device latchs is low level, when the first input pwm signal is high level, CPLD programmable logic device is exported the 4 normal pwm signals in road: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal, now the first output pwm signal is the same with the first input pwm signal, the second output pwm signal is the same with the second input pwm signal, the 3rd output pwm signal is the same with the 3rd input pwm signal, the 4th output pwm signal is the same with the 4th input pwm signal, and if the first input pwm signal that CPLD programmable logic device latchs while breaking down is high level, when the first input pwm signal is low level, CPLD programmable logic device is exported the 4 normal pwm signals in road: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal, now the first output pwm signal is the same with the first input pwm signal, the second output pwm signal is the same with the second input pwm signal, the 3rd output pwm signal is the same with the 3rd input pwm signal, the 4th output pwm signal is the same with the 4th input pwm signal, avoid over current fault to recur when first cycle, IGBT always closes in first cycle, thereby the asymmetric electric current of eliminating transformer because only occurring that half-wave current produces, eliminating transformer bias phenomenon.

Compare with prior art scheme, the utlity model has following advantage and technique effect:

1, circuit is simple and easy to realize, and when over current fault appears in circuit, four IGBT can turn-off simultaneously simultaneously;

2, by phase-shifting full-bridge overcurrent self-shield control method, make circuit working at self-shield state, disappear except when IGBT caused transformer bias phenomenon while there is continuous over current fault;

3, with minimum pwm signal, realize the self-shield of full-bridge circuit overcurrent, be conducive to multi-machine parallel connection and control, cost-saving.

Accompanying drawing explanation

Fig. 1 is a kind of phase-shifting full-bridge overcurrent self-protection circuit circuit diagram based on CPLD of execution mode;

Fig. 2 is current sample and the comparison circuit figure thereof of execution mode.

Fig. 3 is the logical circuitry that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD of execution mode is controlled;

Fig. 4 is the active crystal oscillating circuit figure of execution mode;

Fig. 5 is the sequential logic figure that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD of execution mode is controlled.

Embodiment

Below in conjunction with accompanying drawing, enforcement of the present utility model is further described in detail.

As shown in Figure 1, a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD, figure comprises: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit 1 thereof; Described dsp controller produces 4 tunnels with Dead Time and the pwm signal of complementation: the first input pwm signal PWM1, second inputs pwm signal PWM2, the 3rd input pwm signal PWM3, the 4th inputs pwm signal PWM4 between two; 5 I/O mouths of described CPLD programmable logic device are connected with the output of 4 road pwm signals, current sample and the comparison circuit thereof of dsp controller output respectively, and export that 4 tunnels have overcurrent protection and with Dead Time and the pwm signal of complementation between two by its 4 I/O mouths: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD.

The first described input pwm signal PWM1, the second input pwm signal PWM2, the 3rd input pwm signal PWM3, the 4th input pwm signal PWM4 form 4 road phase-shifting full-bridge pwm signals, wherein the second input pwm signal PWM2 is oppositely obtained by the first input pwm signal PWM1, and the 4th input pwm signal PWM4 is oppositely obtained by the 3rd input pwm signal PWM3.

As preferably, described dsp processor is selected Texas Instruments's 2000 series DSP controllers.

As preferably, described CPLD Programmable Logic Controller is selected the MAX7000 series CPLD Programmable Logic Controller of altera corp.

As shown in Figure 2, described current sample and comparison circuit 1 thereof, figure comprises: Hall current sensor P, 16 resistance R ₁-R ₁₆, 7 capacitor C ₁-C ₇, 4 diode D ₁-D ₄with 2 operational amplifier U ₁and U ₂;

Described Hall current sensor P adopts CSM300LT series Hall current sensor, when flowing through the electric current of IGBT, is timing, and Hall current sensor CSM300LT exports positive current, the first resistance R ₁upper voltage u ₁for positive voltage signal u ₁₊, the second diode D ₂conducting, the first operational amplifier u ₁form anti-phase scale operation circuit, it is output as

$u_2=-\frac{R_4}{R_2}{u}_{1+}---\left(1\right)$

When the electric current that flows through IGBT is when negative, Hall current sensor output negative current, the first resistance R ₁upper voltage u ₁for negative voltage signal u _1-, the first diode D ₁conducting, the first operational amplifier u ₁form voltage follower, now the first operational amplifier u ₁output is because of the second diode D ₂end and can not input late-class circuit.

By the second amplifier u ₂the anti-phase summation operation circuit forming is by u1 and u2 summation, and its output voltage is

$u_o=-R_8(\frac{u_1}{{\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="130730104356.png"\; state="\{\{state\}\}">R</figure-callout>}}_5}+\frac{u_2}{R_6})---\left(2\right)$

u ₁＝u ₁₊+u _1- （3）

Formula (1) and (3) substitution formula (2) are had

$u_o=-\frac{R_8}{R_5}{u}_{1-}+(\frac{R_4{R}_8}{R_2{R}_6}-\frac{R_8}{R_5})u_{1+}---\left(4\right)$

Positive 12V voltage is through the 12 resistance R ₁₂, the 13 resistance R ₁₃dividing potential drop obtains u _o*and and u _owith

relatively, wherein

$u_{o^{*}}=\frac{12*R_{12}}{R_{12}+R_{13}}---\left(5\right)$

U when overcurrent appears in IGBT _obe greater than

, the first comparator U now ₃output low level, the output VI of the output of current sample and comparison circuit 1 thereof is low level; Contrary when IGBT electric current is normal u _obe less than

, the first comparator U ₃output high level, the output VI of the output of current sample and comparison circuit 1 thereof is high level.

Control method for above-mentioned a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD is: when over current fault appears in circuit; the output VI of the output of current sample and comparison circuit 1 thereof is low level; when CPLD programmable logic device detects this low level, export immediately 4 roads and be low level pwm signal: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD; thereby turn-off 4 IGBT of full-bridge circuit, and the state of latch fault first input pwm signal PWM1 while occurring.

When the electric current of IGBT recovers normal, if the first input pwm signal PWM1 that while there is over current fault, CPLD programmable logic device latchs is low level, when the first input pwm signal PWM1 is high level, CPLD programmable logic device is exported the 4 normal pwm signals in road: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD, now the first output pwm signal PWMA is the same with the first input pwm signal PWM1, the second output pwm signal PWMB is the same with the second input pwm signal PWM2, the 3rd output pwm signal PWMC is the same with the 3rd input pwm signal PWM3, the 4th output pwm signal PWMD is the same with the 4th input pwm signal PWM4, and if the first input pwm signal PWM1 that CPLD programmable logic device latchs while breaking down is high level, when the first input pwm signal PWM1 is low level, CPLD programmable logic device is exported the 4 normal pwm signals in road: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD, now the first output pwm signal PWMA is the same with the first input pwm signal PWM1, the second output pwm signal PWMB is the same with the second input pwm signal PWM2, the 3rd output pwm signal PWMC is the same with the 3rd input pwm signal PWM3, the 4th output pwm signal PWMD is the same with the 4th input pwm signal PWM4, avoid over current fault to recur when first cycle, IGBT always closes in first cycle, thereby the asymmetric electric current of eliminating transformer because only occurring that half-wave current produces, eliminating transformer bias phenomenon.

Fig. 3 is the logical circuitry that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD is controlled, figure comprises: 4 PWM outputs of dsp controller, current sample and comparison circuit 1 thereof, active crystal oscillating circuit 2, the first trailing edge triggers d type flip flop D1, the second trailing edge triggers d type flip flop D2, the first dual input or door OR1, the second dual input or door OR2, the first not gate NOT1, the first dual input and door AND1, the second dual input and door AND2, the 3rd dual input and door AND3, the 4th three value and gate AND4, the 5th dual input and door AND5, the 6th dual input and door AND6, the 7th dual input and door AND7, the 8th dual input and door AND8, described 4 PWM outputs of dsp controller are: the first input pwm signal output 3, the second input pwm signal output 4, the 3rd input pwm signal output 5, the 4th input pwm signal output 6, the D input that described the first trailing edge triggers d type flip flop D1 is connected with the first input pwm signal output 3, and CLK input is connected with the output of the second dual input or door OR2, the output of described the first not gate NOT1 is connected with the first input pwm signal output 3, described the first dual input is connected with the output of the first not gate NOT1 with the first input end of door AND1, and the second input is connected with the output Q that the first trailing edge triggers d type flip flop D1, described the second dual input is disconnected with the first input end of door AND2 and the output Q of the first trailing edge triggering d type flip flop D1, and the second input and the first input pwm signal output 3 are connected, the first input end of described the first dual input or door OR1 is connected with the output of door AND1 with the first dual input, and the second input is connected with the output of door AND2 with the second dual input, the D input that described the second trailing edge triggers d type flip flop D2 is connected with the output of the second dual input or door OR2, and CLK input is connected with the output CLKIN of active crystal oscillating circuit 2, described the 3rd dual input is connected with the output VI of the output of current sample and comparison circuit 1 thereof with the first input end of door AND3, and the second input is connected with the output Q that the second trailing edge triggers d type flip flop D2, the output Q of the first input end of described the 4th three value and gate AND4 and the second trailing edge triggering d type flip flop D2 is disconnected, the second input is connected with the output VI of the output of current sample and comparison circuit 1 thereof, and the 3rd input is connected with the output of the first dual input or door OR1, the first input end of the second described dual input or door OR2 is connected with the output of door AND3 with the 3rd dual input, and the second input is connected with the output of the 4th three value and gate AND4, the 5th described dual input is connected with the first input pwm signal output 3, the second input pwm signal output 4, the 3rd input pwm signal output 5, the 4th input pwm signal output 6 respectively with the first input end of door AND8 with door AND7, the 8th dual input with door AND6, the 7th dual input with door AND5, the 6th dual input, described the 5th dual input all connects together with the second input of door AND8 with door AND7, the 8th dual input, and is connected with the second dual input or door OR2 output with door AND6, the 7th dual input with door AND5, the 6th dual input, the output of described the 5th dual input and an AND5, the 6th dual input and a door AND6, the 7th dual input and an AND7, the 8th dual input and an AND8 is for the switch of 4 switching tubes on control circuit two brachium pontis.

As shown in Figure 4, described active crystal oscillating circuit 2, comprising: active crystal oscillator OSC, the 17 resistance R ₁₇, 2 electric capacity (C ₈and C ₉), the first inductance L ₁; The first described inductance L ₁a termination positive 3.3V power supply, the other end and the 8th capacitor C ₈with the 9th capacitor C ₉one end connect, then be connected with the vdd terminal of active crystal oscillator OSC; The 8th described capacitor C ₈with the 9th capacitor C ₉other end ground connection all; The 17 described resistance R ₁₇the OUT end of one end and active crystal oscillator OSC be connected, the other end is the output CLKIN of active crystal oscillating circuit 2; The GND end ground connection of described active crystal oscillator OSC, OE end is unsettled.

Described a kind of control method that realizes the logical circuit that the self-shield of phase-shifting full-bridge overcurrent controls based on CPLD is:

When overcurrent appears in IGBT, comprise the steps:

(S1) output (VI) of the output of current sample and comparison circuit thereof (1) is low level, makes the 3rd dual input and door (AND3), the 4th three value and gate (AND4) output low level;

(S2) because the 3rd dual input and the output of door (AND3), the 4th three value and gate (AND4) are low level, so the output (Y) of the second dual input or door (OR2) is low level;

(S3) output (Y) of the second dual input or door (OR2) is low level, make the second trailing edge trigger d type flip flop (D2) output Q and Q non-output low level and high level respectively, the output (Y*) of the second trailing edge triggering d type flip flop (D2) output Q is low level; Make the 5th dual input and door (AND5), the 6th dual input and door (AND6), the 7th dual input and door (AND7), the 8th dual input and door (AND8) output low level, 4 IGBT in breaking circuit simultaneously;

(S4) output (Y) of now the second dual input or door (OR2) drops to low level by high level, and then trigger the first trailing edge and trigger d type flip flop (D1), the first trailing edge triggers the state that d type flip flop (D1) is preserved the first input pwm signal (PWM1), i.e. the value of the first input pwm signal (PWM1) when the output (PWM1*) of the output Q of the first trailing edge triggering d type flip flop (D1) equals overcurrent generation;

When flowing through the electric current of IGBT and recover normal, comprise the steps:

If 1. now output Q and the non-output of Q of the first trailing edge triggering d type flip flop (D1) are respectively low level and high level, while representing overcurrent occurs, the first input pwm signal (PWM1) is in low level, when the first input pwm signal (PWM1) is high level, non-output (PWM1*) and the first input pwm signal (PWM1) of output Q that triggers d type flip flop (D1) due to the first trailing edge is high level, makes the second dual input and door (AND2) output high level;

2. the second dual input and door (AND2) output high level, makes the first dual input or door (OR1) output high level;

3. the output (VI) due to the first dual input or door, the second output Q not sum current sample of trailing edge triggering d type flip flop (D2) and the output of comparison circuit (1) thereof is high level, makes the 4th three value and gate (AND4) output high level;

4. the 4th three value and gate (AND4) output high level, makes the output of the second dual input or door (OR2) revert to high level ，Ze tetra-road PWM and normally exports;

5. output Q and the non-output of Q of the first trailing edge triggering d type flip flop (D1) are respectively high level and low level, while representing overcurrent occurs, the first input pwm signal (PWM1) is in high level, when the first input pwm signal (PWM1) is low level, because the first input pwm signal (PWM1) is low level, make the first not gate (NOT1) output high level;

6. the output of the output Q of the first not gate (NOT1) and the first trailing edge triggering d type flip flop (D1) is high level, makes the first dual input and door (AND1) output high level;

7. due to the first dual input and door (AND1) output high level, make the first dual input or door (OR1) output high level;

8. the output (VI) due to the first dual input or door (OR1), the second output Q not sum current sample of trailing edge triggering d type flip flop (D2) and the output of comparison circuit (1) thereof is high level, the 4th three value and gate (AND4) output high level;

9. the 4th three value and gate (AND4) output high level, makes the output of the second dual input or door (OR2) revert to high level ，Ze tetra-road PWM and normally exports.

Fig. 5 is the sequential logic figure that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD of execution mode is controlled, when t1, the output VI of the output of the first input pwm signal PWM1 and current sample and comparison circuit 1 thereof is low level, the output Y of now the second dual input or door OR2 becomes low level, during to t2, the output VI of the output of the first input pwm signal PWM1 and current sample and comparison circuit 1 thereof all becomes high level, and the output Y of the second dual input or door OR2 recovers high level; When t3, the first input pwm signal PWM1 is that the output VI of the output of high level and current sample and comparison circuit 1 thereof is low level, the output Y of now the second dual input or door OR2 becomes low level, during to t4, to become the output VI of the output of low level and current sample and comparison circuit 1 thereof be high level to the first input pwm signal PWM1, the output Y of the second dual input or door OR2 recovers high level, Shi Si road pwm signal is normally exported, thereby can eliminating transformer bias phenomenon.

Table 1 is the truth table that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD of execution mode is controlled, in table, state Z1 represents that the output VI of the output of current sample now and comparison circuit 1 thereof is low level, and the first input pwm signal PWM1 is that high level or the output Y of low level the second dual input or door OR2 are low level; State Z2 represents that the output VI of output of current sample now and comparison circuit 1 thereof and the output Y* that the second trailing edge triggers d type flip flop D2 output Q be high level, and the first input pwm signal PWM1 is that high level or the output Y of low level the second dual input or door OR2 are high level; State Z3 represents that the output VI of the output of current sample now and comparison circuit 1 thereof is that high level, the second trailing edge trigger the output Y* of d type flip flop D2 output Q and the non-output PWM1* of output Q that the first trailing edge triggers d type flip flop D1 is low level, now only have when the first input pwm signal PWM1 is high level, the output Y of the second dual input or door OR2 is just high level; State Z4 represents that the output VI of output of current sample now and comparison circuit 1 thereof and the output Y* that the non-output PWM1* of output Q that the first trailing edge triggers d type flip flop D1 be high level, the second trailing edge triggering d type flip flop D2 output Q are low level, now only have when the first input pwm signal PWM1 is low level, the output Y of the second dual input or door OR2 is just high level.

Table 1

Those skilled in the art can make various modifications to this specific embodiment or supplement or adopt similar mode to substitute under the prerequisite without prejudice to principle of the present utility model and essence, but these changes all fall into protection range of the present utility model.Therefore the utility model technical scope is not limited to above-described embodiment.

Claims (5)

1. the phase-shifting full-bridge overcurrent self-protection circuit based on CPLD, is characterized in that comprising: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit (1) thereof; Described dsp controller produces 4 tunnels with Dead Time and complementary pwm signal between two: the first input pwm signal (PWM1), the second input pwm signal (PWM2), the 3rd input pwm signal (PWM3), the 4th input pwm signal (PWM4); 5 I/O mouths of described CPLD programmable logic device are connected with the output of 4 road pwm signals, current sample and the comparison circuit thereof of dsp controller output respectively, and export that 4 tunnels have overcurrent protection and with Dead Time and the pwm signal of complementation between two by its 4 I/O mouths: the first output pwm signal (PWMA), the second output pwm signal (PWMB), the 3rd output pwm signal (PWMC), the 4th output pwm signal (PWMD).

2. a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD according to claim 1, is characterized in that described dsp processor adopts Texas Instruments's 2000 series DSP controllers.

3. a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD according to claim 1, is characterized in that described CPLD Programmable Logic Controller adopts the MAX7000 series CPLD Programmable Logic Controller of altera corp.

4. a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD according to claim 1; it is characterized in that the first described input pwm signal (PWM1), the second input pwm signal (PWM2), the 3rd input pwm signal (PWM3), the 4th input pwm signal (PWM4) form 4 road phase-shifting full-bridge pwm signals; wherein the second input pwm signal (PWM2) is oppositely obtained by the first input pwm signal (PWM1), and the 4th input pwm signal (PWM4) is oppositely obtained by the 3rd input pwm signal (PWM3).

5. a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD according to claim 1, is characterized in that described current sample and comparison circuit (1) thereof comprising: Hall current sensor P, 16 resistance (R ₁-R ₁₆), 7 electric capacity (C ₁-C ₇), 4 diode (D ₁-D ₄) and 2 operational amplifier (U ₁, U ₂); The current signal of described current sample and comparison circuit thereof (1) sampling is the electric current that flows through IGBT, and when overcurrent appears in IGBT, the output (VI) of the output of current sample and comparison circuit thereof (1) is low level; When IGBT electric current is normal, the output (VI) of the output of current sample and comparison circuit (1) thereof is high level on the contrary.

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