CN203416315U - Multipoint transmission equipment system based on SHDSL - Google Patents
Multipoint transmission equipment system based on SHDSL Download PDFInfo
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- CN203416315U CN203416315U CN201320362727.5U CN201320362727U CN203416315U CN 203416315 U CN203416315 U CN 203416315U CN 201320362727 U CN201320362727 U CN 201320362727U CN 203416315 U CN203416315 U CN 203416315U
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Abstract
The utility model relates to a multipoint transmission equipment system based on SHDSL. The structure of the equipment system employs a chassis plugboard type design, and the equipment system comprises a multipoint transmission equipment mother board, a multipoint transmission equipment main control plugboard, a multipoint transmission equipment line plugboard and a multipoint transmission equipment network plugboard; the multipoint transmission equipment main control plugboard, the multipoint transmission equipment line plugboard and the multipoint transmission equipment network plugboard are correspondingly inserted onto the multipoint transmission equipment mother board, wherein each line plugboard achieves functions of two-way twisted pairs and four-way telephones. The multipoint transmission equipment system based on the SHDSL is advantageous in that a multimedia communication network with a radiation radius of tens of kilometers can be established by employing a central office device as the center and provided with a plurality of remote devices and repeating devices; the communication bandwidth of each twisted pair is adjustable from 128 kbps to 8 Mbps; integrated services such as broadband data (data such as videos, files and faxes) and voices can be transmitted simultaneously; and the transmission distance can reach 10 kilometers.
Description
Technical field
The utility model is
a SHDSL multicast communication device systems, it istake twisted-pair feeder as transport vehicle for one, and the integrated digital that integrates packet switching and circuit switching of using up-to-date SHDSL transmission technology to form is communicated by letter
device systems.
Background technology
SHDSL (Single-pair High-speed Digital Subscriber Line, single to line high-speed digital subscriber line, can carry TDM (Time Division Multiplex, time division multiplexing), ATM (Asynchronous Transfer Mode, asynchronous transfer mode), IP (Internet Protocol, Internet Interconnection agreement) or mixed transport, use TC-PAM (Trellis Coded Pulse Amplitude Modulation trellis coded pulse amplitude modulation) coding techniques, circuit antijamming capability is stronger simultaneously, and circuit sending power consumption is lower.Existing equipment exists that transmission range is near, transport service is narrower, stability is not high.
Summary of the invention
The utility model proposes
a kind of device systems based on SHDSL multicast communication, its objective is control information, voice, data are carried out to transfer of data by twisted-pair feeder to there is antijamming capability strong, system communication distance.
Technical solution of the present utility model: based on SHDSL multicast communication device systems, it is characterized in that cabinet board plug type structure, comprise multicast communication equipment motherboard, multicast communication equipment master control plate, multicast communication device line plate and a multicast communication device network plate; Described a multicast communication equipment master control plate, multicast communication device line plate and multicast communication device network plate correspondence patch on multicast communication equipment motherboard, and wherein every block of circuit plate is realized two-way twisted-pair feeder ,Si road telephony feature.
Advantage of the present utility model: centered by local side apparatus, be equipped with a plurality of remote equipments and repeating equipment, can set up into the multimedia communication network of tens of kilometers of radiation radius.Every twisted-pair communication bandwidth is that 128kbps is adjustable to 8Mbps.Can transmit the integrated services such as wideband data (data such as video, file, fax), speech, transmission range can reach 10 kilometers simultaneously.
Accompanying drawing explanation
attachedfig. 1 is the structured flowchart based on SHDSL multicast communication device systems;
Accompanying drawing 2 is multicast communication equipment motherboard schematic diagrames;
Accompanying drawing 3 is the control unit schematic diagrames on multicast communication equipment master control plate;
Accompanying drawing 4 is the line control unit schematic diagrames on multicast communication device line plate;
Accompanying drawing 5 is multicast communication device network plate figure.
Embodiment
Based on SHDSL multicast communication device systems, it is characterized in that adopting the design of cabinet board plug type, comprise multicast communication equipment motherboard, multicast communication equipment master control plate, multicast communication device line plate and a multicast communication device network plate; Described a multicast communication equipment master control plate, multicast communication device line plate and multicast communication device network plate correspondence patch on multicast communication equipment motherboard, and wherein every block of circuit plate is realized two-way twisted-pair feeder ,Si road telephony feature.
Contrast accompanying drawing 1, based on SHDSL multicast communication device systems, its structure comprises 5 wiring boards, network board, master board, 5 wiring boards wherein, every wiring board has 2 road SHDSL interfaces, 4 road telephony interfaces, 2 road Ethernet interfaces, modulation-demodulation circuit, each road SHDSL interface docks with a remote equipment, the Ethernet access network plate of 5 wiring boards, this network board Zhong mono-road Ethernet is received external management interface, another road Ethernet in network board is received master board, this master board You Er road signal and corresponding joining of control circuit in 5 wiring boards, master board also has a road signal and display interface to join, external management interface access exterior PC, the upper operation of PC has office terminal software, software configures the bandwidth on each road and shows the line status of every SHDSL.
Modulation-demodulation circuit completes the SHDSL protocol data that far-end is come by Double-strand transmission and carries out demodulation, after demodulation, by Ethernet interface or TDM mouth, outputs to local terminal ethernet device or TDM equipment.By local terminal being modulated into SHDSL agreement and going out by Double-strand transmission of network interface or TDM interface data too, modulation-demodulation circuit mainly consists of 2 PEF24628 simultaneously.
Described network board comprises control circuit, switched circuit, and wherein control circuit is mainly comprised of LPC1768 ARM chip, and switched circuit mainly consists of two exchange chip 88E6095 cascade; Wherein LPC1768 has been used for the initial configuration of two 88E6095 and state-detection, and exchange chip 88E6095 mainly completes the function of exchange of ten road Ethernets.
Described master board comprises acoustic code circuit, logical circuit, master processor, wherein acoustic code main circuit will complete the encoding and decoding speech function of 64K, master processor is connected by HPI mouth with the DSP of acoustic code circuit, by HPI, is realized the program of DSP is downloaded and data interaction; Logical circuit mainly completes the mutual of PCM speech on the DSP of acoustic code circuit and wiring board.
Described master processor is selected FREESCALE communication processor MPC8280, operation Vxworks operating system, it mainly completes the functions such as configuration to each plate, control, monitoring, coordinate the terminal software on plug-in computer, realization, to the management of local side apparatus and monitoring function, can also transmit the remote equipment of appointment and the duties speech between office terminal in real time.Communicating by letter between master processor and office terminal completes via ethernet switching module.
Described acoustic code main circuit will consist of a chip TMS320VC5509 DSP, mainly complete on plug-in computer the PCM encoding and decoding speech function of the 64K of telephone booth on voice and wiring board, by being connected with master processor MPC8280, the FPGA by logical circuit is connected with the interface of wiring board with the speech interface on plug-in computer.
Described logical circuit mainly consists of a slice EP2C8Q208I8 fpga chip, mainly completes some states control functions on the mutual and master control borad of PCM speech on the DSP of acoustic code circuit and wiring board.
Described ethernet switching module is realized the link layer function of exchange of each circuit plate and master processor and external network, it is formed by two 8 port one 00M exchange chip cascades, the actual port using is 13 (two of each circuit plates, one of master processor, two of external interfaces).
The SHDSL signal of two covered wires of described each SHDSL line function resume module, its core is two SHDSL chips, take circuit receive direction as example, grouping information is wherein delivered to Ethernet exchanging matrix through ethernet physical layer interface chip by base plate, three channel time slot information Zhong mono-tunnel duties words are delivered to the master processor of master control borad by TDM bus by the clock request of master control borad by programming device, two-way telephone signal is delivered to telephone wire via telephony interface chip (SLIC/CO is configurable).In TDM bus between line function module and main control module, except the PCM speech that contains above-mentioned duties words, every plate also arranges a road HDLC control information, is mainly used in the configuration information of transmission lines plate and line status etc.
contrast accompanying drawing 2,on multicast communication equipment motherboard, comprise one with the network plate plate position of the master control plate plate position of the corresponding setting of multicast communication master control plate, and the corresponding setting of multipoint transport network plate and with the polylith circuit plate plate position of the corresponding setting of multicast communication polylith circuit plate.Motherboard carrying polylith circuit plate, a master control plate, a network plate, for signal path and power path are provided between various plates, and provide the signaling transfer point of plate to panel line-outgoing.
contrast accompanying drawing 3,the control unit being furnished with on multicast communication equipment master control plate, its structure is corresponding the joining of signal input/output terminal of first signal input/output end with the RAM of MPC8280 PowerPC;
The secondary signal input/output end of MPC8280 PowerPC and corresponding the joining of signal input/output terminal of FLASH;
The 3rd signal input/output end of MPC8280 PowerPC and corresponding the joining of first signal input/output terminal of EP2C8Q208I8 FPGA;
The 4th signal input/output end of MPC8280 PowerPC with corresponding joining of first signal input/output terminal of the first ethernet PHY chip; Corresponding the joining of first signal input/output end of the secondary signal input/output terminal of the first ethernet PHY chip and A transformer; The secondary signal input/output termination Ethernet of A transformer;
The 5th signal input/output end of MPC8280 PowerPC and corresponding the joining of first signal input/output terminal of TMS320VC5509 DSP;
The 6th signal input/output termination HDLC of MPC8280 PowerPC;
Corresponding the joining of secondary signal input/output end of the secondary signal input/output terminal of EP2C8Q208I8 FPGA and TMS320VC5509 DSP;
Corresponding the joining of signal input/output end of the 3rd signal input/output terminal of EP2C8Q208I8 FPGA and the first digital junction PHY chip; Corresponding the joining of first signal input of the signal output part of the first digital junction PHY chip and B transformer; The signal I/O termination E1 of B transformer;
The 3rd signal input/output termination PCM speech of TMS320VC5509 DSP;
The master control borad course of work is as follows:
1 control unit of master control board initialization, completes hardware parameter initialization; Set up with wiring board between being connected of HDLC;
2 master control borads send configuration parameter to wiring board by HDLC;
The voice that 3 master control borads receive by TDM bus are sent to the office terminal on computer by ethernet switching module;
4 master control borads receive voice and are sent to TDM bus.
Contrast accompanying drawing 4, the line control unit being furnished with on multicast communication device line plate, its structure is corresponding the joining of signal input/output terminal of first signal input/output end with the C transformer of a PEF24628 SHDSL module,
The secondary signal input/output end of the one PEF24628 SHDSL module and corresponding the joining of signal input/output terminal of a LPC1768 ARM first,
The 3rd signal input/output end of the one PEF24628 SHDSL module and corresponding the joining of first signal input/output terminal of the second ethernet PHY chip,
The 4th signal input/output end of the one PEF24628 SHDSL module and corresponding the joining of first signal input/output terminal of an EP2C5Q208C8N FPGA,
Corresponding the joining of first signal input/output end of the signal input/output terminal of the one LPC1768 ARM second and the 2nd PEF24628 SHDSL module,
Corresponding the joining of secondary signal input/output end of the signal input/output terminal of the one LPC1768 ARM the 3rd and the 2nd EP2C5Q208C8N FPGA,
The secondary signal input/output end of the 2nd PEF24628 SHDSL module and corresponding the joining of signal input/output terminal of H transformer,
The 3rd signal input/output terminal of the 2nd EP2C5Q208C8N FPGA and corresponding the joining of signal input/output end of HDLC;
Corresponding the joining of first signal input/output end of the 4th signal input/output terminal of the 2nd EP2C5Q208C8N FPGA and the second digital junction PHY chip, a SLIC/CO, the 2nd SLIC/CO; The secondary signal input/output end of the one SLIC/CO, the 2nd SLIC/CO is answered the call respectively;
The signal output part of the second digital junction PHY chip connects the signal input part of E transformer, the signal input/output termination E1 of E transformer;
The 5th signal input/output terminal of the 2nd EP2C5Q208C8N FPGA respectively with the first signal of the 3rd digital junction PHY chip, Three S's LIC/CO, the 4th SLIC/CO first input/output end is corresponding joins,
The signal input part of the 3rd digital junction PHY chip signal output termination F transformer, the signal input/output termination E1 of F transformer; Join corresponding with phone of secondary signal input/output end of Three S's LIC/CO, the 4th SLIC/CO
The 6th signal I/O termination PCM speech code of the 2nd EP2C5Q208C8N FPGA;
The 3rd corresponding joining of signal input/output end of the 7th signal input/output terminal of the 2nd EP2C5Q208C8N FPGA and the 2nd PEF24628 SHDSL module;
Corresponding the joining of first signal input/output end of the secondary signal input/output terminal of the second ethernet PHY chip and D transformer, the secondary signal input/output termination Ethernet of D transformer;
The 4th signal input/output end and three-ethernet PHY chip first signal corresponding the joining of input/output terminal of the 2nd PEF24628 SHDSL module; Corresponding the joining of first signal input/output end of three-ethernet PHY chip secondary signal input/output terminal and G transformer, the secondary signal input/output termination Ethernet of G transformer;
The wiring board course of work is as follows:
1 wiring board control unit initialization, completes hardware parameter initialization, and SHDSL block configuration is mixed transmission modes (TDM and Ethernet), and foundation is connected with the HDLC between master control borad;
2 wiring boards receive the order of master control borad configuration parameter, download SHDSL module SOC (system on a chip);
3 wiring board configuration line speeds, master/slave pattern, talk-back, subscriber phone;
5 wiring boards receive business information (data such as video, file, fax) by ethernet switching module, by SHDSL module, are sent to far-end;
6 wiring boards receive the PCM speech of master control borad by TDM bus, by SHDSL module, be sent to far-end;
The SHDSL module of 7 wiring boards receives remote equipment message by twisted-pair feeder, and business information (data such as video, file, fax) is sent by ethernet switching module, and PCM voice are sent to TDM bus.
Wiring board is selected the primary processor of the Cortex-M3 processor LPC1768 of NXP company, and SHDSL module (PEF24628), FPGA (Field Programmable Gate Array, field programmable gate array) (EP2C5Q208C8N) form.Primary processor mainly completes functions such as the configuration of the SHDSL chip of wiring board, control, monitorings.Coordinate master control borad software, realize the management of this equipment and monitoring function.
In TDM bus between circuit plate and master control borad except containing above-mentioned PCM speech, every plate also arranges a road HDLC (High Level Data Link Control, senior link is controlled) control information, be mainly used in the configuration information of transmission lines plate and line status etc.
Contrast accompanying drawing 5, on multicast communication device network plate, be furnished with the 2nd LPC1768 ARM of network primary processor, the signal input part of first signal output termination the one 88E6095 exchange chip of the 2nd LPC1768 ARM, the signal input part of secondary signal output termination the 2nd 88E6095 exchange chip of the one LPC1768 ARM
Corresponding the joining of first signal input/output end of the first signal input/output terminal of the one 88E6095 exchange chip and I transformer, the secondary signal input/output termination Ethernet of I transformer;
Corresponding the joining of first signal input/output end of the secondary signal input/output terminal of the one 88E6095 exchange chip and J transformer, the secondary signal input/output termination Ethernet of J transformer;
Corresponding the joining of first signal input/output end of the first signal input/output terminal of the 2nd 88E6095 exchange chip and K transformer, the secondary signal input/output termination Ethernet of K transformer;
Corresponding the joining of first signal input/output end of the secondary signal input/output terminal of the 2nd 88E6095 exchange chip and L transformer, the secondary signal input/output termination Ethernet of L transformer.
Network board primary processor is selected Cortex-M3 processor LPC1768, the Ethernet switching chip (88E6095) of NXP company.
This equipment is by above method, and every twisted-pair communication bandwidth is that 128kbps is adjustable to 8Mbps.Can transmit the integrated services such as wideband data (data such as video, file, fax), speech, transmission range can reach 10 kilometers simultaneously.
Method based on SHDSL multicast communication, comprises
1) on many twisted-pair feeders, carry wideband data and the speech business that is up to 8Mbps simultaneously;
2) every block of circuit plate is processed the HDSL signal of two twisted-pair feeders by two HDSL chips;
3) through ethernet physical layer interface chip, by base plate, deliver to Ethernet exchanging matrix with master control board-to-board information;
4) master processor of master control borad is delivered in PCM speech business by TDM bus by the clock request of master control borad by programming device;
5) telephone signal via telephony interface chip comprise SLIC (Subscriber Line Interface Circuit, user interface circuit/CO (Central Office, telephone wire is delivered in Local Exchange configuration;
6) in the TDM bus between circuit plate and master control except containing above-mentioned PCM speech, every plate also arranges a road HDLC control information, for configuration information and the line status of transmission lines plate;
7) with network board, realize the link layer function of exchange of each circuit plate and master processor and external network, it is formed by two 8 port one 00M Ethernet switching chip cascades.
Claims (5)
1. based on SHDSL multicast communication device systems, it is characterized in that cabinet board plug type structure, comprise multicast communication equipment motherboard, multicast communication equipment master control plate, multicast communication device line plate and a multicast communication device network plate; Described a multicast communication equipment master control plate, multicast communication device line plate and multicast communication device network plate correspondence patch on multicast communication equipment motherboard.
2. according to claim 1 based on SHDSL multicast communication device systems, it is characterized in that comprising on described multicast communication equipment motherboard one with the network plate plate position of the master control plate plate position of the corresponding setting of multicast communication master control plate, and the corresponding setting of multipoint transport network plate and the polylith polylith circuit plate plate position with the corresponding setting of multicast communication circuit plate.
3. according to claim 1 based on SHDSL multicast communication device systems,
described in it is characterized in thaton multicast communication equipment master control plate, be furnished with control unit, the structure of this control unit is corresponding the joining of signal input/output terminal of first signal input/output end with the RAM of MPC8280 PowerPC;
The secondary signal input/output end of MPC8280 PowerPC and corresponding the joining of signal input/output terminal of FLASH;
The 3rd signal input/output end of MPC8280 PowerPC and corresponding the joining of first signal input/output terminal of EP2C8Q208I8 FPGA;
The 4th signal input/output end of MPC8280 PowerPC and corresponding the joining of first signal input/output terminal of the first ethernet PHY chip; Corresponding the joining of first signal input/output end of the secondary signal input/output terminal of the first ethernet PHY chip and A transformer; The secondary signal input/output termination Ethernet of A transformer;
The 5th signal input/output end of MPC8280 PowerPC and corresponding the joining of first signal input/output terminal of TMS320VC5509 DSP;
The 6th signal input/output termination HDLC of MPC8280 PowerPC;
Corresponding the joining of secondary signal input/output end of the secondary signal input/output terminal of EP2C8Q208I8 FPGA and TMS320VC5509 DSP;
Corresponding the joining of signal input/output end of the 3rd signal input/output terminal of EP2C8Q208I8 FPGA and the first digital junction PHY chip; Corresponding the joining of first signal input of the signal output part of the first digital junction PHY chip and B transformer; The signal I/O termination E1 of B transformer;
The 3rd signal input/output termination PCM speech of TMS320VC5509 DSP.
4. according to claim 1 based on SHDSL multicast communication device systems, it is characterized in that being furnished with line control unit on described multicast communication device line plate, the structure of this line control unit is the
The first signal input/output end of one PEF24628 SHDSL module and corresponding the joining of signal input/output terminal of C transformer,
The secondary signal input/output end of the one PEF24628 SHDSL module and corresponding the joining of signal input/output terminal of a LPC1768 ARM first,
The 3rd signal input/output end of the one PEF24628 SHDSL module and corresponding the joining of first signal input/output terminal of the second ethernet PHY chip,
The 4th signal input/output end of the one PEF24628 SHDSL module and corresponding the joining of first signal input/output terminal of EP2C5Q208C8N FPGA,
Corresponding the joining of first signal input/output end of the signal input/output terminal of the one LPC1768 ARM second and the 2nd PEF24628 SHDSL module,
Corresponding the joining of secondary signal input/output end of the signal input/output terminal of the one LPC1768 ARM the 3rd and EP2C5Q208C8N FPGA,
The secondary signal input/output end of the 2nd PEF24628 SHDSL module and corresponding the joining of signal input/output terminal of H transformer,
The 3rd signal input/output terminal of EP2C5Q208C8N FPGA and corresponding the joining of signal input/output end of HDLC;
Corresponding the joining of first signal input/output end of the 4th signal input/output terminal of EP2C5Q208C8N FPGA and the second digital junction PHY chip, a SLIC/CO, the 2nd SLIC/CO; The secondary signal input/output end of the one SLIC/CO, the 2nd SLIC/CO is answered the call respectively;
The signal output part of the second digital junction PHY chip connects the signal input part of E transformer, the signal input/output termination E1 of E transformer;
The 5th signal input/output terminal of EP2C5Q208C8N FPGA respectively with the first signal of the 3rd digital junction PHY chip, Three S's LIC/CO, the 4th SLIC/CO first input/output end is corresponding joins,
The signal input part of the 3rd digital junction PHY chip signal output termination F transformer, the signal input/output termination E1 of F transformer; Join corresponding with phone of secondary signal input/output end of Three S's LIC/CO, the 4th SLIC/CO;
The 6th signal I/O termination PCM speech code of EP2C5Q208C8N FPGA;
The 3rd corresponding joining of signal input/output end of the 7th signal input/output terminal of EP2C5Q208C8N FPGA and the 2nd PEF24628 SHDSL module;
Corresponding the joining of first signal input/output end of the secondary signal input/output terminal of the second ethernet PHY chip and D transformer, the secondary signal input/output termination Ethernet of D transformer;
The 4th signal input/output end and three-ethernet PHY chip first signal corresponding the joining of input/output terminal of the 2nd PEF24628 SHDSL module; Corresponding the joining of first signal input/output end of three-ethernet PHY chip secondary signal input/output terminal and G transformer, the secondary signal input/output termination Ethernet of G transformer.
5. according to claim 1 based on SHDSL multicast communication device systems, it is characterized in that being furnished with network primary processor on described multicast communication device network plate, the signal input part of first signal output termination the one 88E6095 exchange chip of the 2nd LPC1768 ARM of this network primary processor, the signal input part of secondary signal output termination the 2nd 88E6095 exchange chip of the one LPC1768 ARM
Corresponding the joining of first signal input/output end of the first signal input/output terminal of the one 88E6095 exchange chip and I transformer, the secondary signal input/output termination Ethernet of I transformer;
Corresponding the joining of first signal input/output end of the secondary signal input/output terminal of the one 88E6095 exchange chip and J transformer, the secondary signal input/output termination Ethernet of J transformer;
Corresponding the joining of first signal input/output end of the first signal input/output terminal of the 2nd 88E6095 exchange chip and K transformer, the secondary signal input/output termination Ethernet of K transformer;
Corresponding the joining of first signal input/output end of the secondary signal input/output terminal of the 2nd 88E6095 exchange chip and L transformer, the secondary signal input/output termination Ethernet of L transformer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320362727.5U CN203416315U (en) | 2013-06-24 | 2013-06-24 | Multipoint transmission equipment system based on SHDSL |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320362727.5U CN203416315U (en) | 2013-06-24 | 2013-06-24 | Multipoint transmission equipment system based on SHDSL |
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| CN203416315U true CN203416315U (en) | 2014-01-29 |
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| CN201320362727.5U Expired - Fee Related CN203416315U (en) | 2013-06-24 | 2013-06-24 | Multipoint transmission equipment system based on SHDSL |
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Granted publication date: 20140129 Termination date: 20210624 |