CN203350760U - Reference current and reference voltage generating circuit with high power supply rejection ratio and low power consumption - Google Patents

Abstract

The utility model relates to a reference current and reference voltage generating circuit with the high power supply rejection ratio and the low power consumption. The reference current and reference voltage generating circuit is characterized by comprising a PMOS pipe P1, a PMOS pipe P2, a PMOS pipe P3, an NMOS pipe N1, an NMOS pipe N2, an NMOS pipe N3 and an NMOS pipe N4, wherein a power supply VDD is connected with the grid electrode of the N1, the source electrode of the P1, the source electrode of the P2, the source electrode of the P3, the drain electrode of the N2 and the drain electrode of the N3; the drain electrode of the P1 is connected with the grid electrode of the P1, the grid electrode of the P2, the grid electrode of the P3 and the drain electrode of the N1; the source electrode of the N1 is connected with the source electrode of the N3 and the drain electrode of the N4; the grid electrode of the N4 is connected with the grid electrode and the drain electrode of the N5 and the drain electrode of the P2; the grid electrode of the N2 is connected with the grid electrode and the drain electrode of the N3; the source electrode of the N2, the source electrode of the N4 and the source electrode of the N5 are connected with a power supply GND, and the drain electrode of the P3 is used as the output end of the reference current generating circuit. The reference current and reference voltage generating circuit is low in power consumption, small in area and high in power supply rejection ratio.

Description

High PSRR, low-power consumption reference current and reference voltage generating circuit

Technical field

The utility model relates to the Analogous Integrated Electronic Circuits design field, especially a kind of high PSRR, low-power consumption reference current and reference voltage generating circuit.

Background technology

Reference voltage and reference current generating circuit are important unit modules in integrated circuit; be widely used in various Analogous Integrated Electronic Circuits, hybrid digital-analog integrated circuit and on-chip system chip, as analog to digital converter (ADC), phaselocked loop (PLL) and power management chip etc.Reference power supply generally all requires low-power consumption, low supply voltage, Low Drift Temperature coefficient, high PSRR, output noise little etc. now.

Existing is to realize that the reference voltage circuit of Low Drift Temperature coefficient is generally to adopt the substrate bipolar transistor in CMOS technique, because the base-emitter voltage of bipolar transistor has negative temperature coefficient, and two bipolar transistors are operated under unequal current density, the base-emitter voltage difference has positive temperature coefficient (PTC), by two coefficients with suitable weight addition, can obtain zero-temperature coefficient, there is following problem in this kind of method:

1, introduce the amplifier burning voltage, thereby improve Power Supply Rejection Ratio, but need supply voltage larger, the speed of amplifier itself, imbalance, noise also have a great impact output voltage in addition.

2, triode is large with respect to the metal-oxide-semiconductor chip area, and needs resistance, and area occupied is larger.

3, increase amplifier, supply voltage is high, and power consumption is higher.

These factors have limited the performance of reference voltage to a certain extent, have much room for improvement.

As shown in Figure 1, this circuit output current expression formula is typical reference current generating circuit:

$I_{\mathrm{out}}=\frac{2}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}{(W/L)}_N{R_s}^2}{(1-\frac{1}{\sqrt{K}})}^2---\left(1\right).$

Wherein, μ _nfor electron mobility, C _oxfor the gate oxide electric capacity of unit area, the ratio of the breadth length ratio that K is Q2 and the breadth length ratio of Q1, (W/L) _nbreadth length ratio for Q1.

There is following problem in this reference current generating circuit:

1, (1) formula is in the situation that hypothesis I1=I2 draws, works as mains voltage variations, and it is equal with I2 that I1 can't keep, and both variation tendencies are contrary, thereby cause output current larger with mains voltage variations.

2, prior art is ordered about I1=I2 by introducing amplifier, but the imbalance of amplifier and noise can make the reference current source performance reduce equally.

3, in the low-power consumption application, little for making bias current, needed resistance R s is very large, occupies very large tracts of land of chip.

These factors have limited the performance of reference current to a certain extent, have much room for improvement.

The utility model content

In view of this, the purpose of this utility model is to provide a kind of high PSRR, low-power consumption reference current generating circuit.

The utility model adopts following scheme to realize: a kind of high PSRR, the low-power consumption reference current generating circuit, it is characterized in that: comprise PMOS pipe P1, PMOS pipe P2 and PMOS pipe P3 and NMOS pipe N1, NMOS manages N2, NMOS manages N3, NMOS pipe N4 and NMOS pipe N5, power vd D connects the grid of described NMOS pipe N1, described PMOS pipe P1, the drain electrode of the source electrode of PMOS pipe P2 and PMOS pipe P3 and described NMOS pipe N2 and NMOS pipe N3, the drain electrode of described PMOS pipe P1 connects described PMOS pipe P1, the drain electrode of the grid of PMOS pipe P2 and PMOS pipe P3 and described NMOS pipe N1, the source electrode of described NMOS pipe N1 connects the drain electrode of source electrode and the described NMOS pipe N4 of described NMOS pipe N3, the grid of described NMOS pipe N4 connects the drain electrode of grid and drain electrode and the described PMOS pipe P2 of described NMOS pipe N5, the grid of described NMOS pipe N2 connects grid and the drain electrode of described NMOS pipe N3, described NMOS pipe N2, NMOS pipe N4 is connected power supply GND with the source electrode of NMOS pipe N5, the drain electrode of described PMOS pipe P3 is as the output terminal of described reference current generating circuit.

In the utility model one embodiment, also comprise a PMOS pipe P4 and PMOS pipe P5, disconnect the grid of described NMOS pipe N1, drain electrode and described NMOS the pipe drain electrode of N3 and being connected of power vd D of described NMOS pipe N2, described PMOS pipe P4 is connected power vd D with the source electrode of PMOS pipe P5, described PMOS pipe P4 is connected the grid of described PMOS pipe P1 with the grid of PMOS pipe P5, the drain electrode of described PMOS pipe P4 connects the drain electrode of grid and the described NMOS pipe N2 of described NMOS pipe N1, and the drain electrode of described PMOS pipe P5 connects the drain electrode of described NMOS pipe N3.

In the utility model one embodiment, also comprise a start-up circuit, described start-up circuit comprises PMOS pipe Pa, PMOS pipe Pb, PMOS pipe Pc, PMOS pipe Pd and PMOS pipe Pe and capacitor C 1 and capacitor C 2, power vd D connects described PMOS pipe Pa and the source electrode of PMOS pipe Pe and the positive pole of capacitor C, the grid of described PMOS pipe Pa connects the grid of described PMOS pipe P1, the negative pole of described capacitor C connects the drain electrode of described PMOS pipe Pa and PMOS pipe Pb and the grid of described PMOS pipe Pb and PMOS pipe Pe, the source electrode of described PMOS pipe Pb connects the drain and gate of described PMOS pipe Pc, the source electrode of described PMOS pipe Pc connects the drain and gate of described PMOS pipe Pd, the source electrode of described PMOS pipe Pd and the negative pole of described capacitor C 2 are connected power supply GND, the drain electrode of described PMOS pipe Pe connects the drain electrode of positive pole and the described PMOS pipe P4 of described capacitor C 2.

Another purpose of the present utility model is to provide a kind of high PSRR, low-power consumption reference voltage generating circuit.

Adopt following scheme to realize: a kind of high PSRR, the low-power consumption reference voltage generating circuit, it is characterized in that: comprise a reference current generating circuit, one negative temperature coefficient voltage generation unit, N positive temperature coefficient (PTC) voltage generation unit and N+1 PMOS pipe, N is positive integer, the output terminal of described the 1st positive temperature coefficient (PTC) voltage generation unit is as the output terminal of described reference voltage generating circuit, one end of described the 1st positive temperature coefficient (PTC) voltage generation unit described the 1st the PMOS pipe of connecting is connected to power vd D, the other end of described the 1st positive temperature coefficient (PTC) voltage generation unit connects the output terminal of described the 2nd positive temperature coefficient (PTC) voltage generation unit, by that analogy, one end of described N positive temperature coefficient (PTC) voltage generation unit described N the PMOS pipe of connecting is connected to power vd D, the other end of described N positive temperature coefficient (PTC) voltage generation unit connects the output terminal of described negative temperature coefficient voltage generation unit, the grid of described N+1 PMOS pipe all is connected to the drain electrode of described N+1 PMOS pipe and the power end of described reference current generating circuit, the output head grounding of described reference current generating circuit.

In the utility model one embodiment, described positive temperature coefficient (PTC) voltage generation unit comprises NMOS pipe M1 and NMOS pipe M2, the drain electrode of described NMOS pipe M1 is as an end of described positive temperature coefficient (PTC) voltage generation unit and connect described NMOS pipe M1 and the grid of NMOS pipe M2, the source electrode of described NMOS pipe M1 is as the output terminal of described positive temperature coefficient (PTC) voltage generation unit and connect the drain electrode of described NMOS pipe M2, and the source electrode of described NMOS pipe M2 is as the other end of described positive temperature coefficient (PTC) voltage generation unit.

In the utility model one embodiment, described negative temperature coefficient voltage generation unit comprises a NMOS pipe M3, the drain electrode of described NMOS pipe M3 is as the output terminal of described negative temperature coefficient voltage generation unit and connect the grid of described NMOS pipe M3, and the source electrode of described NMOS pipe M3 is connected to ground.

Reference current generating circuit of the present utility model and reference voltage generating circuit have the following advantages:

1, adopt the whole CMOS device, except the little electric capacity that start-up circuit increases, without resistance, chip area is little.

2, introduce the mode of the 3rd branch road in reference current generating circuit, improve the Power Supply Rejection Ratio of reference current generating circuit.

3, circuit working is in sub-threshold region, and the electric current of each branch road is all in the 10nA left and right, and the power consumption of circuitry consumes is quite little.

4, adopt the weighted array of positive temperature coefficient (PTC) voltage generation unit and negative temperature coefficient voltage generation unit in reference voltage generating circuit, the circuit array mode is simply useful, and design is convenient.

5, the reference current generating circuit finally obtained and reference voltage generating circuit power consumption are extremely low and area is little, are particularly suitable for the reference power supply of power management chip in portable type electronic product, analog to digital converter or phaselocked loop etc.

For making the purpose of this utility model, technical scheme and advantage clearer, below will, by specific embodiment and relevant drawings, the utility model be described in further detail.

The accompanying drawing explanation

Fig. 1 is classical and current source schematic diagram independent of power voltage.

Fig. 2 is system chart of the present utility model.

Fig. 3 is reference current generating circuit schematic diagram of the present utility model.

Fig. 4 is positive temperature coefficient (PTC) voltage generation unit schematic diagram.

Fig. 5 is negative temperature coefficient voltage generation unit schematic diagram.

Fig. 6 is reference voltage generating circuit schematic diagram of the present utility model.

Embodiment

As shown in Figure 2, Fig. 2 is system chart of the present utility model, comprises start-up circuit, reference current generating circuit and reference voltage generating circuit.

As shown in Figure 3, a kind of high PSRR, the low-power consumption reference current generating circuit, comprise PMOS pipe P1, PMOS pipe P2 and PMOS pipe P3 and NMOS pipe N1, NMOS manages N2, NMOS manages N3, NMOS pipe N4 and NMOS pipe N5, power vd D connects the grid of described NMOS pipe N1, described PMOS pipe P1, the drain electrode of the source electrode of PMOS pipe P2 and PMOS pipe P3 and described NMOS pipe N2 and NMOS pipe N3, the drain electrode of described PMOS pipe P1 connects described PMOS pipe P1, the drain electrode of the grid of PMOS pipe P2 and PMOS pipe P3 and described NMOS pipe N1, the source electrode of described NMOS pipe N1 connects the drain electrode of source electrode and the described NMOS pipe N4 of described NMOS pipe N3, the grid of described NMOS pipe N4 connects the drain electrode of grid and drain electrode and the described PMOS pipe P2 of described NMOS pipe N5, the grid of described NMOS pipe N2 connects grid and the drain electrode of described NMOS pipe N3, described NMOS pipe N2, NMOS pipe N4 is connected power supply GND with the source electrode of NMOS pipe N5, the drain electrode of described PMOS pipe P3 is as the output terminal of described reference current generating circuit.

Preferably, also comprise a PMOS pipe PMOS pipe P4 and PMOS pipe P5, disconnect the grid of described NMOS pipe N1, drain electrode and described NMOS the pipe drain electrode of N3 and being connected of power vd D of described NMOS pipe N2, described PMOS pipe P4 is connected power vd D with the source electrode of PMOS pipe P5, described PMOS pipe P4 is connected the grid of described PMOS pipe P1 with the grid of PMOS pipe P5, the drain electrode of described PMOS pipe P4 connects the drain electrode of grid and the described NMOS pipe N2 of described NMOS pipe N1, and the drain electrode of described PMOS pipe P5 connects the drain electrode of described NMOS pipe N3, especially, also comprise a start-up circuit, described start-up circuit comprises PMOS pipe PMOS pipe Pa, PMOS pipe Pb, PMOS pipe Pc, PMOS pipe Pd and PMOS pipe Pe and capacitor C 1 and capacitor C 2, power vd D connects described PMOS pipe Pa and the source electrode of PMOS pipe Pe and the positive pole of capacitor C, the grid of described PMOS pipe Pa connects the grid of described PMOS pipe P1, the negative pole of described capacitor C connects the drain electrode of described PMOS pipe Pa and PMOS pipe Pb and the grid of described PMOS pipe Pb and PMOS pipe Pe, the source electrode of described PMOS pipe Pb connects the drain and gate of described PMOS pipe Pc, the source electrode of described PMOS pipe Pc connects the drain and gate of described PMOS pipe Pd, the source electrode of described PMOS pipe Pd and the negative pole of described capacitor C 2 are connected power supply GND, the drain electrode of described PMOS pipe Pe connects the drain electrode of positive pole and the described PMOS pipe P4 of described capacitor C 2.

The principle of work of start-up circuit is, when circuit powers on, circuit is in " degeneracy " zero point, capacitor C 1 both end voltage can not be suddenlyd change, PMOS pipe Pb, PMOS pipe Pc, the PMOS pipe Pd pipe earial drainage connected by diode, when PMOS pipe Pe pipe gate source voltage is greater than its threshold voltage, the conducting of PMOS pipe Pe pipe, force NMOS pipe N2, NMOS pipe N3, NMOS pipe N1 generation current, circuit is started working; The electric current that meanwhile PMOS pipe Pa flows through increases gradually, thereby improves PMOS pipe Pe grid terminal voltage, forces PMOS pipe Pe cut-off, and circuit start is complete.

With classical reference current generating circuit, compare, reference current generating circuit of the present utility model increases the 3rd branch road of PMOS pipe P1 and NMOS pipe N1 formation, the diode that discharges PMOS pipe P4 connects, improve the Power Supply Rejection Ratio of reference current, although existing, by increasing the circuit design of the 3rd branch road, its design also needs to introduce large resistance in the low-power consumption application, and the utility model is introduced NMOS pipe N4, the 4th branch road that NMOS pipe N5 and PMOS pipe P2 form, replace large resistance.Also had or not the design of Resistance standard, still the circuit of design can not be compromised preferably on power consumption, chip area in the past, and the utility model can, at circuit power consumption, chip area, obtain good compromise on circuit performance.

If S _ni, S _pibe respectively the breadth length ratio of i NMOS pipe, PMOS pipe, ${\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="130524150223.png"\; state="\{\{state\}\}">K</figure-callout>}}_1=\frac{S_{N3}{S}_{P4}}{S_{N3}{S}_{P5}},{\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="130524150223.png"\; state="\{\{state\}\}">K</figure-callout>}}_2=\frac{S_{N4}{S}_{P2}}{S_{N5}{S}_{P5}},{\mathrm{<figure-callout\; id="3"\; label="K"\; filenames="130524150223.png"\; state="\{\{state\}\}">K</figure-callout>}}_3=\frac{S_{P1}}{S_{P5}},{\mathrm{\&beta;}}_{\mathrm{<figure-callout\; id="4"\; label="N"\; filenames="130524150223.png"\; state="\{\{state\}\}">N</figure-callout>}4}=\mathrm{\&mu;}{C}_{\mathrm{<figure-callout\; id="4"\; label="ox\; S\; N"\; filenames="130524150223.png"\; state="\{\{state\}\}">ox</figure-callout>}}{S}_N{4}_{},{\mathrm{\&beta;}}_{N5}=\mathrm{\&mu;}{C}_{\mathrm{ox}}{S}_{N5}.$

Wherein, K1 means: (N3 breadth length ratio * P4 breadth length ratio)/(N2 breadth length ratio * P5 breadth length ratio), and K2, K3 is similar; for thermal voltage, k is Boltzmann constant, and q is electron charge, and T means temperature, C _oxfor the gate oxide electric capacity of unit area, mobility [mu]=a μ ₀t ^m, a is scale-up factor, μ ₀for the mobility under initial temperature, m is a parameter relevant with technique, is about-3/2; Output current i _n3expression formula is:

$\begin{array}{c}{\mathrm{<figure-callout\; id="3"\; label="i\; N"\; filenames="130524150223.png"\; state="\{\{state\}\}">i</figure-callout>}}_N={\mathrm{\&beta;}}_{\mathrm{<figure-callout\; id="4"\; label="N"\; filenames="130524150223.png"\; state="\{\{state\}\}">N</figure-callout>}4}{\mathrm{\&xi;}}^2{V_T}^2{K}_{\mathrm{eff}}=\mathrm{\&mu;}{V_T}^2{C}_{\mathrm{<figure-callout\; id="4"\; label="ox\; S\; N"\; filenames="130524150223.png"\; state="\{\{state\}\}">ox</figure-callout>}}{S}_N{4}_{}{\mathrm{\&xi;}}^2{K}_{\mathrm{eff}}=a{\mathrm{\&mu;}}_0{T}^m{\left(\frac{k}{q}\right)}^2{T}^2{C}_{\mathrm{<figure-callout\; id="4"\; label="ox\; S\; N"\; filenames="130524150223.png"\; state="\{\{state\}\}">ox</figure-callout>}}{S}_N{4}_{}{\mathrm{\&xi;}}^2{K}_{\mathrm{eff}}\\ =a{\mathrm{\&mu;}}_0{\left(\frac{k}{q}\right)}^2{C}_{\mathrm{<figure-callout\; id="4"\; label="ox\; S\; N"\; filenames="130524150223.png"\; state="\{\{state\}\}">ox</figure-callout>}}{S}_N{4}_{}{\mathrm{\&xi;}}^2{K}_{\mathrm{eff}}\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="130524150223.png"\; state="\{\{state\}\}">T</figure-callout>}}^{2+m}=\mathrm{\&theta;}\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="130524150223.png"\; state="\{\{state\}\}">T</figure-callout>}}^{2+m}\end{array}---\left(2\right).$

Wherein $K_{\mathrm{eff}}=\frac{[K_2-\frac{{\mathrm{<figure-callout\; id="3"\; label="K"\; filenames="130524150223.png"\; state="\{\{state\}\}">K</figure-callout>}}_3}{2}-\frac{1}{2}+\sqrt{K_2(K_2-K_3-1)}]{\ln }^2\left(K_1\right)}{{({\mathrm{<figure-callout\; id="3"\; label="K"\; filenames="130524150223.png"\; state="\{\{state\}\}">K</figure-callout>}}_3+1)}^2},$ ζ is the sub-threshold slope factor, and its value is also relevant in technique, between representative value 1.2-1.5,

can show that by (2) formula output current varies with temperature the positive temperature coefficient (PTC) a little less than having, temperature variation is little.The existence of the 3rd branch road, make the circuit power rejection ratio very high, can increase the cascade pipe in three branch roads, further improves the Power Supply Rejection Ratio of circuit.

Another purpose of the present utility model is to provide a kind of high PSRR, low-power consumption reference voltage generating circuit.

As shown in Figure 4, positive temperature coefficient (PTC) voltage generation unit comprises NMOS pipe M1 and NMOS pipe M2, the drain electrode of described NMOS pipe M1 is as an end of described positive temperature coefficient (PTC) voltage generation unit and connect described NMOS pipe M1 and the grid of NMOS pipe M2, the source electrode of described NMOS pipe M1 is as the output terminal of described positive temperature coefficient (PTC) voltage generation unit and connect the drain electrode of described NMOS pipe M2, and the source electrode of described NMOS pipe M2 is as the other end of described positive temperature coefficient (PTC) voltage generation unit.

As shown in Figure 5, negative temperature coefficient voltage generation unit comprises a NMOS pipe M3, and the drain electrode of described NMOS pipe M3 is as the output terminal of described negative temperature coefficient voltage generation unit and connect the grid of described NMOS pipe M3, and the source electrode of described NMOS pipe M3 is connected to ground.

As shown in Figure 6, a kind of high PSRR, the low-power consumption reference voltage generating circuit, comprise just like the reference current generating circuit shown in Fig. 3 (meaning by the current source diagram in Fig. 6), one negative temperature coefficient voltage generation unit, 4 positive temperature coefficient (PTC) voltage generation units and 5 PMOS pipes, the output terminal of described the 1st positive temperature coefficient (PTC) voltage generation unit is as the output terminal of described reference voltage generating circuit, one end of described the 1st positive temperature coefficient (PTC) voltage generation unit described the 1st the PMOS pipe of connecting is connected to power vd D, the other end of described the 1st positive temperature coefficient (PTC) voltage generation unit connects the output terminal of described the 2nd positive temperature coefficient (PTC) voltage generation unit, one end of described the 2nd positive temperature coefficient (PTC) voltage generation unit described the 2nd the PMOS pipe of connecting is connected to power vd D, the other end of described the 2nd positive temperature coefficient (PTC) voltage generation unit connects the output terminal of described the 3rd positive temperature coefficient (PTC) voltage generation unit, one end of described the 3rd positive temperature coefficient (PTC) voltage generation unit described the 3rd the PMOS pipe of connecting is connected to power vd D, the other end of described the 3rd positive temperature coefficient (PTC) voltage generation unit connects the output terminal of described the 4th positive temperature coefficient (PTC) voltage generation unit, one end of described the 4th positive temperature coefficient (PTC) voltage generation unit described the 4th the PMOS pipe of connecting is connected to power vd D, the other end of described the 4th positive temperature coefficient (PTC) voltage generation unit connects the output terminal of described negative temperature coefficient voltage generation unit, the grid of described 5 PMOS pipes all is connected to the drain electrode of described the 5th PMOS pipe and the power end of described reference current generating circuit, the output head grounding of described reference current generating circuit.

Reference voltage generating circuit adopts reference current generating circuit of the present utility model as biasing circuit, based on sub-threshold region MOSFET device gate source voltage V _gSnegative temperature characteristic and the positive temperature characterisitic design of two MOSFET series connection intermediate node voltage.The output voltage of circuit can be derived:

$V_o=V_{o\left(1\right)}=\mathrm{\&xi;}{V}_T\ln ({K_M}^N\&CenterDot;N!)+V_{\mathrm{th}}+\mathrm{\&xi;}{V}_T\ln \left(\frac{I_D}{\frac{W}{L}{I}_0}\right)---\left(3\right).$

Wherein, ζ is the sub-threshold slope factor,

for thermal voltage, k is Boltzmann constant, and q is electron charge, and T means temperature, K _mfor the ratio of the breadth length ratio of the breadth length ratio of M2 and M1, N is a way, V _thfor the threshold voltage of M3, I _dfor bias current, I ₀for leakage current,

breadth length ratio for M3.

Make V ₀there is the zero-temperature coefficient characteristic:

$\frac{{\&PartialD;V}_0}{\&PartialD;T}=\mathrm{\&xi;}\frac{k}{q}\ln ({K_M}^N\&CenterDot;N!\&CenterDot;\frac{I_D}{\frac{W}{L}{I}_0})-\mathrm{\&kappa;}=0---\left(4\right).$

The temperature coefficient that κ is the metal-oxide-semiconductor threshold voltage.

Choose suitable K _mcan obtain the output reference voltage of zero temp shift coefficient with N, and, as long as current source biasing metal-oxide-semiconductor is operated in sub-threshold region, output reference voltage floats coefficient with current source size, temperature and almost has nothing to do.In theory, by choosing different K _mcan obtain the different expression form of circuit with N, the utility model proposes wherein a kind of form, work as K _mduring=10, N=4.

Above-listed preferred embodiment; the purpose of this utility model, technical scheme and advantage are further described; institute is understood that; the foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection domain of the present utility model.

Claims (6)

1. a high PSRR, the low-power consumption reference current generating circuit, it is characterized in that: comprise PMOS pipe P1, PMOS pipe P2 and PMOS pipe P3 and NMOS pipe N1, NMOS manages N2, NMOS manages N3, NMOS pipe N4 and NMOS pipe N5, power vd D connects the grid of described NMOS pipe N1, described PMOS pipe P1, the drain electrode of the source electrode of PMOS pipe P2 and PMOS pipe P3 and described NMOS pipe N2 and NMOS pipe N3, the drain electrode of described PMOS pipe P1 connects described PMOS pipe P1, the drain electrode of the grid of PMOS pipe P2 and PMOS pipe P3 and described NMOS pipe N1, the source electrode of described NMOS pipe N1 connects the drain electrode of source electrode and the described NMOS pipe N4 of described NMOS pipe N3, the grid of described NMOS pipe N4 connects the drain electrode of grid and drain electrode and the described PMOS pipe P2 of described NMOS pipe N5, the grid of described NMOS pipe N2 connects grid and the drain electrode of described NMOS pipe N3, described NMOS pipe N2, NMOS pipe N4 is connected power supply GND with the source electrode of NMOS pipe N5, the drain electrode of described PMOS pipe P3 is as the output terminal of described reference current generating circuit.

2. high PSRR according to claim 1, the low-power consumption reference current generating circuit, it is characterized in that: also comprise a PMOS pipe P4 and PMOS pipe P5, disconnect the grid of described NMOS pipe N1, the drain electrode of described NMOS pipe N2 and described NMOS the pipe drain electrode of N3 and being connected of power vd D, described PMOS pipe P4 is connected power vd D with the source electrode of PMOS pipe P5, described PMOS pipe P4 is connected the grid of described PMOS pipe P1 with the grid of PMOS pipe P5, the drain electrode of described PMOS pipe P4 connects the drain electrode of grid and the described NMOS pipe N2 of described NMOS pipe N1, the drain electrode of described PMOS pipe P5 connects the drain electrode of described NMOS pipe N3.

3. high PSRR according to claim 2, low-power consumption reference current generating circuit, it is characterized in that: also comprise a start-up circuit, described start-up circuit comprises PMOS pipe Pa, PMOS pipe Pb, PMOS pipe Pc, PMOS pipe Pd and PMOS pipe Pe and capacitor C 1 and capacitor C 2, power vd D connects described PMOS pipe Pa and the source electrode of PMOS pipe Pe and the positive pole of capacitor C, the grid of described PMOS pipe Pa connects the grid of described PMOS pipe P1, the negative pole of described capacitor C connects the drain electrode of described PMOS pipe Pa and PMOS pipe Pb and the grid of described PMOS pipe Pb and PMOS pipe Pe, the source electrode of described PMOS pipe Pb connects the drain and gate of described PMOS pipe Pc, the source electrode of described PMOS pipe Pc connects the drain and gate of described PMOS pipe Pd, the source electrode of described PMOS pipe Pd and the negative pole of described capacitor C 2 are connected power supply GND, the drain electrode of described PMOS pipe Pe connects the drain electrode of positive pole and the described PMOS pipe P4 of described capacitor C 2.

4. a high PSRR, the low-power consumption reference voltage generating circuit, it is characterized in that: comprise that one according to the described reference current generating circuit of claim 1-3 any one, one negative temperature coefficient voltage generation unit, N positive temperature coefficient (PTC) voltage generation unit and N+1 PMOS pipe, N is positive integer, the output terminal of described the 1st positive temperature coefficient (PTC) voltage generation unit is as the output terminal of described reference voltage generating circuit, one end of described the 1st positive temperature coefficient (PTC) voltage generation unit described the 1st the PMOS pipe of connecting is connected to power vd D, the other end of described the 1st positive temperature coefficient (PTC) voltage generation unit connects the output terminal of described the 2nd positive temperature coefficient (PTC) voltage generation unit, by that analogy, one end of described N positive temperature coefficient (PTC) voltage generation unit described N the PMOS pipe of connecting is connected to power vd D, the other end of described N positive temperature coefficient (PTC) voltage generation unit connects the output terminal of described negative temperature coefficient voltage generation unit, the grid of described N+1 PMOS pipe all is connected to the drain electrode of described N+1 PMOS pipe and the power end of described reference current generating circuit, the output head grounding of described reference current generating circuit.

5. high PSRR according to claim 4, the low-power consumption reference voltage generating circuit, it is characterized in that: described positive temperature coefficient (PTC) voltage generation unit comprises NMOS pipe M1 and NMOS pipe M2, the drain electrode of described NMOS pipe M1 is as an end of described positive temperature coefficient (PTC) voltage generation unit and connect described NMOS pipe M1 and the grid of NMOS pipe M2, the source electrode of described NMOS pipe M1 is as the output terminal of described positive temperature coefficient (PTC) voltage generation unit and connect the drain electrode of described NMOS pipe M2, the source electrode of described NMOS pipe M2 is as the other end of described positive temperature coefficient (PTC) voltage generation unit.

6. high PSRR according to claim 4, low-power consumption reference voltage generating circuit, it is characterized in that: described negative temperature coefficient voltage generation unit comprises a NMOS pipe M3, the drain electrode of described NMOS pipe M3 is as the output terminal of described negative temperature coefficient voltage generation unit and connect the grid of described NMOS pipe M3, and the source electrode of described NMOS pipe M3 is connected to ground.

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