CN203313135U - Current-limiting power amplification driving circuit in power line carrier communication - Google Patents
Current-limiting power amplification driving circuit in power line carrier communication Download PDFInfo
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Abstract
The utility model relates to a current-limiting power amplification driving circuit in power line carrier communication, which is used for realizing power amplification of power line carrier sending signals and coupling the signals on a power line. The current-limiting power amplification driving circuit is characterized by comprising a current-limiting blocking direct input circuit, a first-stage biasing amplification circuit, a second-stage current-limiting amplification circuit, a third-stage power driving circuit, a feedback circuit and a power line carrier signal coupling circuit. The current-limiting blocking direct input circuit in the circuit realizes current-limiting protection for power amplification current input stage; the second-stage current-limiting amplification circuit improves base voltage lower limit of a triode Q4 in the third-stage power driving circuit, and limits the maximum base current of the triode Q4, so that the power amplification circuit is prevented from entering a working dead zone on which Q4 is conducted all the time; the second-stage current-limiting amplification circuit has current-limiting effect for the third-stage power driving circuit, overload damage of the triode is prevented, and the circuit is suitable for variable carrier load impedance in actual on-site application.
Description
Technical Field
The utility model relates to a power line carrier communication's current-limiting power amplification drive circuit belongs to power line carrier communication technical field.
Background
Because the power line carrier communication has the characteristics of no need of additionally erecting a communication line, automatic adaptation to user distribution, low cost and easy networking, the power line carrier communication is a preferred scheme of the current low-voltage automatic meter reading communication and is also a main mode of the current distribution network communication. In order to achieve a good power line carrier communication effect, the design of a power amplification driving circuit for transmitting signals in power line carrier communication is one of the important problems in the research of power line carrier communication technology. The power amplification circuit for the power line carrier communication transmission signal needs to amplify the power of the carrier communication transmission signal, improve the signal amplitude, prolong the transmission distance, ensure low harmonic and low distortion of the transmission signal, operate reliably for a long time, and avoid current overload damage. The invention discloses a power amplification circuit for a power line multi-carrier communication system (application number: CA 201110458555.7), and provides a power amplification driving circuit for power line carrier communication, as shown in fig. 1. However, this circuit has three problems in practical use. Firstly, the input stage of the power amplifier circuit has no current-limiting protection. At the moment of starting transmission, the input capacitor C1 is suddenly charged, which may generate a large instantaneous current, and damage the carrier signal generating circuit connected to the power amplifying circuit. Second, the power amplifier circuit may enter a dead zone of operation and fail to output a power driving signal. When the power amplifier enters a working dead zone, the R7 resistor in fig. 1 pulls down the base voltage of the triode Q4, so that the Q4 always tends to be saturated and conducted, the triodes Q2 and Q3 are difficult to conduct to charge C3, and the connecting point of the resistors R8 and R9 maintains a low level and cannot output a carrier waveform. Thirdly, if the power amplifier circuit does not enter a dead zone, but the output load impedance is small, the three-level transistors Q3 and Q4 at the final stage have no current limiting measures, and heating damage of the three-level transistors Q3 and Q4 caused by excessive power consumption is easy to occur.
Disclosure of Invention
The utility model aims at providing a power line carrier communication's current-limiting power amplification drive circuit, this circuit will solve existing power line carrier communication's power amplification drive circuit's problem, realize the current-limiting to the input, avoid getting into the work blind spot, realize the current-limiting protection of last stage triode drive, avoid leading to triode overload damage because of carrier load impedance is little among the practical application.
The utility model provides a pair of power line carrier communication's current-limiting power amplification drive circuit, a serial communication port, power amplification drive circuit includes current-limiting blocking input circuit, first order biasing amplifier circuit, second level current-limiting amplifier circuit, third level power drive circuit, feedback circuit and power line carrier signal coupling circuit.
The current-limiting and DC-blocking input circuit comprises a resistor Ri and a capacitor C1, the resistor Ri is connected to the input end of the power amplification driving circuit, and the capacitor C1 and the resistor Ri are connected in series and then connected to the input end of the first-stage bias amplification circuit.
The first-stage bias amplifying circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an NPN triode Q1 and a capacitor C2. The resistor R1 and the resistor R2 are connected in series between a power supply VCC and a ground wire GND, the connection node of the resistor R1 and the resistor R2 is used as the input end of the first-stage bias amplifying circuit to be connected with the capacitor C1 of the current-limiting and direct-blocking input circuit and the base electrode of the triode Q1, the resistor R3 is connected between the power supply VCC and the collector electrode of the triode Q1, and the resistor R4 and the capacitor C2 are connected in series between the emitter electrode of the triode Q1 and the ground wire GND.
The second stage current-limiting amplifying circuit amplifies the input signal, controls the signal output of the third stage power driving circuit and limits the third stage powerThe input end of the circuit is connected with the collector electrode of a triode Q1 in the first-stage bias amplification circuit, and the three output ends of the circuitV3、V4AndV5the base electrodes of the triodes Q3 and Q4 in the third-stage power driving circuit and the output end of the third-stage power driving circuit are respectively connected.
The third-stage power driving circuit comprises an NPN triode Q3, a resistor R10, a resistor R11 and a PNP triode Q4 which are sequentially connected in series between a power supply VCC and a ground wire GND, wherein the base electrode of the triode Q3 is connected with the output end of the second-stage current-limiting amplifying circuitV3The collector of the triode Q3 is connected with a power supply VCC, the emitter of the triode Q3 is connected with a resistor R10, and the base of the triode Q4 is connected with the output end of the second stage current-limiting amplifying circuitV4The emitter of the triode Q4 is connected with the resistor R11, the collector of the triode Q4 is connected with the ground wire GND, and the serial connection node of the resistor R10 and the resistor R11 is used as the output end of the third-stage power driving circuit and is connected with the output end of the second-stage current-limiting amplifying circuitV5A resistor R5 in the feedback circuit and a capacitor C4 of the power line carrier signal coupling circuit.
The feedback circuit comprises a resistor R5, and a resistor R5 is connected between the emitter of the transistor Q1 in the first stage bias amplifying circuit and the output end of the third stage power driving circuit.
The power line carrier signal coupling circuit comprises a capacitor C4, a transformer T1 and a capacitor C5, wherein the capacitor C4 is connected between the output end of the third-stage power driving circuit and one end of a low-voltage side coil of the transformer T1, the other end of a low-voltage side coil of the transformer T1 is connected with a ground wire GND, and one end of a high-voltage side coil of the transformer T1 is connected with the capacitor C5 in series and then is respectively connected with the other end of the high-voltage side coil of the transformer T1 to be connected with two ends of an alternating.
The second stage current-limiting amplifying circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R12, a capacitor C3, a diode D1, a diode D2A, a diode D2B, a P-MOS tube Q2 and an NPN triode Q5, wherein the gate of the P-MOS tube Q2 is connected as the input of the second stage current-limiting amplifying circuitIn the first-stage bias amplifying circuit, a collector of a triode Q1, a resistor R8, a capacitor C3, a gate and a drain of a P-MOS transistor Q2, an anode of a diode D1, a drain of the P-MOS transistor Q2, a resistor R6, a cathode of a diode D1 and a collector of a triode Q5, a resistor R12, a base of a triode Q5, a diode D2A and a diode D2B which are connected in series in an anode-to-cathode direction and then connected between an emitter of a triode Q5 and a ground GND, a resistor R7, an emitter of a triode Q5 and a GND, a drain of the P-MOS transistor Q2 connected to one end of a resistor R9, the other end of a resistor R9, a drain of the P-MOS transistor Q2 and a collector of a triode Q5 are respectively used as output terminals of the second-stage current-limiting amplifying circuitV5、V3 andV4。
resistance R6 and diode D1's position can exchange among the second level current-limiting amplifier circuit, and resistance R6 is connected between P-MOS pipe Q2's drain electrode and diode D1's positive pole promptly, and triode Q5's projecting pole is connected to diode D1's negative pole.
The beneficial effects of the utility model are represented as three. Firstly, compared with the existing power amplifier circuit, the current-limiting and DC-blocking input circuit increases a resistor Ri, so that the charging current of the carrier signal generation circuit to the input capacitor C1 can be limited at the moment of starting and sending, and the circuit is prevented from being damaged.
Secondly, the second stage current-limiting amplifying circuit sets the base voltage of a transistor Q4 in the third stage power driving circuit through a transistor Q5, resistors R12 and R7 and diodes D2A and D2BV 4Lower limit, i.e.
Wherein,V D A2andV D B2are respectively provided withIs the conduction voltage drop of diodes D2A and D2B,V BE_Q5andV CE(sat)_Q5the base-emitter turn-on voltage drop and the collector-emitter saturation turn-on voltage drop of transistor Q5, respectively. And base current of transistor Q4I B_Q4The upper limit is also limited, i.e., the collector current of transistor Q5 cannot be exceededI 4：
Therefore, the circuit prevents the triode Q4 from entering a state of being always conducted, the voltage of the output end of the third-stage power driving circuit cannot be always pulled down by the triode Q4, and finally the whole power amplifying circuit is prevented from entering a work dead zone.
Third, the added resistors R8 and R9 can limit the maximum output current of the third stage power driving circuit, and prevent the transistors Q3 and Q4 from being damaged by overload. The maximum current and maximum power consumption of the transistors Q3 and Q4 occur at the output end of the third stage power driving circuitVAnd 5 corresponds to the carrier band having an impedance of 0. When the transistor Q4 is turned off and the P-MOS transistor Q2 and the transistor Q3 are turned on, if the on voltage drop of the P-MOS transistor Q2 and the base current of the transistor Q3 are neglected, the maximum current peak of the transistor Q3 at this time is:
whereinV S Is the voltage of the power supply VCC,
for the node when the carrier load impedance is 0VA dc bias voltage of 5 a and a dc bias voltage,V BE_Q3is the base-emitter turn-on voltage drop of transistor Q3,I 4is the collector current of transistor Q5. When P-MOS transistor Q2 and triodeWhen the transistor Q4 is turned on and the Q3 is turned off, the maximum current peak of the transistor Q4 is:
based on the charge balance of the charge and discharge of the coupling capacitor, the peak average currents of Q3 and Q4 can be obtained as follows:
the formula for calculating the peak average current of the transistors Q3 and Q4 can be seen as follows: increasing the resistance R8 can be achieved by decreasingI PK_Q3Decreasing the maximum output current of Q3 and Q4; the reduction of the resistance R9 can be simultaneously reducedI PK_Q3AndI PK_Q4thereby reducing the maximum output current of Q3 and Q4; decreasing the resistance R6 or increasing the resistance R11 can decreaseI PK_Q4Thereby reducing the maximum output current of Q3 and Q4; when the resistor R7 is increased, the collector current of the transistor Q5I 4Decrease, can reduceI PK_Q4Thereby reducing the maximum output current of Q3 and Q4. However, the magnitude of the resistor R6 will affect the crossover distortion of the output signal of the third stage power driving circuit. While a larger resistor R11 consumes more power across resistor R11. Therefore, the utility model discloses power amplifier circuit passes through resistance R7, R8 and R9, can adjust and restrict triode Q3 and Q4's peak value average current, realizes preventing triode Q3 and Q4 overload damage's effect. In addition, compare the existing power amplifier circuit of fig. 1, the utility model discloses the open-loop amplification factor of first order bias amplifier circuit and second level current-limiting amplifier circuit can be reduced to the introduction of R8 and R9 in the circuit, but this open-loop amplification factor is still very big, and when carrier load impedance is great, the introduction of R8 and R9 can not influence the amplified output waveform and the power of carrier signal.
The utility model discloses the impedance that electric capacity corresponds in the carrier signal frequency range is less in the circuit, can ignore, then the utility model discloses power amplifier circuit's magnification is about:
the utility model discloses in the circuit, resistance R6 and diode D1's position can exchange, as long as keep diode D1's positive pole to the negative pole direction and second grade current-limiting amplifier circuit electric current from the VCC to the direction of ground wire GND unanimously can.
Drawings
Fig. 1 is a current-limiting power amplification driving circuit for power line carrier communication.
Fig. 2 is a schematic diagram of a current-limiting power amplification driving circuit for power line carrier communication according to the present invention.
Fig. 3 is a circuit diagram of an embodiment of a current-limiting power amplification driving circuit for power line carrier communication according to the present invention.
Detailed Description
The specific implementation mode is as follows:
the circuit diagram of the specific embodiment of the current-limiting power amplification driving circuit for power line carrier communication of the present invention is shown in fig. 3. The utility model discloses power amplification circuit includes current-limiting blocking input circuit, first order bias amplifier circuit, second level current-limiting amplifier circuit, third level power drive circuit, feedback circuit and power line carrier signal coupling circuit. The voltage of the power supply terminal VCC isV S = 12V。
The utility model discloses current-limiting DC blocking input circuit includes 10 omega's resistance Ri and 0.47μAnd F, a capacitor C1 and a resistor Ri are connected to the input end of the power amplification circuit, and a capacitor C1 and the resistor Ri are connected in series and then connected to the input end of the first-stage bias amplification circuit. When the sending is started, when 3V voltage difference exists between the voltage input into the power amplifier circuit and the voltage of the left end of the capacitor C1, the resistor Ri can limit the instantaneous current to 300 mA.
The bias amplifying circuit of the first stage of the embodiment comprises a 6.8k omega resistor R1, a 6.8k omega resistor R2, a 2k omega resistor R3, a 100 omega resistor R4, a BC817 type NPN triode Q1 and a 0.1μAnd an F capacitor C2, wherein a resistor R1 and a resistor R2 are connected in series with each other and are respectively connected with a power supply VCC and a ground GND, a connection point of the resistors R1 and R2 is used as an input end of the first-stage bias amplification circuit and is connected with the capacitor C1 and the base of the triode Q1, a resistor R3 is connected between the power supply VCC and the collector of the triode Q1, and a resistor R4 and a capacitor C2 are connected in series with each other and are respectively connected with the emitter of the triode Q1 and the ground GND. Assume that the base-emitter turn-on voltage drop of transistor Q1V BE_Q1= 0.7V, neglecting the dc current at R5, the output terminal of the third stage power driving circuitVThe dc bias voltage of 5 is:
the second stage current-limiting amplifying circuit comprises a 33 omega resistor R6, a 51 omega resistor R7, a 51 omega resistor R8, a 33 omega resistor R9, a 10k omega resistor R12, a 22pF capacitor C3, a 1N4148 type diode D1, a BAV99 device comprising two diodes D2A and D2B, a BSS84 type P-MOS transistor Q2 and a BC817 type NPN triode Q5. The gate of the P-MOS transistor Q2 is connected to the collector of the transistor Q1, and the source of the P-MOS transistor Q2 is connected to the power VCC via the resistor R8. The capacitor C3 is connected between the gate and the drain of the P-MOS transistor Q2. The anode of the diode D1 is connected with the drain of the P-MOS tube. The resistor R6 is connected between the cathode of the diode D1 and the collector of the transistor Q5. The base of the triode Q5 is connected with a power supply VCC through a resistor R12, and is connected with a ground wire GND after being connected in series along the direction from the anode to the cathode through a diode D2A and a diode D2B, and the emitter of the triode Q5 is connected with the ground wire GND after passing through a resistor R7. The resistor R9 is connected between the drain of the P-MOS transistor Q2 and the output end of the third stage power driving circuit.
Embodiment third stage power driving circuit includes BD237 type NPN transistor Q3, 1 Ω resistor R10, 1 Ω resistor R11, and BD238 type PNP transistor Q4 connected in series in that order between power source VCC and ground GND. The base electrode of the triode Q3 is connected with the drain electrode of the P-MOS transistor Q2, the collector electrode of the triode Q3 is connected with a power supply VCC, and the emitter electrode of the triode Q3 is connected with the resistor R10. The base electrode of the triode Q4 is connected with the collector electrode of the triode Q5, the emitter electrode of the triode Q4 is connected with the resistor R11, and the collector electrode of the triode Q4 is connected with the ground wire GND. The serial connection node of the resistor R10 and the resistor R11 is used as the output end of the third-stage power driving circuit and is connected with the resistor R5 and the capacitor C4 in the feedback circuit.
The feedback circuit of the embodiment includes a 560 Ω resistor R5, and a resistor R5 is connected between the emitter of transistor Q1 and the output of the third stage power driver circuit.
The embodiment of the power line carrier signal coupling circuit comprises a power line carrier signal coupling circuit 3.3μF capacitor C4, transformer T1 and 0.22μF. And a safety capacitor C5 rated at 275V alternating voltage. The primary side and the secondary side of the transformer T1 are all 22 turns, and the transformer T1 has the characteristics of low magnetic leakage, low loss and rated working frequency band larger than carrier signal frequency. The capacitor C4 is connected between the output end of the third-stage power driving circuit and one end of the low-voltage side coil of the transformer T1, the other end of the low-voltage side coil of the transformer T1 is connected with the ground GND, one end of the high-voltage side coil of the transformer T1 is connected with the capacitor C5 in series, and then the other end of the high-voltage side coil of the transformer T1 and the other end of the capacitor C5 are respectively connected to two ends of an alternating current power line of the commercial power 220V.
The positions of the diode D1 and the resistor R6 in the second stage current-limiting amplifying circuit of the embodiment can be exchanged, namely R6 is connected between the drain of the P-MOS tube and the anode of the diode D1, and the cathode of the diode D1 is connected with the emitter of the triode Q5.
According to the embodiment parameters, if diode D is assumed2A and D2BV D A2 = V D B2= 0.7V, base-emitter conduction voltage drop of triode Q5V BE_Q4= 0.7V, collector-emitter saturation conduction voltage drop of triode Q5V CE(sat)_Q4= 0.7V, then
Base voltage of triode Q4 in third stage power driving circuitV 4The lower limit is 1.4V. Furthermore, the base current of the transistor Q4I B_Q4The upper limit is also limited, i.e., the collector current of transistor Q5 cannot be exceededI 4Namely:
therefore, the triode Q4 is prevented from entering saturation conduction, and the whole power amplifier circuit is prevented from entering a work dead zone.
Assume that the output of the third stage power driving circuit of the embodimentVAfter 5, the impedance corresponding to the carrier frequency band is 0, when the transistor Q4 is turned off and the P-MOS transistor Q2 and the transistor Q3 are turned on, if the conduction voltage drop of the P-MOS transistor Q2 and the base current of the transistor Q3 are ignored, and the base-emitter conduction voltage drop of the transistor Q3 is taken out when the collector has a larger currentV BE_Q3If =1.0V, the maximum current peak of the transistor Q3 at this time is:
this current value is less than the maximum allowed collector conduction current value of the BD237 type triode.
When the P-MOS transistor Q2 and the transistor Q3 are turned off and the transistor Q4 is turned on, the voltage drop of the diode D1 is obtainedV D1= 0.7V, the emitter-base conduction voltage drop of the triode Q4 is taken under the condition that the collector has larger currentV EB_Q4=1.0V, amplification factor of triode Q4 is takenβ Q4= 100, the maximum current peak of the transistor Q4 is:
the peak average currents for Q3 and Q4 thus can be found as:
the embodiment of the utility model provides a limit triode Q3 and Q4's average current at 0.289A to avoided triode Q3 and Q4 to generate heat because of the electric current is too big and damage.
The embodiment of the utility model provides a be applied to power amplification and power line coupling based on Orthogonal Frequency Division Multiplexing (OFDM) modulation mode's power line carrier sending signal, the used frequency band scope of carrier signal is 220 kHz to 280kHz, and selected device satisfies the carrier frequency band requirement. Input the embodiment of the utility model provides a power amplifier circuit's carrier signal peak-to-peak value is within 0.8V, and the utility model discloses the magnification is about:
therefore, the peak-to-peak value of the output signal of the power amplifier is within 5.28V. Furthermore, the test data obtained by the specific circuit test according to the embodiment of the present invention is consistent with the above analysis. When the carrier load impedance is larger, the power amplifier circuit can normally output the amplified carrier signal waveform and has smaller distortion degree. When the carrier load impedance is small, the output current of the power amplifier is restrained, and the power amplifier triode is protected. Meanwhile, although the amplitude of the transmitted carrier signal is reduced and the degree of distortion is increased, the signal transmission capability is still certain.
Claims (3)
1. A current-limiting power amplification driving circuit for power line carrier communication is characterized in that the power amplification driving circuit comprises a current-limiting blocking input circuit, a first-stage bias amplifying circuit, a second-stage current-limiting amplifying circuit, a third-stage power driving circuit, a feedback circuit and a power line carrier signal coupling circuit, wherein the current-limiting blocking input circuit, the first-stage bias amplifying circuit, the second-stage current-limiting amplifying circuit, the third-stage power driving circuit, the feedback circuit and the power line carrier; wherein,
the current-limiting and DC-blocking input circuit comprises a resistor Ri and a capacitor C1, the resistor Ri is connected to the input end of the power amplification driving circuit, and the capacitor C1 and the resistor Ri are connected in series and then connected to the input end of the first-stage bias amplification circuit;
the first-stage bias amplifying circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an NPN triode Q1 and a capacitor C2, wherein the resistor R1 and the resistor R2 are connected in series between a power supply VCC and a ground wire GND, a connection node of the resistor R1 and the resistor R2 is used as an input end of the first-stage bias amplifying circuit to be connected with the capacitor C1 of the current-limiting and DC-blocking input circuit and simultaneously connected with a base electrode of the triode Q1, the resistor R3 is connected between the power supply VCC and a collector electrode of the triode Q1, and the resistor R4 and the capacitor C2 are connected in series between an emitter electrode;
the second stage current-limiting amplifying circuit amplifies the input signal, controls the signal output of the third stage power driving circuit and limits the current of the third stage power driving circuit, the input end of the circuit is connected with the collector of the triode Q1 in the first stage bias amplifying circuit, and the three output ends of the circuitV3、V4AndV5the base electrodes of triodes Q3 and Q4 in the third-stage power driving circuit and the output end of the third-stage power driving circuit are respectively connected;
the third-stage power driving circuit comprises an NPN triode Q3, a resistor R10, a resistor R11 and a PNP triode Q4 which are sequentially connected in series between a power supply VCC and a ground wire GND, wherein the base electrode of the triode Q3 is connected with the output end of the second-stage current-limiting amplifying circuitV3The collector of the triode Q3 is connected with a power supply VCC, the emitter of the triode Q3 is connected with a resistor R10, and the base of the triode Q4 is connected with the output end of the second stage current-limiting amplifying circuitV4The emitter of the triode Q4 is connected with the resistor R11, the collector of the triode Q4 is connected with the ground wire GND, and the serial connection node of the resistor R10 and the resistor R11 is used as the output end of the third-stage power driving circuit and is connected with the output end of the second-stage current-limiting amplifying circuitV5A resistor R5 in the feedback circuit and a capacitor C4 of the power line carrier signal coupling circuit;
the feedback circuit comprises a resistor R5, and a resistor R5 is connected between an emitter of a transistor Q1 in the first stage bias amplifying circuit and an output end of the third stage power driving circuit;
the power line carrier signal coupling circuit comprises a capacitor C4, a transformer T1 and a capacitor C5, wherein the capacitor C4 is connected between the output end of the third-stage power driving circuit and one end of a low-voltage side coil of the transformer T1, the other end of a low-voltage side coil of the transformer T1 is connected with a ground wire GND, and one end of a high-voltage side coil of the transformer T1 is connected with the capacitor C5 in series and then is respectively connected with the other end of the high-voltage side coil of the transformer T1 to be connected with two ends of an alternating.
2. The current-limiting power amplification driving circuit for power line carrier communication of claim 1, wherein the second stage current-limiting amplification circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R12, a capacitor C3, a diode D1, a diode D2A, a diode D2B, a P-MOS Q2 and an NPN transistor Q5, wherein a gate of the P-MOS Q2 is connected as an input terminal of the second stage current-limiting amplification circuit to a collector of the transistor Q1 in the first stage bias amplification circuit, the resistor R8 is connected between a power source VCC and a source of the P-MOS Q2, the capacitor C3 is connected between the gate and a drain of the P-MOS Q2, an anode of the diode D1 is connected to a drain of the P-MOS Q2, the resistor R6 is connected between a cathode of the diode D1 and a collector of the transistor Q5, and the resistor R12 is connected between the base of the power source VCC and a base of the transistor Q5, The diode D2A and the diode D2B are connected in series along the direction from the anode to the cathode and then connected between the emitter of the triode Q5 and the ground GND, the resistor R7 is connected between the emitter of the triode Q5 and the ground GND, one end of the resistor R9 is connected with the drain of the P-MOS transistor Q2, and the other end of the resistor R9, the drain of the P-MOS transistor Q2 and the collector of the triode Q5 are respectively used as the output end of the second stage current-limiting amplifying circuitV5、V3 andV4。
3. the current-limiting power amplification driving circuit for power line carrier communication of claim 2, wherein the positions of the resistor R6 and the diode D1 in the second stage of current-limiting amplification circuit are interchanged, the resistor R6 is connected between the drain of the P-MOS transistor Q2 and the anode of the diode D1, and the cathode of the diode D1 is connected to the emitter of the transistor Q5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013203794155U CN203313135U (en) | 2013-06-28 | 2013-06-28 | Current-limiting power amplification driving circuit in power line carrier communication |
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| CN2013203794155U CN203313135U (en) | 2013-06-28 | 2013-06-28 | Current-limiting power amplification driving circuit in power line carrier communication |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103338012A (en) * | 2013-06-28 | 2013-10-02 | 盛吉高科（北京）科技有限公司 | Current limiting power amplification driving circuit for power line carrier communication |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103338012A (en) * | 2013-06-28 | 2013-10-02 | 盛吉高科（北京）科技有限公司 | Current limiting power amplification driving circuit for power line carrier communication |
| CN103338012B (en) * | 2013-06-28 | 2016-01-20 | 盛吉高科（北京）科技有限公司 | A kind of current-limited power amplification driving circuit of power line carrier communication |
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