CN203299814U - Novel board design - Google Patents
Novel board design Download PDFInfo
- Publication number
- CN203299814U CN203299814U CN2013203513842U CN201320351384U CN203299814U CN 203299814 U CN203299814 U CN 203299814U CN 2013203513842 U CN2013203513842 U CN 2013203513842U CN 201320351384 U CN201320351384 U CN 201320351384U CN 203299814 U CN203299814 U CN 203299814U
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- Prior art keywords
- board
- signal line
- master chip
- sas
- signal wire
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- Expired - Fee Related
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- 230000002093 peripheral effect Effects 0.000 abstract 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
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Abstract
A novel board design comprises a board. SAS interfaces, a master chip, a memory slot and a PCIE (peripheral component interface express) signal line are all arranged on the board. The SAS interfaces used for connecting a hard-disk backboard are arranged on the right side of the board. The master chip arranged on the left side of the SAS interfaces shortens the length of routing of an SAS signal line. The memory slot is arranged on the left side of the PCIE signal line which is arranged between the master chip and the memory slot, and the PCIE signal line is lengthened within the scope of standard. Due to the fact that positions of the master chip and a memory chip are exchanged on the board and the PCIE signal line is lengthened, the routing of the SAS signal line is greatly shortened, signal attenuation brought by excessively long routing of the signal line is avoided, and the risk of disk falling is reduced.
Description
Technical field
The utility model relates to field of computer, is specifically related to a kind of novel board design.
Background technology
Existing board is considered the reason of PCIE signal wire outlet, master chip is placed on to the left side of board, causes SAS signal wire cabling long, causes the SAS loss of signal serious, and the risk of dish is arranged when connecting hard disk backboard.
The utility model content
The utility model, for the weak point that prior art exists, provides a kind of novel board design rational in infrastructure.
board design disclosed in the utility model, the technical scheme that addresses the above problem employing is as follows: comprise a board, on described board, be provided with the SAS interface, master chip, memory bank and PCIE signal wire, wherein the SAS interface is for connecting the right side that hard disk backboard is arranged on board, master chip is arranged on the length that SAS signal wire cabling has been shortened in SAS interface left side, memory bank is arranged on PCIE signal wire left side, and the PCIE signal wire is arranged between master chip and memory bank, and the PCIE signal wire elongates in critical field, described board is provided with golden finger below simultaneously.
The beneficial effect that novel board design disclosed in the utility model has is: this novel board is by master chip and memory bank location swap, the PCIE signal wire elongates, greatly shorten the length of SAS signal wire cabling, avoid the long signal attenuation that brings of signal wire cabling, reduced and fallen to coil risk.
The accompanying drawing explanation
Accompanying drawing 1 is the structured flowchart of board design described in the utility model.
Embodiment
Below in conjunction with accompanying drawing, novel board design disclosed in the utility model is described in further details.
Board design disclosed in the utility model, its structure as shown in Figure 1, comprise a board, on described board, be provided with SAS interface, master chip, memory bank and PCIE signal wire, wherein the SAS interface is for connecting the right side that hard disk backboard is arranged on board, master chip is arranged on the length that SAS signal wire cabling has been shortened in SAS interface left side, memory bank is arranged on PCIE signal wire left side, and the PCIE signal wire is arranged between master chip and memory bank, and the PCIE signal wire elongates in critical field; Described board below is provided with golden finger.
In original board structure, consider the reason that the PCIE signal wire occurs, memory bank is arranged between SAS interface and master chip, make SAS signal wire cabling long, as can be known from the project organization of novel board, in this board by master chip and memory bank location swap, the PCIE signal wire elongates within critical field, so greatly shortened the length of SAS signal wire cabling, the decay of avoiding signal to bring because cabling is long, lowered and fallen to coil risk.
Except technical characterictic described in the utility model, be the known technology of those skilled in the art.
Claims (1)
1. novel board design, comprise a board, it is characterized in that, on described board, be provided with SAS interface, master chip, memory bank and PCIE signal wire, wherein the SAS interface is for connecting the right side that hard disk backboard is arranged on board, and master chip is arranged on SAS interface left side, memory bank is arranged on PCIE signal wire left side, and the PCIE signal wire is arranged between master chip and memory bank, and the PCIE signal wire elongates in critical field, and described board is provided with golden finger below simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203513842U CN203299814U (en) | 2013-06-19 | 2013-06-19 | Novel board design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203513842U CN203299814U (en) | 2013-06-19 | 2013-06-19 | Novel board design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203299814U true CN203299814U (en) | 2013-11-20 |
Family
ID=49575812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203513842U Expired - Fee Related CN203299814U (en) | 2013-06-19 | 2013-06-19 | Novel board design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203299814U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105975427A (en) * | 2016-05-18 | 2016-09-28 | 南京国睿中数电子科技有限公司 | PCIE dual-mode system based on SAS interface |
| CN107729270A (en) * | 2017-10-24 | 2018-02-23 | 郑州云海信息技术有限公司 | A kind of NVMe hard disk backboards and its design method based on NVMe agreements |
-
2013
- 2013-06-19 CN CN2013203513842U patent/CN203299814U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105975427A (en) * | 2016-05-18 | 2016-09-28 | 南京国睿中数电子科技有限公司 | PCIE dual-mode system based on SAS interface |
| CN107729270A (en) * | 2017-10-24 | 2018-02-23 | 郑州云海信息技术有限公司 | A kind of NVMe hard disk backboards and its design method based on NVMe agreements |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131120 Termination date: 20170619 |