CN203260570U - 一种基于框架腐蚀凸点的无载体式新型封装件 - Google Patents

一种基于框架腐蚀凸点的无载体式新型封装件 Download PDF

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CN203260570U
CN203260570U CN201220479169.6U CN201220479169U CN203260570U CN 203260570 U CN203260570 U CN 203260570U CN 201220479169 U CN201220479169 U CN 201220479169U CN 203260570 U CN203260570 U CN 203260570U
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salient point
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孙青秀
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China Chippacking Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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Abstract

本实用新型涉及一种基于框架腐蚀凸点的无载体式新型封装件，属于集成电路封装技术领域。引线框架正反面设有金属凸点，芯片与引线框架通过粘片胶相连，键合线直接从芯片打到金属凸点上，引线框架上是粘片胶和金属凸点，粘片胶上是芯片，芯片上的焊点与金属凸点间的焊线是键合线，塑封体包围了引线框架、金属凸点、粘片胶、芯片、键合线构成了电路的整体；芯片、金属凸点、键合线、引线框架构成了电路的电源和信号通道；本实用新型只需用电镀的方法在金属板上制作凸点，制作周期短，极大降低成本；凸点的排布以及I/O的密集程度上得到极大的提升，防拖拉结构使封装可靠性得到保证，在很大程度上克服目前QFN/DFN系列封装件制作工艺的局限。

Description

一种基于框架腐蚀凸点的无载体式新型封装件
技术领域
本实用新型涉及一种基于框架腐蚀凸点的无载体式新型封装件，属于集成电路封装技术领域。 
背景技术
近几年随着通讯及便携式小型数码电子产品的产生，四面扁平无引脚封装的QFN及双扁平无引脚封装的DFN迅速发展起来的，QFN/DFN封装适用于高频、宽带、低噪声、高导热、小体积，高速度等、电性要求的中小规模集成电路的封装；QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率，同时，封装由于引线短小、塑封体尺寸小、封装体薄，可以使CPU体积缩小30％-50％，所以它能提供卓越的电性能，还提供了出色的散热性能。 
但是，普通的QFN/DFN封装主要存在以下不足：框架载体的QFN/DFN产品需要根据芯片尺寸及电路连通设计框架图形，再用腐蚀等方法将框架加工成设计好的图形，设计及制作周期长，成本比较高。并且目前的QFN/DFN系列封装件在凸点的排布以及I/O的密集程度上也由于框架设计及框架制造工艺而有所限制，封装可靠性也得不到保证。 
实用新型内容
为了克服上述现有技术存在的问题，本实用新型提供一种基于框架腐蚀凸点的无载体式新型封装件，不再需要根据芯片尺寸及电路连通设计框架图形及加工框架，只需用电镀的方法在金属板上制作凸点，制作周期短，极大降低成本；凸点的排布以及I/O的密集程度上得到极大的提升，防拖拉结构使封装可靠性得到保证，在很大程度上克服目前QFN/DFN系列封装件制作工艺的局限。 
为了实现上述目的，本实用新型采用的技术方案：一种基于框架腐蚀凸点的无载体式新型封装件包括引线框架1、金属凸点2、粘片胶4、芯片5、键合线6、塑封体7；其中引线框架1正反面设有金属凸点2，芯片5与引线框架1通过粘片胶4相连，键合线6直接从芯片5打到金属凸点2上，引线框架1上是粘片胶4和金属凸点2，粘片胶4上是芯片5，芯片5上的焊点与金属凸点2间的焊线是键合线6，对芯片5和金属凸点2的键合线6起到了支撑和保护作用的塑封体7包围了引线框架1、金属凸点2、粘片胶4、芯片5、键合线6构成了电路的整体；芯片5、金属凸点2、键合线6、引线框架1构成了电路的电源和信号通道。 
所述的金属凸点2可以为单圈也可以为多圈；金属凸点2通过电镀的方法形成：金属凸点2可以选择Ag、NiPdAu或NiPd；所述的粘片胶4可以用胶膜片(DAF)代替。 
本实用新型的有益效果：本实用新型采用普通框架即可进行产品制作流程，无需过多加上框架载体，缩短设计及制作周期，降低成本；在金属板的正反面使用电镀的方法制作凸点，结合蚀刻工艺可实现在框架上自然形成图形，无需光照蚀刻；蚀刻后的金属板与原有部分形成凹槽，在塑封后形成有效的防拖拉结构，有效提高封装可靠性：在凸点排布及I/O数不受框架设计及制作限制的前提下，实现了凸点排布可任意定义，更好得实现芯片与载体的互联；更可实现双圈或多圈金属凸点排布，使I/O更加密集，成本更低，封装可靠性更高；摒弃以往使用光刻胶进行光照腐蚀的工艺，极大降低成本，提高生产效率。 
附图说明
图1本实用新型的引线框架剖面图； 
图2本实用新型的框架正反面电镀凸点后剖面图； 
图3本实用新型的框架腐蚀图形后剖面图； 
图4本实用新型的上芯后剖面图； 
图5本实用新型的压焊后剖面图； 
图6本实用新型的塑封后剖面图； 
图7本实用新型的去除框架后的成品剖面图。 
图中：1-引线框架、2-金属凸点、3-蚀刻区域、4-粘片胶或胶膜片(DAF)、5-芯片、6-键合线、7-塑封体 
具体实施方式
下面结合附图和实施例对本实用新型作进一步说明，以方便技术人员理解。 
如图7所示：一种基于框架腐蚀凸点的无载体式新型封装件包括引线框架1、金属凸点2、粘片胶4、芯片5、键合线6、塑封体7；其中引线框架1正反面设有金属凸点2，芯片5与引线框架1通过粘片胶4相连，键合线6直接从芯片5打到金属凸点2上，引线框架1上是粘片胶4和金属凸点2，粘片胶4上是芯片5，芯片5上的焊点与金属凸点2间的焊线是键合线6，对芯片5和金属凸点2的键合线6起到了支撑和保护作用的塑封体7包围了引线框架1、金属凸点2、粘片胶4、芯片5、键合线6构成了电路的整体；芯片5、金属凸点2、键合线6、引线框架1构成了电路的电源和信号通道。 
所述的金属凸点2可以为单圈也可以为多圈；金属凸点2通过电镀的方法形成；金属凸点2可以选择Ag、NiPdAu或NiPd等惰性金属；所述的粘片胶4可以用胶膜片(DAF)代替。 
本实用新型采用普通框架即可进行产品制作流程，无需过多加工框架载体，缩短设计及制作周期，降低成本；在金属板的正反面使用电镀的方法制作凸点，结合蚀刻工艺可实现在框架上自然形成图形，在金属板的正反面使用电镀的方法制作凸点，结合蚀刻工艺可实现在 框架上自然形成图形，正面凸点便于打线，背面凸点主要保护金属板，而上下对应的金属凸点经过蚀刻有效形成图形，无需光照蚀刻；蚀刻后的金属板与原有部分形成凹槽，在塑封后形成有效的防拖拉结构，有效提高封装可靠性；在凸点排布及I/O数不受框架设计及制作限制的前提下，实现了凸点排布可任意定义，更好得实现芯片与载体的互联；更可实现双圈或多圈金属凸点排布，使I/O更加密集，成本更低，封装可靠性更高；摒弃以往使用光刻胶进行光照腐蚀的工艺，极大降低成本，提高生产效率。 
如图1-7所示：本实用新型的制作工艺流程如下：框架电镀形成金属凸点→正面蚀刻图形→晶圆减薄→划片→上芯→压焊→塑封→背面蚀刻图形去除框架载体→切割。具体方法如下； 
第一步、引线框架1电镀形成金属凸点2，框架正反面经过蚀刻有效形成图形； 
在0.05mm-0.35mm之间厚度的引线框架1上使用电镀的方法在金属板的正反面制作金属凸点2，金属凸点2可以是Ag、NiPdAu或NiPd等惰性金属凸点，此法结合蚀刻工艺即可实现在框架上自然形成图形，正面凸点便于打线，背面凸点主要保护金属板，而上下对应的金属凸点经过蚀刻有效形成图形，无需光照蚀刻，极大降低成本； 
第二步、减薄；根据需要对晶圆厚度进行减薄处理； 
第三步、划片；150μm以上晶圆同普通QFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺； 
第四步、上芯；既可采用粘片胶2上芯； 
第五步、压焊；压焊同常规QFN/DFN工艺，同时，在芯片5和金属凸点2之间打金属线； 
第六步、塑封；蚀刻后的金属板与原有部分形成凹槽，塑封料在塑封工序时浇注进凹槽，从而形成有效的防拖拉结构，有效提高封装可靠性； 
第七步、背面蚀刻图形去除框架载体；背面凸点主要保护金属板，而上下对应的金属凸点经过蚀刻或磨屑的方法去除框架载体，从而有效形成图形，无需光照蚀刻； 
第八步、切割；采用常规QFN/DF的制作工艺。 
本实用新型通过附图进行说明的，在不脱离本实用新型范围的情况下，还可以对本实用新型专利进行各种变换及等同代替，因此，本实用新型专利不局限于所公开的具体实施过程，而应当包括落入本实用新型专利权利要求范围内的全部实施方案。 

Claims (4)

1.一种基于框架腐蚀凸点的无载体式新型封装件，其特征在于：包括引线框架、金属凸点、粘片胶、芯片、键合线、塑封体；其中引线框架正反面设有金属凸点，芯片与引线框架通过粘片胶相连，键合线直接从芯片打到金属凸点上，引线框架上是粘片胶和金属凸点，粘片胶上是芯片，芯片上的焊点与金属凸点间的焊线是键合线，所述塑封体包围了引线框架、金属凸点、粘片胶、芯片和键合线；芯片、金属凸点、键合线、引线框架构成了电路的电源和信号通道。
2.根据权利要求1所述的一种基于框架腐蚀凸点的无载体式新型封装件，其特征在于：所述的金属凸点可以为单圈也可以为多圈。
3.根据权利要求1所述的一种基于框架腐蚀凸点的无载体式新型封装件，其特征在于：所述的金属凸点可以选择Ag、NiPdAu或NiPd。
4.根据权利要求1所述的一种基于框架腐蚀凸点的无载体式新型封装件，其特征在于：所述的粘片胶可以用胶膜片代替。
CN201220479169.6U 2012-09-19 2012-09-19 一种基于框架腐蚀凸点的无载体式新型封装件 Expired - Lifetime CN203260570U (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870100A (zh) * 2015-01-05 2016-08-17 广东气派科技有限公司 一种超薄封装件及其制作工艺
CN105895615A (zh) * 2015-01-05 2016-08-24 广东气派科技有限公司 一种超薄封装元件及其制作工艺
CN106409689A (zh) * 2016-09-30 2017-02-15 乐依文半导体(东莞)有限公司 高密度线路芯片封装工艺

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870100A (zh) * 2015-01-05 2016-08-17 广东气派科技有限公司 一种超薄封装件及其制作工艺
CN105895615A (zh) * 2015-01-05 2016-08-24 广东气派科技有限公司 一种超薄封装元件及其制作工艺
CN106409689A (zh) * 2016-09-30 2017-02-15 乐依文半导体(东莞)有限公司 高密度线路芯片封装工艺
CN106409689B (zh) * 2016-09-30 2019-11-01 乐依文半导体(东莞)有限公司 高密度线路芯片封装工艺

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