CN203219282U - Time-delay chain and time-delay chain group - Google Patents
Time-delay chain and time-delay chain group Download PDFInfo
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- CN203219282U CN203219282U CN 201320102157 CN201320102157U CN203219282U CN 203219282 U CN203219282 U CN 203219282U CN 201320102157 CN201320102157 CN 201320102157 CN 201320102157 U CN201320102157 U CN 201320102157U CN 203219282 U CN203219282 U CN 203219282U
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Abstract
The utility model provides a time-delay chain and a time-delay chain group, wherein the time-delay chain comprises a first time-delay segment, a second time-delay segment, a third time-delay segment, an odd number of forth time-delay segments, and a fifth time-delay segment, wherein a second end of the first time-delay segment is horizontally connected to a first port of the time-delay chain, a first end of the second time-delay segment is perpendicularly connected with a first end of the first time-delay segment, a first end of the third time-delay segment is perpendicularly connected with a second end of the second time-delay segment, the third time-delay segment is parallel to the first time-delay segment, the third time-delay segment and the first time-delay segment are arranged at the same side of the second time-delay segment, the odd number of forth time-delay segments are parallel to the first time-delay segment and are connected orderly, a first end of the fifth time-delay segment is connected with a first end of the last forth time-delay segment in the odd number of forth time-delay segments, and a second port neighbors the first port.
Description
Technical field
The utility model relates to the digital circuit field, in particular to a kind of time delay chain and time delay chain group.
Background technology
In the large scale digital circuit, the extensive use of time delay chain, there is more and more higher requirement aspects such as feasible time-delay to time delay chain is accurate, input output distance, laying out pattern area.
Time delay chain mainly is the effect of playing time-delay by a plurality of time delay devices, simultaneously because in each time delay chain the different time delay device of quantity can be set, therefore can adjust the time length of each time delay chain time-delay by the length of adjusting time delay chain.Because be different for different time-delay scenes or the required time-delay of time-delay situation, therefore a plurality of time delay chains can be set, form a time delay chain group, thereby can select the number of the time delay chain that uses in the time delay chain group to carry out delay process as required.General time delay chain be mainly used in phase-locked loop, clock synchronously, clock count need carry out the place of delay process with timely number conversion etc.
In correlation technique, the layout type of time delay chain has following several:
1) rectangular layout of time delay chain rule
As shown in Figure 1, the inverter (each square all represents the time delay device of a same size, identical domain among the figure) that a plurality of time delay devices in the time delay chain are formed forms the rectangular layout time delay chain according to snakelike inflection type layout.But there is following defective in the layout type of this time delay chain: the distance between input (in) and the output (out) is too far away, is unfavorable for input and output are carried out logical operation.
2) the rectangular inflection layout of time delay chain
As shown in Figure 2, the time delay chain that a plurality of rectangular inflection layouts are arranged, each square all represents the inverter module of same size, identical domain among the figure, the square of white is the inverter module that is in the use state, hypographous square is illusory module (being called the dummy module again), and but these modules only are arranged in the layout of time delay chain do not play the effect of essence.In this time delay chain layout type, though revised the drawback of hypertelorism between input and the output, but, when the time delay chain of a plurality of different lengths is formed the time delay chain group together, for example, as shown in Figure 2, this time delay chain group is made up of 5 one time delay chains, this 5 one time delay chain is respectively: the time delay chain 1 between in1 and the out1, the time delay chain 2 between in2 and the out2 ... time delay chain 5 between in5 and the out5.In layout as shown in Figure 2, just there are a plurality of illusory modules, so just caused the waste of chip area.That is, the area of the domain that has dash area of lower left as shown in Figure 2 waste, more big at long delay chain and short time delay chain gap, the time delay chain number is wasted more serious more for a long time.
Problem at one of above-mentioned at least in the correlation technique does not propose effective solution at present as yet.
The utility model content
The utility model provides a kind of time delay chain and time delay chain group, to solve the problem that layout area that time delay chain layout in the correlation technique can not solve the time delay chain group that input and output distance time delay chain big and different length form is simultaneously wasted at least.
According to an aspect of the present utility model, provide a kind of time delay chain to comprise: first delay number, the second end level of described first delay number is connected to first port of described time delay chain; Second delay number, the vertical connection of first end of first end of described second delay number and described first delay number; The 3rd delay number, the vertical connection of second end of first end of described the 3rd delay number and described second delay number, and be parallel to described first delay number, wherein, described the 3rd delay number and described first delay number are at the homonymy of described second delay number; Odd number the 4th delay number, described odd number the 4th delay number are parallel to described first delay number and connect successively, and wherein, second end of first the 4th delay number in described odd number the 4th delay number is connected with second end of described the 3rd delay number; The 5th delay number, first end of last the 4th delay number in first end of described the 5th delay number and described odd number the 4th delay number is connected, second end of described the 5th delay number is connected with described second port, described the 5th delay number is parallel with described first delay number, and described second port is adjacent with described first port; Wherein, described first delay number, described second delay number, described the 3rd delay number, described the 4th delay number and described the 5th delay number comprise one or more time delay devices respectively.
Preferably, described time delay device comprises: inverter and/or delay unit.
Preferably, the number of the described time delay device that described first delay number comprises is identical with the number of the described time delay device that described the 3rd delay number comprises, perhaps, the number of the described time delay device that comprises greater than described the 3rd delay number of the number of the described time delay device that comprises of described first delay number.
Preferably, described first port is input, and described second port is output; Perhaps described first port is output, and described second port is input.
According to another aspect of the present utility model, a kind of time delay chain group is provided, comprise one or more above-mentioned time delay chains.
Preferably, described time delay device comprises: inverter and/or delay unit.
Preferably, comprise under the situation of a plurality of described time delay chains in described time delay chain group, the number of the time delay device that first delay number of each time delay chain in the described time delay chain group comprises is identical with the number of the described time delay device that the 3rd delay number comprises, and the number of the time delay device that comprises of first delay number of different delayed time chain is identical.
Preferably, the time delay device number that comprises of each time delay chain in the described time delay chain group is identical.
Preferably, comprise under the different situation of time delay device number that a plurality of time delay chains and each time delay chain comprise the number of the time delay device that the number of the time delay device that first delay number of each time delay chain in the described time delay chain group comprises comprises greater than the 3rd delay number in described time delay chain group.
Preferably, the number of the time delay device that comprises according to each time delay chain of a plurality of time delay chains in the described time delay chain group from how to few setting that is nested successively from outside to inside.
In the utility model, the time delay chain group comprises one or more time delay chains, wherein, this time delay chain comprises: first delay number, the second end level of above-mentioned first delay number is connected to first port of above-mentioned time delay chain, and wherein, second port of above-mentioned time delay chain is parallel adjacent with above-mentioned first port, overcome the defective of distance between input and the output, thereby helped input and output are carried out logical operation; Second delay number, the vertical connection of first end of first end of above-mentioned second delay number and above-mentioned first delay number; The 3rd delay number, the vertical connection of second end of first end of above-mentioned the 3rd delay number and above-mentioned second delay number, and be parallel to above-mentioned first delay number, wherein, above-mentioned the 3rd delay number and above-mentioned first delay number are at the homonymy of above-mentioned second delay number; Odd number the 4th delay number, above-mentioned odd number the 4th delay number are parallel to above-mentioned first delay number and connect successively, and wherein, second end of first the 4th delay number in above-mentioned odd number the 4th delay number is connected with second end of above-mentioned the 3rd delay number; First end of last the 4th delay number in the 5th delay number, first end of above-mentioned the 5th delay number and above-mentioned odd number the 4th delay number is connected, and second end of above-mentioned the 5th delay number is connected with above-mentioned second port, and is parallel to above-mentioned first delay number; Wherein, above-mentioned first delay number, above-mentioned second delay number, above-mentioned the 3rd delay number, above-mentioned the 4th delay number and above-mentioned the 5th delay number comprise one or more inverters respectively, realized that a plurality of inverters in the time delay chain can be arranged on by the layout type of snakelike inflection in certain areal extent compactly, the time delay chain of different length can arrange first delay number of different length respectively, second delay number, the 3rd delay number, the 4th delay number, the 5th delay number, with rational deployment time delay chain group domain, help to save chip area, in addition, first port of above-mentioned time delay chain is parallel adjacent with above-mentioned second port, overcome the defective of distance between input and the output, thereby help input and output are carried out logical operation, help to improve the time delay chain performance.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present utility model, constitutes the application's a part, and illustrative examples of the present utility model and explanation thereof are used for explaining the utility model, do not constitute improper restriction of the present utility model.In the accompanying drawings:
Fig. 1 is the time delay chain schematic layout pattern according to correlation technique;
Fig. 2 is the time delay chain group schematic layout pattern according to correlation technique;
Fig. 3 is the time delay chain schematic layout pattern according to the utility model embodiment;
Fig. 4 is the preferred time delay chain schematic layout pattern according to the utility model embodiment;
Fig. 5 is the preferred time delay chain group schematic layout pattern one according to the utility model embodiment;
Fig. 6 is the preferred time delay chain group schematic layout pattern two according to the utility model embodiment;
Fig. 7 is the preferred time delay chain group schematic layout pattern three according to the utility model embodiment;
Fig. 8 is the preferred time delay chain group schematic layout pattern four according to the utility model embodiment;
Fig. 9 is the preferred time delay chain group schematic layout pattern five according to the utility model embodiment;
Figure 10 is the preferred time delay chain group schematic layout pattern six according to the utility model embodiment;
Figure 11 is the preferred binary system time delay chain group schematic layout pattern according to the utility model embodiment.
Embodiment
Hereinafter will describe the utility model with reference to the accompanying drawings and in conjunction with the embodiments in detail.Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.
Present embodiment provides a kind of time delay chain, as shown in Figure 3, comprise: first delay number (Fig. 3 get the bid 1 time delay device form first delay number), first port that the second end level of above-mentioned first delay number is connected to above-mentioned time delay chain (namely, in among Fig. 3), wherein, second port of above-mentioned time delay chain (that is the out among Fig. 3) is adjacent with above-mentioned first port; Second delay number (Fig. 3 get the bid 2 time delay device form second delay number), the vertical connection of first end of first end of above-mentioned second delay number and above-mentioned first delay number; The 3rd delay number (Fig. 3 get the bid 3 time delay device form the 3rd delay number), the vertical connection of second end of first end of above-mentioned the 3rd delay number and above-mentioned second delay number, and be parallel to above-mentioned first delay number, wherein, above-mentioned the 3rd delay number and above-mentioned first delay number are at the homonymy of above-mentioned second delay number; Odd number the 4th delay number (Fig. 3 get the bid 4 and be positioned at same horizontal time delay device and form the 4th delay number), above-mentioned odd number the 4th delay number is parallel to above-mentioned first delay number and connects successively, wherein, second end of first the 4th delay number in above-mentioned odd number the 4th delay number is connected with second end of above-mentioned the 3rd delay number; The 5th delay number (Fig. 3 get the bid 5 time delay device form the 5th delay number), first end of last the 4th delay number in first end of above-mentioned the 5th delay number and above-mentioned odd number the 4th delay number is connected, second end of above-mentioned the 5th delay number is connected with above-mentioned second port, and be parallel to above-mentioned first delay number, and above-mentioned second port is adjacent with first port; Wherein, above-mentioned first delay number, above-mentioned second delay number, above-mentioned the 3rd delay number, above-mentioned the 4th delay number and above-mentioned the 5th delay number comprise one or more time delay devices respectively.
Preferably, in this preferred embodiment, above-mentioned first port can be the input of time delay chain, and above-mentioned second port can be the output of time delay chain; Perhaps above-mentioned first port can be the output of time delay chain, and above-mentioned second port can be the input of time delay chain.
Further, this preferred embodiment also provides a kind of time delay chain group, comprises one or more time delay chains as shown in Figure 3.
In the above-described embodiments, the time delay chain group comprises one or more time delay chains, wherein, this time delay chain comprises: first delay number, the second end level of above-mentioned first delay number is connected to first port of above-mentioned time delay chain, wherein, second port of above-mentioned time delay chain is adjacent with above-mentioned first port, be on the horizontal-extending position between above-mentioned second port and above-mentioned first port any time delay device not to be set, overcome the defective of distance between the input of time delay chain and the output, thereby helped input and output are carried out logical operation; Second delay number, the vertical connection of first end of first end of above-mentioned second delay number and above-mentioned first delay number; The 3rd delay number, the vertical connection of second end of first end of above-mentioned the 3rd delay number and above-mentioned second delay number, and be parallel to above-mentioned first delay number, wherein, above-mentioned the 3rd delay number and above-mentioned first delay number are at the homonymy of above-mentioned second delay number; Odd number the 4th delay number, above-mentioned odd number the 4th delay number are parallel to above-mentioned first delay number and connect successively, and wherein, second end of first the 4th delay number in above-mentioned odd number the 4th delay number is connected with second end of above-mentioned the 3rd delay number; First end of last the 4th delay number in the 5th delay number, first end of above-mentioned the 5th delay number and above-mentioned odd number the 4th delay number is connected, and second end of above-mentioned the 5th delay number is connected with above-mentioned second port, and is parallel to above-mentioned first delay number; Wherein, above-mentioned first delay number, above-mentioned second delay number, above-mentioned the 3rd delay number, above-mentioned the 4th delay number and above-mentioned the 5th delay number comprise one or more time delay devices respectively, realized that a plurality of time delay devices in the time delay chain can be arranged on by the layout type of snakelike inflection in certain areal extent compactly, the time delay chain of different length can arrange first delay number of different length respectively, second delay number, the 3rd delay number, the 4th delay number, the 5th delay number, with rational deployment time delay chain group domain, help to save chip area, in addition, on the horizontal-extending position between the output of above-mentioned time delay chain and the above-mentioned input any time delay device is not set, be that input and output are adjacent, overcome the defective of distance between input and the output, thereby help input and output are carried out logical operation, help to improve the time delay chain performance.
Preferably, in this preferred embodiment, if the time delay chain group includes only a time delay chain, for avoiding the problem of this time delay chain layout area waste, as shown in Figure 4, the number of the above-mentioned time delay device that the number of the above-mentioned time delay device that first delay number (Fig. 4 get the bid 1 time delay device form first delay number) comprises and above-mentioned the 3rd delay number (Fig. 4 get the bid 3 time delay device form the 3rd delay number) comprise is identical, and the layout of whole piece time delay chain is the inflection rectangle.Namely rationally determine the length of first delay number, the length of above-mentioned second delay number, the length of above-mentioned the 3rd delay number, the number of above-mentioned the 4th delay number as required, make the layout of whole piece time delay chain be the inflection rectangle, this moment, the length of above-mentioned the 4th delay number was identical with the length of the 5th delay number, can think that maybe the 5th delay number does not exist, the 4th delay number directly is connected with output, can realize a plurality of time delay devices in the above-mentioned time delay chain are arranged in certain area compactly.
Preferably, in this preferred embodiment, if include a plurality of time delay chains in the time delay chain group, in order to solve the problem of time delay chain layout area waste well, not only first delay number of same time delay chain and time delay device number that the 3rd delay number comprises are identical (be identical with 3 number as Fig. 5 and time delay chains 1 corresponding 1 shown in Figure 7) in a time delay chain group, the time delay device number that first delay number of different delayed time chain comprises in a time delay chain group also is identical (be identical as 1 number in 1 number in Fig. 5 and the time delay chain 1 shown in Figure 7 and the time delay chain 2), the layout of every one time delay chain just is the inflection rectangle in same time delay chain group like this, a plurality of inflection rectangle splicings realize the layout of time delay chain group, can effectively save chip area, solve the problem of chip area waste well.In order to solve the input between each time delay chain, the problem of output distance, certain inflection rectangle can be arranged conversely, as Fig. 5 and shown in Figure 7, time delay chain 1 arranges conversely, time delay chain 2 forward settings, the input (in2), the distance between the output (out2) (be that time delay chain 1,2 first port are input, second port is output) of input (in1), output (out1) and the time delay chain 2 of time delay chain 1 have so namely been realized shortening.Further, when a plurality of time delay chains are the inflection rectangle and form as Fig. 5 and time delay chain group shown in Figure 7, in order to make input and the output of two adjacent time delay chains can carry out the signal input easily, can be as Fig. 6 and shown in Figure 8, first port that time delay chain 1 is set is output (out1), second port is input (in1), first port of time delay chain 2 is input (in2), second port is output (out2), and the signal of the output of time delay chain 1 can be input to the input of time delay chain 2 easily like this.
Merit attention and be, carry out the arrangement of time delay chain according to the arrangement mode among Fig. 5 to 8, the number of the time delay device that contains of the different delayed time chain in the time delay chain group can be different (as illustrated in Figures 5 and 6), also can be identical (shown in Fig. 7 and 8), also can be, as long as the feasible composition form that can line up the time delay chain as shown in Fig. 5 to 8 of the number of time delay device in each delay number rationally is set.Wherein, when the time delay device number that comprises when each time delay chain in a plurality of time delay chains of time delay chain group is identical, preferably make the time delay device number that first delay number of different delayed time chain comprises in the time delay chain group identical, the time delay device number that certain the 3rd delay number comprises is also identical.
Preferably, if the time delay chain group comprises a plurality of time delay chains, and the time delay device number that each time delay chain comprises is not simultaneously, in order to solve the problem of time delay chain layout area waste well, the number of the time delay device that the number that the above-mentioned time delay device that first delay number comprises also can be set comprises greater than the 3rd delay number.Be that the length of first delay number of each time delay chain is greater than the length of the 3rd delay number, for the arrangement of the wall scroll time delay chain after arranging in this manner just as shown in Figure 3, be equivalent to above-mentioned first delay number when signal enters time delay chain from end (input) through certain-length A() turn back downwards, being equivalent to above-mentioned second delay number through length B() the back time delay chain turns back to the right, process length C (being equivalent to above-mentioned the 3rd delay number) back time delay chain makes progress left as snakelike inflection type is turned back, and length D(is equivalent to above-mentioned the 4th delay number), can repeat as required repeatedly as the snakelike inflection type length D that turns back herein, signal is by the output output of certain-length (being equivalent to above-mentioned the 5th delay number) back below the time delay chain input then, be that whole time delay chain is pistol-shaped, preferably, as shown in Figure 3, the length of above-mentioned the 3rd delay number (C) can be to Duo the length of a time delay device than the length (D) of the 4th delay number.Preferably, time delay device between input and the output is arranged in certain area compactly, the length of first delay number can rationally be set according to the length of each time delay chain in the time delay chain group, the length of above-mentioned second delay number, the length of above-mentioned the 3rd delay number, the number of above-mentioned the 4th delay number, make a plurality of time delay chains present the pistol-shaped that varies in size, and can be with a plurality of time delay chains according to the descending setting that is nested successively of length from outside to inside, to form as shown in Figure 9 time delay chain group (trend that the black line among Fig. 9 represent the time delay chain that time delay device forms as shown in Figure 3), with the saving chip area.
Preferably, the layout type of above-mentioned time delay chain group both can be used for the binary system time delay chain also can be used for going forward one by one the type time delay chain, can the length of the length of the first different delay numbers, above-mentioned second delay number, the number of above-mentioned the 4th delay number be set according to the different delayed time chain length, and with the setting that is nested of a plurality of time delay chains, can save chip area well.If desired a plurality of signals are carried out identical delay process, then can set up two symmetrical time delay chains based on Y-axis or X-axis, as shown in figure 10, be a kind of two time delay chains based on the Y-axis symmetry, namely, the right and left of Y-axis is two time delay chains that delay effect is identical about the Y-axis symmetry, thereby has realized the symmetrical treatment of Y-axis to a certain extent.The binary system time delay chain is that delay number is distributed as 2 power time length, 2D-4D-8D for example, and D be the length of delaying time substantially; The non-binary type time delay chain that goes forward one by one is the non-power of linear growth time length, 3D-5D-9D for example, and D be basic time-delay length, how for multistage delay precision adjustable delay chain.
In this preferred embodiment, be example with the binary system time delay chain, the layout type of time delay chain group is described, (each square all represents same size among the figure as shown in figure 11, the time delay device of domain, the square of white is the delay unit that is in the use state, the square of shade is the dummy module), the length of the first different delay numbers is set according to the different delayed time chain length, the length of above-mentioned second delay number, the length of above-mentioned the 3rd delay number, the length of above-mentioned the 4th delay number, and with the setting that is nested of a plurality of time delay chains, and with a plurality of time delay chains according to the descending setting that is nested successively of length from outside to inside, thereby make the different time delay chain of a plurality of length agree with ground, arrange compactly.
In above-mentioned each preferred implementation, time delay device includes but not limited to: inverter and/or be delay unit, wherein, the effect of inverter is carried out negate to signal exactly, what the inferior negate of even number obtained still is original signal, yet there is the delay on the regular hour in inverter itself, has realized the transmission delay of signal just by the process of this negate; The circuit that delay unit generally is made up of one or more gates, sort circuit only are the transmission delays that realizes signal by the delayed action of the gate in the circuit not to the signal negate.Wherein, in same one time delay chain inverter can only be arranged, also delay unit can only be arranged, also can be that the configuration of delay unit and inverter is used, as long as finally can reach the purpose of time-delay.
The above is preferred embodiment of the present utility model only, is not limited to the utility model, and for a person skilled in the art, the utility model can have various changes and variation.All within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.
Claims (10)
1. a time delay chain is characterized in that, comprising:
First delay number, the second end level of described first delay number is connected to first port of described time delay chain;
Second delay number, the vertical connection of first end of first end of described second delay number and described first delay number;
The 3rd delay number, the vertical connection of second end of first end of described the 3rd delay number and described second delay number, and be parallel to described first delay number, wherein, described the 3rd delay number and described first delay number are at the homonymy of described second delay number;
Odd number the 4th delay number, described odd number the 4th delay number are parallel to described first delay number and connect successively, and wherein, second end of first the 4th delay number in described odd number the 4th delay number is connected with second end of described the 3rd delay number;
The 5th delay number, first end of last the 4th delay number in first end of described the 5th delay number and described odd number the 4th delay number is connected, second end of described the 5th delay number is connected with described second port, described the 5th delay number is parallel with described first delay number, and described second port is adjacent with described first port;
Wherein, described first delay number, described second delay number, described the 3rd delay number, described the 4th delay number and described the 5th delay number comprise one or more time delay devices respectively.
2. time delay chain according to claim 1 is characterized in that, described time delay device comprises: inverter and/or delay unit.
3. time delay chain according to claim 1, it is characterized in that, the number of the described time delay device that described first delay number comprises is identical with the number of the described time delay device that described the 3rd delay number comprises, perhaps, the number of the described time delay device that comprises greater than described the 3rd delay number of the number of the described time delay device that comprises of described first delay number.
4. according to each described time delay chain in the claim 1 to 3, it is characterized in that described first port is input, described second port is output; Perhaps described first port is output, and described second port is input.
5. a time delay chain group is characterized in that, comprises one or more time delay chains as claimed in claim 1.
6. time delay chain group according to claim 5 is characterized in that time delay device comprises: inverter and/or delay unit.
7. according to claim 5 or 6 described time delay chain groups, it is characterized in that, comprise under the situation of a plurality of described time delay chains in described time delay chain group, the number of the time delay device that first delay number of each time delay chain in the described time delay chain group comprises is identical with the number of the described time delay device that the 3rd delay number comprises, and the number of the time delay device that comprises of first delay number of different delayed time chain is identical.
8. time delay chain group according to claim 7 is characterized in that, the time delay device number that each time delay chain in the described time delay chain group comprises is identical.
9. according to claim 5 or 6 described time delay chain groups, it is characterized in that, comprise under the different situation of time delay device number that a plurality of time delay chains and each time delay chain comprise the number of the time delay device that the number of the time delay device that first delay number of each time delay chain in the described time delay chain group comprises comprises greater than the 3rd delay number in described time delay chain group.
10. time delay chain group according to claim 9 is characterized in that, the number of the time delay device that a plurality of time delay chains in the described time delay chain group comprise according to each time delay chain from how to few setting that is nested successively from outside to inside.
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| CN111835320A (en) * | 2019-04-22 | 2020-10-27 | 珠海格力电器股份有限公司 | Signal edge detection device |
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| CN111835320A (en) * | 2019-04-22 | 2020-10-27 | 珠海格力电器股份有限公司 | Signal edge detection device |
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Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100190 No. 10 South Road, Zhongguancun Academy of Sciences, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |
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Granted publication date: 20130925 |