CN203219178U - Limited bipolarity control full-bridge power supply module parallel circuit based on digital signal processor (DSP) - Google Patents
Limited bipolarity control full-bridge power supply module parallel circuit based on digital signal processor (DSP) Download PDFInfo
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- CN203219178U CN203219178U CN 201320014911 CN201320014911U CN203219178U CN 203219178 U CN203219178 U CN 203219178U CN 201320014911 CN201320014911 CN 201320014911 CN 201320014911 U CN201320014911 U CN 201320014911U CN 203219178 U CN203219178 U CN 203219178U
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Abstract
The utility model discloses a limited bipolarity control full-bridge power supply module parallel circuit based on a digital signal processor (DSP), and the limited bipolarity control full-bridge power supply module parallel circuit comprises a DSP circuit, a pulse width modulation (PWM) multiplexing and tripping protection circuit, a PWM drive circuit, a full-bridge inverter and an output rectification filter circuit; the DSP circuit is connected with the PWM multiplexing and tripping protection circuit, and the PWM multiplexing and tripping protection circuit is sequentially connected with the PWM drive circuit, the full-bridge inverter and the output rectification filter circuit; and the PWM multiplexing and tripping protection circuit is also connected with the full-bridge inverter. Multiple PWM multiplexing and tripping protection circuits are shared by two PWM signals, each full-bridge inverter is only provided with another two independent PWM signals, the PWM output signal of the DSP is saved, the multiple limited bipolarity control of the DSP for the full-bridge circuit can be enlarged, the parallel output of the limited bipolarity control full-bridge topological circuit is realized, the output capacity is increased, and the control cost is saved.
Description
Technical field
The utility model relates to high power DC switch power technology field, is specifically related to a kind of finite both control full-bridge power module parallel circuits based on DSP.
Background technology
At present, increase day by day in the demand of the various large power supplies of many industries, especially the demand of some high-power DC power supplies.But the DC power supplier finite capacity often adopts the multimode parallel running, its output energy is the several times of module output, improved the power grade of DC power supply, the multimode parallel operation makes system have certain redundancy simultaneously, makes the reliability of whole system that large increase arranged.The multimode parallel running not only makes DC power supply have bigger power and reliability, but also has good versatility, and flexible combination becomes the system of various power as required.In this case, general employing now fully independently power module output in parallel comes extended power, independent mutually between the module like this, do not disturb mutually, be beneficial to maintenance and the long-time running of power supply, but control is comparatively complicated, line is more, and in the dynamic property that requires power supply and the higher occasion of synchronism, independently power module is difficult to reach higher requirement, especially when non-constant current output mode, the consistency of power supply and dynamic property are required higher, general module parallel connection is difficult to reach requirement.
The utility model content
The purpose of this utility model is to provide the finite both control full-bridge power module parallel circuits based on DSP, and circuit complexity in the existing DC power supply parallel connection, control are loaded down with trivial details to solve, bad dynamic performance, power supply be synchronously than problems such as difficulties.The utility model carries out multiplexing to pwm signal, namely a plurality of full-bridge inverters share two-way pwm signal, the PWM output signal of having saved DSP.
The utility model is for achieving the above object, and the technical scheme that adopts is as follows:
Based on the finite both of DSP control full-bridge power module parallel circuits, comprise the dsp processor circuit, PWM is multiplexing and trip protection circuit, PWM drive circuit, full-bridge inverter and output rectifier and filter; Wherein said dsp processor circuit and trip protection circuit multiplexing with PWM is connected, and the multiplexing and trip protection circuit of described PWM is connected with PWM drive circuit, full-bridge inverter, output rectifier and filter in turn; Multiplexing and the trip protection circuit of described PWM also is connected with full-bridge inverter.
Described full-bridge inverter adopts the finite both control mode, and 4 road required pwm signals are produced by the dsp processor circuit, and is amplified to through the PWM drive circuit and is enough to the driving power devices switch.
First via pwm signal PWM1H and the second road pwm signal PWM1L are fixing pwm signal in described 4 road pwm signals, and first via pwm signal PWM1H and the second road pwm signal PWM1L driving brachium pontis are full-bridge inverter first brachium pontis; Third Road pwm signal PWM2H and the four road pwm signal PWM2L are the adjustable pwm signal of pulsewidth, and it is full-bridge inverter second brachium pontis that Third Road pwm signal PWM2H and the four road pwm signal PWM2L drive brachium pontis.
Described first via pwm signal PWM1H becomes 180 ° of complementary square waves with the second road pwm signal PWM1L, and Third Road pwm signal PWM2H becomes 180 ° of complementary square waves with the four road pwm signal PWM2L; First via pwm signal PWM1H is consistent with the rising edge of the four road pwm signal PWM2L, and the second road pwm signal PWM1L is consistent with the rising edge of Third Road pwm signal PWM2H.
Described dsp processor circuit is controlled the output size of power module by the pulsewidth of regulating Third Road pwm signal PWM2H and the four road pwm signal PWM2L.
The fixedly pwm signal that described PWM is multiplexing and the trip protection circuit produces the dsp processor circuit: first via pwm signal PWM1H and the second road pwm signal PWM1L carry out multiplexing; be that a plurality of full-bridge inverters all have a brachium pontis to adopt first via pwm signal PWM1H and the second road pwm signal PWM1L to drive, the another one brachium pontis all adopts separately the independently adjustable pwm signal of pulsewidth.
Multiplexing and the trip protection circuit of described PWM is made of four dual inputs and door and a d type flip flop; four dual inputs all are connected with the output Q of d type flip flop with the first input end of door; first dual input is imported termination first via pwm signal PWM1H with second of door; second dual input is imported termination the second road pwm signal PWM1L with second of door; the 3rd dual input is imported termination Third Road pwm signal PWM2H with second of door, the second input termination the four road pwm signal PWM2L of the 4th dual input and door.
The input end of clock CLK of described d type flip flop all is connected with the IO mouth of DSP; The input D of d type flip flop is connected with clear terminal CLR, and connects with the input of trip protection signal; The output Q of d type flip flop also is connected with the dsp processor circuit, exports for generation of the trip protection signal; The locking control of trip protection signal is by the IO mouth control of DSP; namely when the trip protection signal is input as low level; the clear terminal CLR of d type flip flop is low level; d type flip flop Q end is low level; four dual inputs and door locked 4 road pwm signals are low level; when the input of trip protection signal reverts to high level; d type flip flop Q end still keeps low level; no matter whether the input of trip protection signal changes in cycle at this pwm signal; the output Q of d type flip flop keeps low level when the IO of DSP mouth produces next rising edge; d type flip flop Q end just can change according to input D, has therefore realized the locking control of trip protection signal output.
With respect to the prior art scheme, the beneficial effects of the utility model are:
1, circuit is simple and practical, pwm signal has been carried out multiplexing, and the pwm signal of some can drive more full-bridge inverter, and the pwm signal control of expansion dsp processor circuit has been saved and controlled cost;
2, control method is simple, has realized the parallel connection of multimode power supply in a DSP, has omitted communication and central monitoring system between the module.
3, owing to adopt same DSP to control a plurality of full-bridge topological circuits, dynamic performance, consistency, synchronism are in full accord, are fit to various applications.
Description of drawings
Fig. 1 is the phase-shifting full-bridge power module parallel circuits sketch based on DSP of embodiment;
Fig. 2 is that the PWM of the finite both control of embodiment drives signal schematic representation;
Fig. 3 is the full-bridge inverter circuit figure of embodiment;
Fig. 4 is the multiplexing and trip protection circuit diagram of the PWM of embodiment.
Embodiment
Below in conjunction with accompanying drawing enforcement of the present utility model is done further and to be described in detail.
As shown in Figure 1, based on the finite both of DSP control full-bridge power module parallel circuits, comprise dsp processor circuit, three tunnel identical power circuits; The described three tunnel identical every roads of power circuit comprise PWM multiplexing and trip protection circuit, PWM drive circuit, full-bridge inverter and output rectifier and filter; Described dsp processor circuit and trip protection circuit multiplexing with the PWM of three-way power circuit is connected, multiplexing and the trip protection circuit of the PWM of every road power circuit is connected with PWM drive circuit, full-bridge inverter, output rectifier and filter in turn, and the multiplexing and trip protection circuit of PWM also is connected with full-bridge inverter; The output rectifier and filter positive pole of three-way power circuit links together, and negative pole links together, and forms output mode in parallel.
Full-bridge inverter adopts the finite both control mode, and the dsp processor circuit produces 8 road pwm signals, and is amplified to through the PWM drive circuit and is enough to the driving power devices switch.First via pwm signal PWM1H becomes 180 ° of complementary square waves with the second road pwm signal PWM1L in described 8 road pwm signals, Third Road pwm signal PWM2H becomes 180 ° of complementary square waves with the four road pwm signal PWM2L, the five road pwm signal PWM3H becomes 180 ° of complementary square waves with the six road pwm signal PWM3L, and the seven road pwm signal PWM4H becomes 180 ° of complementary square waves with eight-path PWM signal PWM4L; Wherein first via pwm signal PWM1H and the second road pwm signal PWM1L are fixing pwm signal, it drives brachium pontis is full-bridge inverter first brachium pontis in the power circuit of every road, and namely first via pwm signal PWM1H, the second road pwm signal PWM1L of full-bridge inverter first brachium pontis in the power circuit of every road are connected to together; It is full-bridge inverter second brachium pontis of first via power circuit that Third Road pwm signal PWM2H and the four road pwm signal PWM2L drive brachium pontis, it is full-bridge inverter second brachium pontis of No. the second power circuit that the five road pwm signal PWM3H and the six road pwm signal PWM3L drive brachium pontis, and it is full-bridge inverter second brachium pontis of Third Road power circuit that the seven road pwm signal PWM4H and eight-path PWM signal PWM4L drive brachium pontis; Described Third Road to the eight-path PWM signal pulsewidth is adjustable.
As shown in Figure 2, all the other two-way pwm signal rising edges of described every road power circuit are consistent with first via pwm signal PWM1H or the second road pwm signal PWM1L respectively; Be example with first via power circuit, first via pwm signal PWM1H is consistent with the rising edge of the four road pwm signal PWM2L, and the second road pwm signal PWM1L is consistent with the rising edge of Third Road pwm signal PWM2H.
As shown in Figure 3, full-bridge inverter is by the first switching tube Q
1, second switch pipe Q
2, the 3rd switching tube Q
3, the 4th switching tube Q
4With the first diode D
1, the second diode D
2, the 3rd diode D
3, the 4th diode D
4, leakage inductance L
rForm; The first switching tube Q wherein
1By first via pwm signal PWM1H driving, second switch pipe Q
2By the second road pwm signal PWM1L driving, the 3rd switching tube Q
3By Third Road pwm signal PWM2H driving, the 4th switching tube Q
4Driven by the four road pwm signal PWM2L; The first switching tube Q
1With second switch pipe Q
2The place brachium pontis is first brachium pontis, the 3rd switching tube Q
3With the 4th switching tube Q
4The place brachium pontis is second brachium pontis.
Described dsp processor circuit is controlled the output size of each power module by the pulsewidth of regulating Third Road to the eight-path PWM signal.The fixedly pwm signal that PWM is multiplexing and the trip protection circuit produces the dsp processor circuit: first via pwm signal PWM1H and the second road pwm signal PWM1L carry out multiplexing, i.e. multiplexing and the shared first via pwm signal PWM1H of trip protection circuit and the second road pwm signal PWM1L of the PWM of three-way power circuit.
As shown in Figure 4, the multiplexing and trip protection circuit of the PWM of every road power circuit constitutes by four dual inputs and door and a d type flip flop, four dual inputs with first input end all be connected with the output Q of d type flip flop; The PWM of every road power circuit first dual input multiplexing and the trip protection circuit is imported termination first via pwm signal PWM1H with second of door, the second input termination, the second road pwm signal PWM1L of second dual input and door; The PWM of first via power circuit the 3rd dual input multiplexing and the trip protection circuit is imported termination Third Road pwm signal PWM2H with second of door, the second input termination the four road pwm signal PWM2L of the 4th dual input and door; The PWM of No. the second power circuit the 3rd dual input multiplexing and the trip protection circuit is imported termination the five road pwm signal PWM3H with second of door, the second input termination the six road pwm signal PWM3L of the 4th dual input and door; The PWM of Third Road power circuit the 3rd dual input multiplexing and the trip protection circuit is imported termination the seven road pwm signal PWM4H with second of door, the second input termination eight-path PWM signal PWM4L of the 4th dual input and door.
The input end of clock CLK of the d type flip flop of every road power circuit all is connected with the IO mouth of DSP; The output of d type flip flop
Unsettled, preset end PR ground connection; The input D of d type flip flop is connected with clear terminal CLR, and connects with the input of trip protection signal; The output Q of d type flip flop also is connected with the dsp processor circuit, exports for generation of the trip protection signal; The locking control of trip protection signal is by the IO mouth control of DSP; namely when the trip protection signal is input as low level; the clear terminal CLR of d type flip flop is low level; d type flip flop Q end is low level; four dual inputs and door locked 4 road pwm signals are low level; when the input of trip protection signal reverts to high level; d type flip flop Q end still keeps low level; no matter whether the input of trip protection signal changes in cycle at this pwm signal; the output Q of d type flip flop keeps low level when the IO of DSP mouth produces next rising edge; d type flip flop Q end just can change according to input D, has therefore realized the locking control of trip protection signal output.
Dual input in the foregoing circuit can be adopted other dual inputs that can lock output or many inputs and door with door, or door, NAND gate and NOR gate etc. can be formed by the logic gates of an input signal locking output, even can pass through CPLD, and hardware such as FPGA are realized.
As seen; above-mentioned finite both control full-bridge power module parallel circuits based on DSP; multiplexing and the trip protection circuit of a plurality of PWM has the two-way pwm signal to share; just a plurality of full-bridge inverters have the two-way pwm signal to share; the two-way pwm signal that is a plurality of full-bridge inverters links together; it is independently that each full-bridge inverter has only other 2 road pwm signals, has saved the PWM output signal of dsp processor.
Those skilled in the art can make various modifications to this specific embodiment or replenish or adopt similar mode to substitute under the prerequisite of principle of the present utility model and essence, but these are changed and all fall into protection range of the present utility model.Therefore the utility model technical scope is not limited to above-described embodiment.
Claims (3)
1. based on the finite both of DSP control full-bridge power module parallel circuits, it is characterized in that comprising the dsp processor circuit, PWM is multiplexing and trip protection circuit, PWM drive circuit, full-bridge inverter and output rectifier and filter; Wherein said dsp processor circuit and trip protection circuit multiplexing with PWM is connected, and the multiplexing and trip protection circuit of described PWM is connected with PWM drive circuit, full-bridge inverter, output rectifier and filter in turn; Multiplexing and the trip protection circuit of described PWM also is connected with full-bridge inverter; Described full-bridge inverter adopts the finite both control mode, and 4 road required pwm signals of full-bridge inverter are produced by the dsp processor circuit, and is amplified to through the PWM drive circuit and is enough to the driving power devices switch; First via pwm signal PWM1H and the second road pwm signal PWM1L are fixing pwm signal in described 4 road pwm signals, and first via pwm signal PWM1H and the second road pwm signal PWM1L driving brachium pontis are full-bridge inverter first brachium pontis; Third Road pwm signal PWM2H and the four road pwm signal PWM2L are the adjustable pwm signal of pulsewidth, and it is full-bridge inverter second brachium pontis that Third Road pwm signal PWM2H and the four road pwm signal PWM2L drive brachium pontis.
2. the finite both based on DSP according to claim 1 is controlled full-bridge power module parallel circuits; it is characterized in that the multiplexing and trip protection circuit of described PWM is made of four dual inputs and door and a d type flip flop; four dual inputs all are connected with the output Q of d type flip flop with the first input end of door; first dual input is imported termination first via pwm signal PWM1H with second of door; second dual input is imported termination the second road pwm signal PWM1L with second of door; the 3rd dual input is imported termination Third Road pwm signal PWM2H with second of door, the second input termination the four road pwm signal PWM2L of the 4th dual input and door.
3. the finite both control full-bridge power module parallel circuits based on DSP according to claim 2 is characterized in that the input end of clock CLK of described d type flip flop all is connected with the IO mouth of DSP; The input D of d type flip flop is connected with clear terminal CLR, and connects with the input of trip protection signal; The output Q of d type flip flop also is connected with the dsp processor circuit, exports for generation of the trip protection signal; The locking control of trip protection signal is by the IO mouth control of DSP.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320014911 CN203219178U (en) | 2013-01-12 | 2013-01-12 | Limited bipolarity control full-bridge power supply module parallel circuit based on digital signal processor (DSP) |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320014911 CN203219178U (en) | 2013-01-12 | 2013-01-12 | Limited bipolarity control full-bridge power supply module parallel circuit based on digital signal processor (DSP) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078507A (en) * | 2013-01-12 | 2013-05-01 | 华南理工大学 | Limited bipolarity control full-bridge power supply module parallel circuit based on digital signal processor (DSP) |
| CN111293861A (en) * | 2020-03-20 | 2020-06-16 | 邢台子中电子科技有限公司 | Limited bipolar circuit and method |
-
2013
- 2013-01-12 CN CN 201320014911 patent/CN203219178U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078507A (en) * | 2013-01-12 | 2013-05-01 | 华南理工大学 | Limited bipolarity control full-bridge power supply module parallel circuit based on digital signal processor (DSP) |
| CN103078507B (en) * | 2013-01-12 | 2015-10-28 | 华南理工大学 | A kind of limited double poled control scheme full-bridge power module parallel circuits based on DSP |
| CN111293861A (en) * | 2020-03-20 | 2020-06-16 | 邢台子中电子科技有限公司 | Limited bipolar circuit and method |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130925 Termination date: 20200112 |
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| CF01 | Termination of patent right due to non-payment of annual fee |