CN203193625U - Miniaturized zero intermediate frequency transceiver - Google Patents
Miniaturized zero intermediate frequency transceiver Download PDFInfo
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- CN203193625U CN203193625U CN2012207344904U CN201220734490U CN203193625U CN 203193625 U CN203193625 U CN 203193625U CN 2012207344904 U CN2012207344904 U CN 2012207344904U CN 201220734490 U CN201220734490 U CN 201220734490U CN 203193625 U CN203193625 U CN 203193625U
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Abstract
The utility model of the patent discloses a miniaturized zero intermediate frequency transceiver, which belongs to the fields of baseband modulation and demodulation, local oscillator signal generation, up conversion from a baseband signal to a radio-frequency signal, a down conversion from a radio-frequency signal to a baseband signal, amplification, filtering, and automatic gain control (AGC) of a demodulation channel in communication equipment. According to the utility model, a baseband signal is directly processed by up conversion into a radio-frequency signal; and a radio-frequency signal is directly processed by down conversion into a baseband signal; and an AGC function is integrated at a down conversion channel. Therefore, the transceiver with the advantages of small size, low cost, and multiple systems is realized. Moreover, the provided transceiver has the characteristics of small and exquisite size, simple structure and low cost. With cooperation of an FPGA chip with multi-time burning, the transceiver can realize multiple kinds of modulation and demodulation modes and several kinds of rates; the transmitting frequency is flexible and varied; and the transceiver is capable of realizing wireless communication with a certain self-adaption frequency selection function.
Description
Technical field
The utility model relates to a kind of miniaturization zero intermediate frequency transceiver in the communications field, is particularly suitable for cost and volume requirement higher continuous communiction and burst communication system are used.
Background technology
In continuous communiction and burst communication system, common transceiver upconverts to intermediate frequency to baseband signal in the elder generation that makes a start mostly, upconverts to radio frequency by intermediate frequency again; And in receiving end, then be earlier radiofrequency signal to be down-converted to intermediate frequency, be down-converted to base band by intermediate frequency again, because Transmitting and Receiving End all needs double conversion, so structure is complicated, cost is higher.And the receiving end circuit adopts independently agc circuit usually, further causes complex structure, and cost is higher.
The utility model content
The purpose of this utility model be to avoid the weak point of common transceiver in the above-mentioned background technology and provide a kind of simple in structure, volume is small and exquisite, lower-cost transceiver.The utility model adopts zero intermediate frequency, and conversion only needs single-conversion between baseband signal and the radiofrequency signal, not only simplifies the structure but also reduced cost.Also be integrated with the AGC module in the IQ demodulator of the present utility model (7), the dynamic gain scope has reached 69.5dB, can further simplify structure and the specification requirement of radio frequency receiving end.
The purpose of this utility model is achieved in that
A kind of miniaturization zero intermediate frequency transceiver comprises that FPGA1 (field programmable gate array), DAC2 (digital-analog convertor), ADC3 (analogue-to-digital converters), the first low pass circuit 4-1, the second low pass circuit 4-2, local oscillation circuit 5, IQ modulator 6, IQ demodulator 7, the first filter 8-1, the second filter 8-2, the first amplifier 9-1, the second amplifier 9-2, radio frequency make a start 10 and radio frequency receiving end 11; It is characterized in that:
The input port 3 of described FPGA1 receives the modulation code word that upper-layer protocol sends, and by the operation modulation program, the modulation code word modulation is shaped to digital baseband signal, and this signal is sent to the input port 1 of DAC2 by output port 2; Simultaneously, the input port 1 of FPGA1 receives the baseband sampling signal that sends from ADC3 output port 3, by the operation demodulation process, demodulates the demodulation code word, and sends to upper-layer protocol by output port 4; The digital baseband signal that the input port 1 of DAC2 receives from FPGA1 output port 2 is converted into I, Q two-way differential analog signal to it, and gives input port 1 and the input port 2 of the first low pass circuit 4-1 by output port 2 and output port 3 respectively; The input port 1 of the first low pass circuit 4-1 and input port 2 receive I, the Q two-way differential analog signal from the output port 2 of DAC2 and output port 3 transmissions respectively, filtering high fdrequency component wherein flows to signal by output port 3 and output port 4 input port 1 and the input port 2 of IQ modulator 6; Local oscillation circuit 5 produces the radio-frequency (RF) local oscillator signal, and giving the input port 3 of IQ modulator 6 and the input port 2 of IQ demodulator 7 it respectively by output port 1 and output port 2; The input port 1 of IQ modulator 6 and input port 2 receive respectively from the I of the output port 3 of the first low pass circuit 4-1 and output port 4, Q two-way differential analog signal, input port 3 receives the radio-frequency (RF) local oscillator signal that sends from local oscillation circuit 5 output ports 1, finish the up-conversion from the baseband signal to the radiofrequency signal, and radiofrequency signal is given the input port 1 of the first filter 8-1 by output port 4; The input port 1 of the first filter 8-1 receives the radiofrequency signal that the transmit port 4 from IQ modulator 6 sends, the out of band components of this signal of filtering, and filtered signal is sent to the input port 1 of the second amplifier 9-2 by output port 2; The input port 1 of the second amplifier 9-2 is received the signal from the first filter 8-1 output port 2, and it is amplified to the radio frequency 10 desired level values of making a start, and by output port 2 signal after amplifying is sent to make a start 10 input port 1 of radio frequency then; The radio frequency radiofrequency signal that 10 input port 1 receives from the output port 2 of the second amplifier 9-2 of making a start, and it is sent in the space go; And radio frequency receiving end 11 receives from the signal in the space, and gives the input port 1 of the second filter 8-2 it by output port 1; The input port 1 of the second filter 8-2 is received the signal from radio frequency receiving end 11 output ports 1, and the filtering out of band components obtains with interior radiofrequency signal, and it is sent to the input port 1 of the first amplifier 9-1 by output port 2; The input port 1 of the first amplifier 9-1 is received the radiofrequency signal from the second filter 8-2 output port 2, and it is amplified to the required level of IQ demodulator 7, gives the input port 1 of IQ demodulator 7 then by output port 2; The radiofrequency signal that the input port 1 of IQ demodulator 7 receives from the first amplifier 9-1 output port 2, the local oscillator radiofrequency signal that input port 2 receives from local oscillation circuit 5 output ports 2, finish from radiofrequency signal to the down-conversion of baseband signal, and the I, the Q two-way differential analog signal that obtain after utilizing inner integrated AGC down-conversion be amplified to the level value with the ADC3 coupling, then the I that produces, Q two-way differential analog signal is given the second low pass circuit 4-2 respectively by output port 3 and output port 4 input port 1 and input port 2; The input port 1 of the second low pass circuit 4-2 and input port 2 receive I, the Q two-way differential analog signal from the output port 3 of IQ demodulator 7 and output port 4 transmissions respectively, filtering high fdrequency component is wherein given input port 1 and the input port 2 of ADC3 then filtered signal respectively by output port 3 and output port 4; ADC3 input port 1 and input port 2 receive I, the Q two-way differential analog signal that sends respectively from the second low pass circuit 4-2 output port 3 and output port 4 respectively, and it is become the baseband sampling signal, give the input port 2 of FPGA1 by output port 3.
The utility model compared with prior art has the following advantages:
1. the utility model adopts zero intermediate frequency, can realize the direct conversion between baseband signal and radiofrequency signal, circuit such as the needed crystal oscillator of double conversion unit, filter circuit, amplifying circuit, mixting circuit have been saved, therefore, it is small and exquisite to the utlity model has volume, simple in structure, lower-cost characteristics.
2. be integrated with agc circuit in the IQ demodulator on the utility model receiving end passage, and the dynamic gain scope reaches 69.5dB, no longer needed independently agc circuit on the radio frequency receiving end, can further simplify structure and the designing requirement of radio frequency receiving end.
3, described FPGA can realize multiple mode, the digital modulation and demodulation of multiple speed by the different modulation program of operation;
4, described local oscillation circuit 5 can produce the local oscillation signal in 62.5MHz to the 1.8GHz scope, and tranmitting frequency is flexible and changeable; And, after setting tranmitting frequency, can control local oscillation signal by FPGA1 and carry out positive and negative 5% frequency shift (FS) (for example, tranmitting frequency is set at 1GHz, then FPGA1 can control local oscillation signal and freely switches between 1050MHz at 950MHz, can satisfy certain adaptive frequency-selecting requirement.
Description of drawings
Fig. 1 is electrical schematic diagram of the present utility model.
Embodiment:
With reference to Fig. 1, the utility model comprises that FPGA1, DAC2, ADC3, the first low pass circuit 4-1, the second low pass circuit 4-2, local oscillation circuit 5, IQ modulator 6, IQ demodulator 7, the first filter 8-1, the second filter 8-2, the first amplifier 9-1, the second amplifier 9-2, radio frequency make a start 10, radio frequency receiving end 11, and embodiment presses Fig. 1 connection line.Wherein, the effect of FPGA1 is by the operation modulation program, and the modulation code word modulation is shaped to digital baseband signal, and by the operation demodulation process, demodulates the demodulation code word from the baseband sampling signal; The effect of DAC2 be that digital baseband signal is converted to I, Q two-way differential analog signal; The effect of ADC3 is that I, Q two-way differential analog signal are sampled, and produces the baseband sampling signal; The effect of the first low pass circuit 4-1 and the second low pass circuit 4-2 is that I, Q two-way differential analog signal are carried out low-pass filtering; The effect of local oscillation circuit 5 is to produce the radio-frequency (RF) local oscillator signal; The effect of IQ modulator 6 is to utilize the radio-frequency (RF) local oscillator signal, and I, Q two-way differential analog signal are upconverted to radio frequency; The effect of IQ demodulator 7 then is to utilize the radio-frequency (RF) local oscillator signal that radiofrequency signal is down-converted to zero-frequency, utilizes inner integrated AGC that this zero frequency signal is amplified to level value with the coupling of ADC3 simultaneously; The effect of the first filter 8-1 and the second filter 8-2 is the out of band components of filtering radiofrequency signal; The effect of the first amplifier 9-1 and the second amplifier 9-2 is that radiofrequency signal is amplified; Radio frequency 10 the effect of making a start is radiofrequency signal to be sent in the space go; The effect of radio frequency receiving end 11 is the signals that receive in the space, and it is converted to the signal of telecommunication.
The Cyclone Series FPGA chip that FPGA1 in the utility model adopts U.S. altera corp to produce can be selected concrete signal flexibly according to the requirement of working procedure.
DAC2 in the utility model and ADC3 adopt AD9763 and the AD9288 of U.S. AD company production respectively, also can change two-way ADC or the DAC of other model according to required signal bit wide.
The Si4133 chip that local oscillation circuit 5 adopts U.S. Silicon Laboratories company to produce in the utility model can produce the local oscillation signal in 62.5MHz to the 1.8GHz scope, and tranmitting frequency is flexible and changeable; And, after setting tranmitting frequency, can control local oscillation signal by FPGA1 and carry out positive and negative 5% frequency shift (FS) (for example, tranmitting frequency is set at 1GHz, then FPGA1 can control local oscillation signal and freely switches between 1050MHz at 950MHz), can satisfy certain adaptive frequency-selecting requirement.
AD8349 and AD8347 that IQ modulator 6 in the utility model and IQ demodulator 7 adopt U.S. AD company to produce respectively, wherein AD8347 inside is integrated with the AGC module, the dynamic gain scope has reached 69.5dB, can further simplify 11 structures and the designing requirement of radio frequency receiving end.
Claims (1)
1. miniaturization zero intermediate frequency transceiver comprises that FPGA (1), DAC (2), ADC (3), first low pass circuit (4-1), second low pass circuit (4-2), local oscillation circuit (5), IQ modulator (6), IQ demodulator (7), first filter (8-1), second filter (8-2), first amplifier (9-1), second amplifier (9-2), radio frequency make a start (10) and radio frequency receiving end (11); It is characterized in that:
The input port 3 of described FPGA (1) receives the modulation code word that upper-layer protocol sends, and by the operation modulation program, the modulation code word modulation is shaped to digital baseband signal, and this signal is sent to the input port 1 of DAC (2) by output port 2; Simultaneously, the input port 1 of FPGA (1) receives the baseband sampling signal that sends from ADC (3) output port 3, by the operation demodulation process, demodulates the demodulation code word, and sends to upper-layer protocol by output port 4; The digital baseband signal that the input port 1 of DAC (2) receives from FPGA (1) output port 2, it is converted into I, Q two-way differential analog signal, and gives input port 1 and the input port 2 of first low pass circuit (4-1) by output port 2 and output port 3 respectively; The input port 1 of first low pass circuit (4-1) and input port 2 receive I, the Q two-way differential analog signal from the output port 2 of DAC (2) and output port 3 transmissions respectively, filtering high fdrequency component wherein flows to signal by output port 3 and output port 4 input port 1 and the input port 2 of IQ modulator (6); Local oscillation circuit (5) produces the radio-frequency (RF) local oscillator signal, and gives the input port 3 of IQ modulator (6) and the input port 2 of IQ demodulator (7) it respectively by output port 1 and output port 2; The input port 1 of IQ modulator (6) and input port 2 receive respectively from the I of the output port 3 of first low pass circuit (4-1) and output port 4, Q two-way differential analog signal, input port 3 receives the radio-frequency (RF) local oscillator signal that sends from local oscillation circuit (5) output port 1, finish the up-conversion from the baseband signal to the radiofrequency signal, and radiofrequency signal is given the input port 1 of first filter (8-1) by output port 4; The input port 1 of first filter (8-1) receives the radiofrequency signal that the transmit port 4 from IQ modulator (6) sends, the out of band components of this signal of filtering, and filtered signal is sent to the input port 1 of second amplifier (9-2) by output port 2; The input port 1 of second amplifier (9-2) is received the signal from first filter (8-1) output port 2, it is amplified to radio frequency (10) the desired level value of making a start, by output port 2 signal after amplifying is sent to the make a start input port 1 of (10) of radio frequency then; The make a start input port 1 of (10) of radio frequency receives radiofrequency signal from the output port 2 of second amplifier (9-2), and it is sent in the space goes; And radio frequency receiving end (11) receives from the signal in the space, and gives the input port 1 of second filter (8-2) it by output port 1; The input port 1 of second filter (8-2) is received the signal from radio frequency receiving end (11) output port 1, and the filtering out of band components obtains with interior radiofrequency signal, and it is sent to the input port 1 of first amplifier (9-1) by output port 2; The input port 1 of first amplifier (9-1) is received the radiofrequency signal from second filter (8-2) output port 2, and it is amplified to the required level of IQ demodulator (7), gives the input port 1 of IQ demodulator (7) then by output port 2; The radiofrequency signal that the input port 1 of IQ demodulator (7) receives from first amplifier (9-1) output port 2, the local oscillator radiofrequency signal that input port 2 receives from local oscillation circuit (5) output port 2, finish from radiofrequency signal to the down-conversion of baseband signal, and the I, the Q two-way differential analog signal that obtain after utilizing inner integrated AGC down-conversion be amplified to the level value with the ADC3 coupling, gives input port 1 and the input port 2 of second low pass circuit (4-2) I, the Q two-way differential analog signal that produce respectively by output port 3 and output port 4 then; The input port 1 of second low pass circuit (4-2) and input port 2 receive I, the Q two-way differential analog signal from the output port 3 of IQ demodulator (7) and output port 4 transmissions respectively, filtering high fdrequency component is wherein given input port 1 and the input port 2 of ADC (3) then filtered signal respectively by output port 3 and output port 4; ADC (3) input port 1 and input port 2 receive I, the Q two-way differential analog signal that sends respectively from second low pass circuit (4-2) output port 3 and output port 4 respectively, it is become the baseband sampling signal, give the input port 2 of FPGA (1) by output port 3.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012207344904U CN203193625U (en) | 2012-12-28 | 2012-12-28 | Miniaturized zero intermediate frequency transceiver |
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| CN2012207344904U CN203193625U (en) | 2012-12-28 | 2012-12-28 | Miniaturized zero intermediate frequency transceiver |
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| CN203193625U true CN203193625U (en) | 2013-09-11 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103500318A (en) * | 2013-10-08 | 2014-01-08 | 南京航空航天大学 | SAW (Surface Acoustic Wave) reader receiving link circuit structure adopting ZIF (Zero Intermediate Frequency) IQ (In-phase Quadrature) demodulation technology and working method of SAW reader receiving link circuit structure |
| CN103973605A (en) * | 2013-12-18 | 2014-08-06 | 中国电子科技集团公司第五十四研究所 | Multi-rate burst self-adaptive communication device suitable for microwave communication |
| CN104851272A (en) * | 2015-05-21 | 2015-08-19 | 南京新联电子股份有限公司 | Small-size high-speed data transmission communication module applied to state grid II type concentrator |
| CN108337204A (en) * | 2017-12-26 | 2018-07-27 | 北京航天测控技术有限公司 | A kind of minimized wide-band vector signal up-converter circuit |
-
2012
- 2012-12-28 CN CN2012207344904U patent/CN203193625U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103500318A (en) * | 2013-10-08 | 2014-01-08 | 南京航空航天大学 | SAW (Surface Acoustic Wave) reader receiving link circuit structure adopting ZIF (Zero Intermediate Frequency) IQ (In-phase Quadrature) demodulation technology and working method of SAW reader receiving link circuit structure |
| CN103973605A (en) * | 2013-12-18 | 2014-08-06 | 中国电子科技集团公司第五十四研究所 | Multi-rate burst self-adaptive communication device suitable for microwave communication |
| CN103973605B (en) * | 2013-12-18 | 2017-06-27 | 中国电子科技集团公司第五十四研究所 | A kind of multi tate burst adaptive communication device for being suitable for microwave communication |
| CN104851272A (en) * | 2015-05-21 | 2015-08-19 | 南京新联电子股份有限公司 | Small-size high-speed data transmission communication module applied to state grid II type concentrator |
| CN104851272B (en) * | 2015-05-21 | 2018-04-06 | 南京新联电子股份有限公司 | Miniaturized high-speed number for state's net II type concentrators passes communication module |
| CN108337204A (en) * | 2017-12-26 | 2018-07-27 | 北京航天测控技术有限公司 | A kind of minimized wide-band vector signal up-converter circuit |
| CN108337204B (en) * | 2017-12-26 | 2020-12-25 | 北京航天测控技术有限公司 | Miniaturized broadband vector signal up-conversion circuit |
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Granted publication date: 20130911 |