CN203193588U - Delayed power-off switch based on CMOS (complementary metal oxide semiconductor) programmable frequency divider - Google Patents
Delayed power-off switch based on CMOS (complementary metal oxide semiconductor) programmable frequency divider Download PDFInfo
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- CN203193588U CN203193588U CN 201320181189 CN201320181189U CN203193588U CN 203193588 U CN203193588 U CN 203193588U CN 201320181189 CN201320181189 CN 201320181189 CN 201320181189 U CN201320181189 U CN 201320181189U CN 203193588 U CN203193588 U CN 203193588U
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Abstract
The utility model discloses a delayed power-off switch based on a CMOS (complementary metal oxide semiconductor) programmable frequency divider. The delayed power-off switch based on a CMOS programmable frequency divider comprises the CMOS programmable frequency divider, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a linked switch, a first triode, a second triode, a third triode, a first capacitor, a second capacitor, a third capacitor, a relay, a light-emitting diode, a voltage stabilizer tube, a potentiometer and a socket, wherein the core component of the delayed power-off switch disclosed by the utility model is the CMOS programmable frequency divider, and a timing time is adjustable; and the subsequent delay steps of an internal oscillator and a counter can be adjusted gear by gear, and a needed output timing range can be selected by changing the programming control level combination connected by a second BCD (binary coded decimal) code signal input end and a third BCD code signal input end. The delayed power-off switch is few in circuit peripheral components, high in timing accuracy, wide in timing range, flexible and reliable to use, and capable of automatically disconnecting a main power supply when the predetermined time is concluded by directly pressing the power supply switch after electricity utilization, without manual control.
Description
Technical field
The utility model relates to a kind of timing electronic switch, relates in particular to a kind of delay cut-off switch based on the CMOS programmable frequency divider.
Background technology
Timer circuit is much, but electricity consumption can guarantee at any time that electrical appliance finishes the time, again by predetermined time delay cutting power timer almost do not have.Along with the application of all kinds of electric equipments is extensive day by day, the demand of this type of timer is also more and more.As: projector needs delay cutting power when shutting down; Computer need wait for that when shutdown machine finishes delay cutting power behind the shutdown programm: will wait for also before the family expenses electromagnetic oven is cut off the electricity supply that could cut off this delay cutting power of electricity switch after machine cools off has just just satisfied above-mentioned requirements.
The utility model content
The purpose of this utility model provides a kind of delay cut-off switch based on the CMOS programmable frequency divider with regard to being in order to address the above problem.
The utility model is achieved through the following technical solutions above-mentioned purpose:
The utility model comprises the CMOS programmable frequency divider, first resistance to the, seven resistance, first diode to the, five diodes, linked switch, first triode, second triode, the 3rd triode, first electric capacity, second electric capacity, the 3rd electric capacity, relay, light-emitting diode, voltage-stabiliser tube, potentiometer and socket, the zero line while of AC power and an end of described socket, the negative pole of described the 3rd diode is connected with the positive pole of described second diode, the live wire while of described AC power is connected with first end of first switch of described linked switch and first end of described relay normally open switch, second end while of first switch of described linked switch and first end of described first resistance, first end of described first electric capacity, second end of described relay normally open switch and second end of described socket are connected, second end while of described first resistance and second end of described first electric capacity, the positive pole of described first diode is connected with the negative pole of described the 4th diode, the negative pole while of described first diode and the negative pole of described second diode, first end of described second electric capacity, first end of described relay, first end of the negative pole of described the 5th diode and described second resistance is connected, the anodal while of described the 4th diode and the positive pole of described the 3rd diode, second end of described second electric capacity is connected with the emitter of described the 3rd triode, second end of described relay is connected with the collector electrode of described the 3rd triode and the positive pole of described the 5th diode simultaneously, the base stage of described the 3rd triode is connected with first end of described the 3rd resistance, second end while of described second resistance and the negative pole of described voltage-stabiliser tube, first end of described the 4th resistance, the first binary-coded decimal signal output part of described CMOS programmable frequency divider, the second binary-coded decimal signal output part of described CMOS programmable frequency divider, the 3rd binary-coded decimal signal output part of described CMOS programmable frequency divider and first pulse input end of described CMOS programmable frequency divider are connected, the anodal of described voltage-stabiliser tube is connected with the negative pole of described light-emitting diode and second pulse signal input terminal of described CMOS programmable frequency divider simultaneously, second end of described the 4th resistance is connected with the positive pole of described light-emitting diode, second end while of described the 3rd resistance and the electrode input end of described CMOS programmable frequency divider, first end of described the 8th resistance, first end of described the 7th resistance, the emitter of described second triode, the 3rd pulse input end of the collector electrode of described first triode and described CMOS programmable frequency divider is connected, second end of described the 8th resistance is connected with the base stage of described first triode, second end of described the 7th resistance is connected with the base stage of described second triode, the collector electrode of described second triode is connected with first end of described potentiometer, second end of described potentiometer is connected with the sliding end of described potentiometer and first end of described the 6th resistance simultaneously, second end while of described the 6th resistance and first end of described the 5th resistance, first end of first end of described the 3rd electric capacity and the second switch of described linked switch is connected, second end of the second switch of described linked switch is connected with the emitter of described first triode, second end of described the 3rd electric capacity is connected with the 4th pulse input end of described CMOS programmable frequency divider, and second end of described the 5th resistance is connected with the 4th binary-coded decimal signal output part of described CMOS programmable frequency divider.
The beneficial effects of the utility model are:
Core parts of the present utility model are a kind of CMOS programmable frequency dividers, and timing is adjustable.Connect programming Control level combination by changing the second binary-coded decimal signal input part and the 3rd binary-coded decimal signal input part, can stepping adjust the follow-up time-delay progression of built-in vibration, counter, select the output timing range that needs.The circuit peripheral cell is few, the timing accuracy height, and timing range is wide, uses flexibility and reliability, can directly click mains switch when electricity consumption finishes, and general supply can automatic disconnection when you finish predetermined time, does not need Artificial Control.
Description of drawings
Fig. 1 is circuit structure schematic diagram of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing:
As shown in Figure 1: the utility model comprises CMOS programmable frequency divider IC, first resistance R, 1 to the 7th resistance R 7, the first diode D1 to the, five diode D5, linked switch, the first triode T1, the second triode T2, the 3rd triode T3, first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3, relay J, LED, voltage-stabiliser tube DW, potentiometer RP and socket CZ, the zero line while of AC power and the end of socket CZ, the negative pole of the 3rd diode D3 is connected with the positive pole of the second diode D2, the live wire while of AC power is connected with first end of the first switch S 1-1 of linked switch and first end of relay J normal open switch J1, second end while of the first switch S 1-1 of linked switch and first end of first resistance R 1, first end of first capacitor C 1, second end of relay J normal open switch J1 is connected with second end of socket CZ, second end while of first resistance R 1 and second end of first capacitor C 1, the positive pole of the first diode D1 is connected with the negative pole of the 4th diode D4, the negative pole while of the first diode D1 and the negative pole of the second diode D2, first end of second capacitor C 2, first end of relay J, the negative pole of the 5th diode D5 is connected with first end of second resistance R 2, the anodal while of the 4th diode D4 and the positive pole of the 3rd diode D3, second end of second capacitor C 2 is connected with the emitter of the 3rd triode D3, second end of relay J is connected with the collector electrode of the 3rd triode D3 and the positive pole of the 5th diode D5 simultaneously, the base stage of the 3rd triode D3 is connected with first end of the 3rd resistance R 3, second end while of second resistance R 2 and the negative pole of voltage-stabiliser tube DW, first end of the 4th resistance R 4, the first binary-coded decimal signal output part of CMOS programmable frequency divider IC, the second binary-coded decimal signal output part of CMOS programmable frequency divider IC, the 3rd binary-coded decimal signal output part of CMOS programmable frequency divider IC is connected with first pulse input end of CMOS programmable frequency divider IC, the anodal of voltage-stabiliser tube DW is connected with the negative pole of LED and second pulse signal input terminal of CMOS programmable frequency divider IC simultaneously, second end of the 4th resistance R 4 is connected with the positive pole of LED, second end while of the 3rd resistance R 3 and the electrode input end of CMOS programmable frequency divider IC, first end of the 8th resistance R 8, first end of the 7th resistance R 7, the emitter of the second triode D3, the collector electrode of the first triode T1 is connected with the 3rd pulse input end of CMOS programmable frequency divider IC, second end of the 8th resistance R 8 is connected with the base stage of the first triode T1, second end of the 7th resistance R 7 is connected with the base stage of the second triode T2, the collector electrode of the second triode T2 is connected with first end of potentiometer RP, second end of potentiometer RP is connected with the sliding end of potentiometer RP and first end of the 6th resistance R 6 simultaneously, second end while of the 6th resistance R 6 and first end of the 5th resistance R 5, first end of first end of the 3rd capacitor C 3 and the second switch D1-2 of linked switch is connected, second end of the second switch S1-2 of linked switch is connected with the emitter of the first triode T1, second end of the 3rd capacitor C 3 is connected with the 4th pulse input end of CMOS programmable frequency divider IC, and second end of the 5th resistance R 5 is connected with the 4th binary-coded decimal signal output part of CMOS programmable frequency divider IC.
As shown in Figure 1: utilize the 3rd pulse input end of CMOS programmable frequency divider IC to import the variation of high and low level and make the second triode T2 and the 3rd triode T3 of electronic switch, make clock ON/OFF circuit that separately timing resistor be arranged.Potentiometer RP is the linear potentiometer of 100K Ω.Here the second binary-coded decimal signal input part and the 3rd binary-coded decimal signal input part of CMOS programmable frequency divider IC are received high level, to select long timing mode, external timing resistor, the electric capacity of the 3rd pulse input end of CMOS programmable frequency divider IC is optional forr a short time like this.The 220V alternating current through delay cut-off switching circuit electric capacity through 1 step-down of first capacitor C, the first diode D1 to the, four diode D4 rectifications, 2 filtering of second capacitor C, obtain the direct voltage of about 15V, one the tunnel for relay J work, the voltage stabilizing that another route second resistance R 2 and voltage-stabiliser tube DW form is as the working power of CMOS programmable frequency divider IC.
As shown in Figure 1: CMOS programmable frequency divider IC has constituted back off timer with element on every side, here the first triode T1 and the second triode T2 are as electronic switch, the timing element that inserts CMOS programmable frequency divider IC is switched in conducting in turn by them, the utility model does not need the time-delay start, only need delay switching-off, so the timing resistor of time-delay start is zero (be set to the normally opened contact of switch, the energising back is closed).Begin circuit output when just linked switch closes and be in closure state all the time, output 220V civil power.Because the second binary-coded decimal signal input part and the 3rd binary-coded decimal signal input part of CMOS programmable frequency divider IC all connects low level, after the power on circuitry, at first can automatically perform reset operation, output low level after resetting drives the 3rd triode T3 and ends, and relay J is not worked, normal open switch J1 disconnects, civil power on the socket CZ is cut off, but because the timing resistor of time-delay start is zero, so circuit changes open state immediately over to.When linked switch was closed, the first switch S 1-1 of relay normally open contact J1 and linked switch also connect together, outwards exported the 220V civil power simultaneously.During the deenergization linked switch, circuit remains on definition status, CMOS programmable frequency divider IC output this moment high level, and the 3rd triode T3 conducting, relay J gets electric work, normal open switch J1 closure, socket CZ externally exports civil power.At this moment the second triode T2 leads and the first triode T1 ends, the timing resistor of clock circuit connects the 7th resistance R 7 by the base stage of the second triode T2, potentiometer RP and the 6th resistance R 6 are composed in series, the time-delay progression maximum of output this moment, regularly adjustable range is also the wideest, press the element of giving among the figure, by changing the resistance of potentiometer RP, the unused time can be adjusted in 5～12 minutes.
As shown in Figure 1: first resistance R 1 constitutes the power work indicating circuit for the current drain resistance of first capacitor C 1 after the power down, the 4th resistance R 4 with light-emitting diode, and the 5th diode D5 is the anti-pressure protection diode.
Claims (1)
1. delay cut-off switch based on the CMOS programmable frequency divider, it is characterized in that: comprise the CMOS programmable frequency divider, first resistance to the, seven resistance, first diode to the, five diodes, linked switch, first triode, second triode, the 3rd triode, first electric capacity, second electric capacity, the 3rd electric capacity, relay, light-emitting diode, voltage-stabiliser tube, potentiometer and socket, the zero line while of AC power and an end of described socket, the negative pole of described the 3rd diode is connected with the positive pole of described second diode, the live wire while of described AC power is connected with first end of first switch of described linked switch and first end of described relay normally open switch, second end while of first switch of described linked switch and first end of described first resistance, first end of described first electric capacity, second end of described relay normally open switch and second end of described socket are connected, second end while of described first resistance and second end of described first electric capacity, the positive pole of described first diode is connected with the negative pole of described the 4th diode, the negative pole while of described first diode and the negative pole of described second diode, first end of described second electric capacity, first end of described relay, first end of the negative pole of described the 5th diode and described second resistance is connected, the anodal while of described the 4th diode and the positive pole of described the 3rd diode, second end of described second electric capacity is connected with the emitter of described the 3rd triode, second end of described relay is connected with the collector electrode of described the 3rd triode and the positive pole of described the 5th diode simultaneously, the base stage of described the 3rd triode is connected with first end of described the 3rd resistance, second end while of described second resistance and the negative pole of described voltage-stabiliser tube, first end of described the 4th resistance, the first binary-coded decimal signal output part of described CMOS programmable frequency divider, the second binary-coded decimal signal output part of described CMOS programmable frequency divider, the 3rd binary-coded decimal signal output part of described CMOS programmable frequency divider and first pulse input end of described CMOS programmable frequency divider are connected, the anodal of described voltage-stabiliser tube is connected with the negative pole of described light-emitting diode and second pulse signal input terminal of described CMOS programmable frequency divider simultaneously, second end of described the 4th resistance is connected with the positive pole of described light-emitting diode, second end while of described the 3rd resistance and the electrode input end of described CMOS programmable frequency divider, first end of described the 8th resistance, first end of described the 7th resistance, the emitter of described second triode, the 3rd pulse input end of the collector electrode of described first triode and described CMOS programmable frequency divider is connected, second end of described the 8th resistance is connected with the base stage of described first triode, second end of described the 7th resistance is connected with the base stage of described second triode, the collector electrode of described second triode is connected with first end of described potentiometer, second end of described potentiometer is connected with the sliding end of described potentiometer and first end of described the 6th resistance simultaneously, second end while of described the 6th resistance and first end of described the 5th resistance, first end of first end of described the 3rd electric capacity and the second switch of described linked switch is connected, second end of the second switch of described linked switch is connected with the emitter of described first triode, second end of described the 3rd electric capacity is connected with the 4th pulse input end of described CMOS programmable frequency divider, and second end of described the 5th resistance is connected with the 4th binary-coded decimal signal output part of described CMOS programmable frequency divider.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320181189 CN203193588U (en) | 2013-04-11 | 2013-04-11 | Delayed power-off switch based on CMOS (complementary metal oxide semiconductor) programmable frequency divider |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320181189 CN203193588U (en) | 2013-04-11 | 2013-04-11 | Delayed power-off switch based on CMOS (complementary metal oxide semiconductor) programmable frequency divider |
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| CN203193588U true CN203193588U (en) | 2013-09-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103928965A (en) * | 2014-05-04 | 2014-07-16 | 可牛网络技术（北京）有限公司 | Charger and method and device for using charger |
| CN104470076A (en) * | 2014-11-21 | 2015-03-25 | 张金海 | Illuminating lamp multi-gear electronic time-delay switch |
| CN116494814A (en) * | 2023-06-30 | 2023-07-28 | 四川金信石信息技术有限公司 | Ordered charging switching integrated device and new energy automobile charging system |
-
2013
- 2013-04-11 CN CN 201320181189 patent/CN203193588U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103928965A (en) * | 2014-05-04 | 2014-07-16 | 可牛网络技术（北京）有限公司 | Charger and method and device for using charger |
| CN103928965B (en) * | 2014-05-04 | 2017-01-04 | 可牛网络技术（北京）有限公司 | A kind of charger and using method thereof and use device |
| CN104470076A (en) * | 2014-11-21 | 2015-03-25 | 张金海 | Illuminating lamp multi-gear electronic time-delay switch |
| CN116494814A (en) * | 2023-06-30 | 2023-07-28 | 四川金信石信息技术有限公司 | Ordered charging switching integrated device and new energy automobile charging system |
| CN116494814B (en) * | 2023-06-30 | 2023-09-05 | 四川金信石信息技术有限公司 | Ordered charging switching integrated device and new energy automobile charging system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130911 Termination date: 20140411 |