CN203181056U - Novel anti-interference modem - Google Patents
Novel anti-interference modem Download PDFInfo
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- CN203181056U CN203181056U CN 201320126679 CN201320126679U CN203181056U CN 203181056 U CN203181056 U CN 203181056U CN 201320126679 CN201320126679 CN 201320126679 CN 201320126679 U CN201320126679 U CN 201320126679U CN 203181056 U CN203181056 U CN 203181056U
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Abstract
The utility model discloses a novel anti-interference modem comprising a phase-locked loop circuit, a differential amplifier circuit, a filter circuit, and a level conversion circuit. The phase-locked loop circuit comprises a phase-locked loop integrated circuit, a first potentiometer, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a first resistor, a second resistor, and a third resistor. A first end of the first capacitor is an audio input end, and a second end of the first capacitor is respectively connected with a second pin of the phase-locked loop integrated circuit and a first end of the first resistor. A second end of the first resistor is connected with a first end of the second resistor, and a second end of the second resistor is connected with a third pin of the phase-locked loop integrated circuit. By arranging the phase-locked loop integrated circuit and the filter circuit, the phase-locked loop integrated circuit can be used to optimize the circuit of the modem, and the filter circuit can be used to filter the high frequency AC component, therefore the bandwidth of the tuner can be determined, and the anti-interference performance can be greatly improved.
Description
Technical field
The utility model relates to a kind of modulator-demodulator, particularly relates to a kind of New Anti-interference modulator-demodulator.
Background technology
Frequency modulated transmitter at first is modulated to frequency-modulated wave with audio signal and high frequency carrier, and the frequency of high frequency carrier is changed with audio signal, the high-frequency signal that produces is amplified again, excitation, power amplifier and a series of impedance matching make signal output to antenna, the device that sends.Frequency modulated transmitter needs an orthogonal mixer and modulator-demodulator to reconcile signal, and there are shortcomings such as circuit complexity and anti-interference difference in traditional modulator-demodulator.
The utility model content
The purpose of this utility model is to provide a kind of circuit simple, anti-interference effective New Anti-interference modulator-demodulator in order to address the above problem.
The utility model is achieved through the following technical solutions:
A kind of New Anti-interference modulator-demodulator, comprise phase-locked loop circuit, differential amplifier circuit, filter circuit and level shifting circuit, described phase-locked loop circuit comprises phase-locked loop intergrated circuit, first potentiometer, first electric capacity, second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, first resistance, second resistance and the 3rd resistance, first end of described first electric capacity is audio input end, second end of described first electric capacity is connected with second pin of described phase-locked loop intergrated circuit and first end of described first resistance respectively, second end of described first resistance is connected with first end of described second resistance respectively, second end of described second resistance is connected with the 3rd pin of described phase-locked loop intergrated circuit, first pin of described phase-locked loop intergrated circuit is connected with first end of described second electric capacity, second end of described second electric capacity is connected with first end of described the 3rd electric capacity and the 9th pin of described phase-locked loop intergrated circuit respectively, the 8th pin of described phase-locked loop intergrated circuit is connected with first end of described the 3rd resistance and first end of described the 6th electric capacity respectively, second end of described the 3rd resistance is connected with first end of described first potentiometer, second end of described first potentiometer all is connected with first end of described the 4th electric capacity with the sliding end of described first potentiometer, the second end ground connection of described the 4th electric capacity, the tenth pin of described phase-locked loop intergrated circuit is connected with first end of described the 5th electric capacity, second end of described the 5th electric capacity is connected with second end of described the 6th electric capacity respectively, described filter circuit comprises the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, the 8th resistance, the 9th resistance, the tenth resistance, the 11 resistance, the 12 resistance, the 13 resistance and second amplifier, first end of described the 11 resistance is connected with the output of described differential amplifier circuit, second end of described the 11 resistance is connected with first end of described the 8th electric capacity and first end of described the tenth resistance respectively, second end of described the tenth resistance is connected with first end of described the 9th resistance and first end of described the tenth electric capacity respectively, the second end ground connection of described the tenth electric capacity, second end of described the 9th resistance is connected with first end of described the 7th electric capacity and first end of described the 8th resistance respectively, second end of described the 7th electric capacity is connected with first end of described the 12 resistance respectively, second end of described the 12 resistance is connected with the negative input of described second amplifier and first end of described the 13 resistance respectively, second end of described the 8th resistance is connected with first end of described the 9th electric capacity and the electrode input end of described second amplifier respectively, the second end ground connection of described the 9th electric capacity.
Further, described differential amplifier circuit comprises the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance and first amplifier, first end of described the 4th resistance is connected with the 7th pin of described phase-locked loop intergrated circuit, second end of described the 4th resistance is connected with the electrode input end of described first amplifier and first end of described the 5th resistance respectively, the second end ground connection of described the 5th resistance, first end of described the 6th resistance is connected with the 6th pin of described phase-locked loop intergrated circuit, second end of described the 6th resistance is connected with the negative input of described first amplifier and first end of described the 7th resistance respectively, and second end of described the 7th resistance is connected with the output of described first amplifier.
Further, described level shifting circuit comprises the 14 resistance, the 15 resistance, the 16 resistance, the 17 resistance, the 3rd amplifier, the 11 electric capacity, second potentiometer and ammeter, first end of described the 14 resistance is connected with the negative input of described the 3rd amplifier, the electrode input end of described the 3rd amplifier is connected with first end of described ammeter and first end of described the 11 electric capacity respectively, second end of described ammeter and second end of described the 11 electric capacity are connected with first end of described the 17 resistance, second end of described the 17 resistance is connected with first end of described the 16 resistance, second end of described the 16 resistance is connected with first end of described the 14 resistance and first end of the 15 resistance respectively, and second end of described the 15th resistance is connected with the sliding end of described second potentiometer.
The beneficial effects of the utility model are:
By phase-locked loop intergrated circuit and filter circuit are set, by adopting phase-locked loop intergrated circuit to optimize the circuit of modulator-demodulator, by filter circuit, can filter the high-frequency ac component, and determined the bandwidth of tuner to have improved interference free performance of the present utility model greatly.
Description of drawings
Fig. 1 is the circuit diagram of a kind of New Anti-interference modulator-demodulator of the utility model.
Embodiment
The utility model is described in further detail below in conjunction with drawings and the specific embodiments:
As shown in Figure 1, a kind of New Anti-interference modulator-demodulator of the utility model, comprise phase-locked loop circuit, differential amplifier circuit, filter circuit and level shifting circuit, described phase-locked loop circuit comprises phase-locked loop intergrated circuit IC, the first potentiometer RP1, first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, the 6th capacitor C 6, first resistance R 1, second resistance R 2 and the 3rd resistance R 3, first end of described first capacitor C 1 is audio input end, second end of described first capacitor C 1 is connected with second pin of described phase-locked loop intergrated circuit IC and first end of described first resistance R 1 respectively, second end of described first resistance R 1 is connected with first end of described second resistance R 2 respectively, second end of described second resistance R 2 is connected with the 3rd pin of described phase-locked loop intergrated circuit IC, first pin of described phase-locked loop intergrated circuit IC is connected with first end of described second capacitor C 2, second end of described second capacitor C 2 is connected with first end of described the 3rd capacitor C 3 and the 9th pin of described phase-locked loop intergrated circuit IC respectively, the 8th pin of described phase-locked loop intergrated circuit IC is connected with first end of described the 3rd resistance R 3 and first end of described the 6th capacitor C 6 respectively, second end of described the 3rd resistance R 3 is connected with first end of the described first potentiometer RP1, second end of the described first potentiometer RP1 all is connected with first end of described the 4th capacitor C 4 with the sliding end of the described first potentiometer RP1, the second end ground connection of described the 4th capacitor C 4, the tenth pin of described phase-locked loop intergrated circuit IC is connected with first end of described the 5th capacitor C 5, second end of described the 5th capacitor C 5 is connected with second end of described the 6th capacitor C 6 respectively, described filter circuit comprises the 7th capacitor C 7, the 8th capacitor C 8, the 9th capacitor C 9, the tenth capacitor C 10, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the 12 resistance R 12, the 13 resistance R 13 and the second amplifier A2, first end of described the 11 resistance R 11 is connected with the output of described differential amplifier circuit, second end of described the 11 resistance R 11 is connected with first end of described the 8th capacitor C 8 and first end of described the tenth resistance R 10 respectively, second end of described the tenth resistance R 10 is connected with first end of described the 9th resistance R 9 and first end of described the tenth capacitor C 10 respectively, the second end ground connection of described the tenth capacitor C 10, second end of described the 9th resistance R 9 is connected with first end of described the 7th capacitor C 7 and first end of described the 8th resistance R 8 respectively, second end of described the 7th capacitor C 7 is connected with first end of described the 12 resistance R 12 respectively, second end of described the 12 resistance R 12 is connected with the negative input of the described second amplifier A2 and first end of described the 13 resistance R 13 respectively, second end of described the 8th resistance R 8 is connected with first end of described the 9th capacitor C 9 and the electrode input end of the described second amplifier A2 respectively, the second end ground connection of described the 9th capacitor C 9.
Described differential amplifier circuit comprises the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7 and the first amplifier A1, first end of described the 4th resistance R 4 is connected with the 7th pin of described phase-locked loop intergrated circuit IC, second end of described the 4th resistance R 4 is connected with the electrode input end of the described first amplifier A1 and first end of described the 5th resistance R 5 respectively, the second end ground connection of described the 5th resistance R 5, first end of described the 6th resistance R 6 is connected with the 6th pin of described phase-locked loop intergrated circuit IC, second end of described the 6th resistance R 6 is connected with the negative input of the described first amplifier A1 and first end of described the 7th resistance R 7 respectively, and second end of described the 7th resistance R 7 is connected with the output of the described first amplifier A1.
Described level shifting circuit comprises the 14 resistance R 14, the 15 resistance R 15, the 16 resistance R 16, the 17 resistance R 17, the 3rd amplifier A3, the 11 capacitor C 11, the second potentiometer RP2 and ammeter mA, first end of described the 14 resistance R 14 is connected with the negative input of described the 3rd amplifier A3, the electrode input end of described the 3rd amplifier A3 is connected with first end of described ammeter mA and first end of described the 11 capacitor C 11 respectively, second end of described ammeter mA is connected with first end of described the 17 resistance R 17 with second end of described the 11 capacitor C 11, second end of described the 17 resistance R 17 is connected with first end of described the 16 resistance R 16, second end of described the 16 resistance R 16 is connected with first end of described the 14 resistance R 14 and first end of the 15 resistance R 15 respectively, and second end of described the 15th resistance R 15 is connected with the sliding end of the described second potentiometer RP2.
Claims (3)
1. New Anti-interference modulator-demodulator, it is characterized in that: comprise phase-locked loop circuit, differential amplifier circuit, filter circuit and level shifting circuit, described phase-locked loop circuit comprises phase-locked loop intergrated circuit, first potentiometer, first electric capacity, second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, first resistance, second resistance and the 3rd resistance, first end of described first electric capacity is audio input end, second end of described first electric capacity is connected with second pin of described phase-locked loop intergrated circuit and first end of described first resistance respectively, second end of described first resistance is connected with first end of described second resistance respectively, second end of described second resistance is connected with the 3rd pin of described phase-locked loop intergrated circuit, first pin of described phase-locked loop intergrated circuit is connected with first end of described second electric capacity, second end of described second electric capacity is connected with first end of described the 3rd electric capacity and the 9th pin of described phase-locked loop intergrated circuit respectively, the 8th pin of described phase-locked loop intergrated circuit is connected with first end of described the 3rd resistance and first end of described the 6th electric capacity respectively, second end of described the 3rd resistance is connected with first end of described first potentiometer, second end of described first potentiometer all is connected with first end of described the 4th electric capacity with the sliding end of described first potentiometer, the second end ground connection of described the 4th electric capacity, the tenth pin of described phase-locked loop intergrated circuit is connected with first end of described the 5th electric capacity, second end of described the 5th electric capacity is connected with second end of described the 6th electric capacity respectively, described filter circuit comprises the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, the 8th resistance, the 9th resistance, the tenth resistance, the 11 resistance, the 12 resistance, the 13 resistance and second amplifier, first end of described the 11 resistance is connected with the output of described differential amplifier circuit, second end of described the 11 resistance is connected with first end of described the 8th electric capacity and first end of described the tenth resistance respectively, second end of described the tenth resistance is connected with first end of described the 9th resistance and first end of described the tenth electric capacity respectively, the second end ground connection of described the tenth electric capacity, second end of described the 9th resistance is connected with first end of described the 7th electric capacity and first end of described the 8th resistance respectively, second end of described the 7th electric capacity is connected with first end of described the 12 resistance respectively, second end of described the 12 resistance is connected with the negative input of described second amplifier and first end of described the 13 resistance respectively, second end of described the 8th resistance is connected with first end of described the 9th electric capacity and the electrode input end of described second amplifier respectively, the second end ground connection of described the 9th electric capacity.
2. New Anti-interference modulator-demodulator according to claim 1, it is characterized in that: described differential amplifier circuit comprises the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance and first amplifier, first end of described the 4th resistance is connected with the 7th pin of described phase-locked loop intergrated circuit, second end of described the 4th resistance is connected with the electrode input end of described first amplifier and first end of described the 5th resistance respectively, the second end ground connection of described the 5th resistance, first end of described the 6th resistance is connected with the 6th pin of described phase-locked loop intergrated circuit, second end of described the 6th resistance is connected with the negative input of described first amplifier and first end of described the 7th resistance respectively, and second end of described the 7th resistance is connected with the output of described first amplifier.
3. New Anti-interference modulator-demodulator according to claim 1, it is characterized in that: described level shifting circuit comprises the 14 resistance, the 15 resistance, the 16 resistance, the 17 resistance, the 3rd amplifier, the 11 electric capacity, second potentiometer and ammeter, first end of described the 14 resistance is connected with the negative input of described the 3rd amplifier, the electrode input end of described the 3rd amplifier is connected with first end of described ammeter and first end of described the 11 electric capacity respectively, second end of described ammeter and second end of described the 11 electric capacity are connected with first end of described the 17 resistance, second end of described the 17 resistance is connected with first end of described the 16 resistance, second end of described the 16 resistance is connected with first end of described the 14 resistance and first end of the 15 resistance respectively, and second end of described the 15 resistance is connected with the sliding end of described second potentiometer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320126679 CN203181056U (en) | 2013-03-20 | 2013-03-20 | Novel anti-interference modem |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320126679 CN203181056U (en) | 2013-03-20 | 2013-03-20 | Novel anti-interference modem |
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| Publication Number | Publication Date |
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| CN203181056U true CN203181056U (en) | 2013-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201320126679 Expired - Fee Related CN203181056U (en) | 2013-03-20 | 2013-03-20 | Novel anti-interference modem |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065843A (en) * | 2013-03-20 | 2014-09-24 | 成都世旗电子科技有限公司 | Novel anti-interference modulator-demodulator |
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2013
- 2013-03-20 CN CN 201320126679 patent/CN203181056U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065843A (en) * | 2013-03-20 | 2014-09-24 | 成都世旗电子科技有限公司 | Novel anti-interference modulator-demodulator |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130904 Termination date: 20140320 |