CN203178792U - Control apparatus for general control bus processor - Google Patents
Control apparatus for general control bus processor Download PDFInfo
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- CN203178792U CN203178792U CN2013201740131U CN201320174013U CN203178792U CN 203178792 U CN203178792 U CN 203178792U CN 2013201740131 U CN2013201740131 U CN 2013201740131U CN 201320174013 U CN201320174013 U CN 201320174013U CN 203178792 U CN203178792 U CN 203178792U
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- control chip
- cpld
- bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The utility model provides a control apparatus for a general control bus processor, which is characterized by comprising a CPLD control module, an ARM core processor module and an RS 485 interface circuit. The RS 485 interface circuit comprises an RS 485 communication circuit, a level converting circuit and a power supply interface circuit. The CPLD control module comprises a control chip, and the control chip is an EPM 240 chip. The ARM core processor module comprises a master control chip, the master control chip is an STM 32 F 103 VE chip, the master control chip is first connected with the RS 485 communication chip of a host computer and a CPLD control chip, and then is directly communicated with an RS 485 bus direct digital controller (DDC) through the CPLD control chip. According to the control apparatus for a general control bus processor, on-site communication with the host computer is achieved, simultaneously, a plurality of RS 485 bus direct digital controllers (DDC) are controlled.
Description
Technical field
The utility model relates to a kind of automatic building control system, particularly discloses a kind of general controls bus processor control device, has realized the control device of RS485 bus communication and control RS485 interface direct digital controller (DDC) (DDC).
Background technology
In recent years, along with the rapid emergence of China's rapid economy development and real estate market, industrial building is more strong to the demand of intelligent building control product.And the intelligent building that often uses on the market control product is based on the total line products of LON, thus the inconvenience of having given field adjustable, maintenance, mounting strap.
For field control, the present controller that is based on the LON bus that generally uses, this just requires the commissioning staff can skillfully use programming language, the interface configuration of this controller, project field adjustable difficulty is big, wayward on the other hand, therefore will inevitably produce many problems in the work progress at the scene.
Summary of the invention
The purpose of this utility model is to address the deficiencies of the prior art, design a kind of general controls bus processor control device, this device communicates by ModBUS RTU bus protocol and host computer, what slave computer then used is ModBUS ASCII bus protocol, realized that problems such as satisfying industry spot by serial communication controlling commonly used controls, and the project field adjustable difficulty that exists for prior art is big, wayward provide practicable solution and technological means.
The utility model is achieved in that a kind of general controls bus processor control device, it is characterized in that: comprise the CPLD control module, ARM core processor module and RS485 interface circuit three parts are formed, described RS485 interface circuit then is by the RS485 telecommunication circuit, level shifting circuit and power interface circuit are formed, described CPLD control module comprises a control chip, described control chip is the EPM240 chip, described ARM core processor module comprises a main control chip, described main control chip is the STM32F103VE chip, this chip links with host computer RS485 communication chip and CPLD control chip earlier, communicates by letter with RS485 bus direct digital controller (DDC) (DDC) by the CPLD control chip.The EPM240 chip that the control chip of described CPLD control module is produced for U.S. altera corp, and the main control chip of ARM kernel control module is the STM32F103VE chip that company limited of STMicw Electronics (STMicroelectronics) produces.
The beneficial effects of the utility model are: the utility model is integrated with CPLD chip, ARM chip, RS485 telecommunication circuit, power interface circuit and level shifting circuit etc., realizes and the communicating by letter and control a large amount of RS485 bus direct digital controller (DDC)s (DDC) simultaneously of host computer.
Description of drawings
Fig. 1 is the utility model structured flowchart.
Embodiment
With reference to the accompanying drawings, the utility model is a kind of general controls bus processor control device, its structure comprises CPLD control module, ARM core processor module and RS485 interface circuit three parts, and wherein the RS485 interface circuit comprises a RS485 telecommunication circuit of communicating by letter with host computer, four RS485 telecommunication circuit, level shifting circuit and power interface circuits of communicating by letter with RS485 bus direct digital controller (DDC) (DDC).The EPM240 chip that the control chip of CPLD control module is produced for U.S. altera corp, and the main control chip of ARM kernel control module is the STM32F103VE chip that company limited of STMicw Electronics (STMicroelectronics) produces.
The concrete course of work of the present utility model is as follows:
After the normal startup of the utility model, host computer sends order to ARM core processor module by the RS485 bus interface, by serial ports the CPLD control module is issued in order more after treatment, sends to corresponding slave computer by the RS485 bus interface again.
The utility model uses common RS485 bus interface, host computer ModBUS rtu protocol, what slave computer was used then is the ModBUS ASCII protocol, realized satisfying industry spot control by serial line interface control commonly used, for problems such as project field adjustable difficulty is big, wayward provide practicable solution and technological means.
Above embodiment is only for the usefulness that the utility model is described; but not to restriction of the present utility model; those skilled in the art are under the situation that does not break away from spirit and scope of the present utility model; can also make various being equal to or equivalent conversion or variation; its technical scheme also should belong to category of the present utility model, and protection domain of the present utility model limits with claim of the present utility model and is as the criterion.
Claims (2)
1. general controls bus processor control device, it is characterized in that: comprise the CPLD control module, ARM core processor module and RS485 interface circuit three parts are formed, described RS485 interface circuit then is by the RS485 telecommunication circuit, level shifting circuit and power interface circuit are formed, described CPLD control module comprises a control chip, described control chip is the EPM240 chip, described ARM core processor module comprises a main control chip, described main control chip is the STM32F103VE chip, this chip links with host computer RS485 communication chip and CPLD control chip earlier, communicates by letter with RS485 bus direct digital controller (DDC) DDC by the CPLD control chip.
2. according to the described general controls bus processor of claim 1 control device, it is characterized in that: the EPM240 chip that the control chip of described CPLD control module adopts U.S. altera corp to produce, and the STM32F103VE chip that the main control chip of ARM kernel control module adopts STMicroelectronics company limited of STMicw Electronics to produce.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2013201740131U CN203178792U (en) | 2013-04-09 | 2013-04-09 | Control apparatus for general control bus processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2013201740131U CN203178792U (en) | 2013-04-09 | 2013-04-09 | Control apparatus for general control bus processor |
Publications (1)
Publication Number | Publication Date |
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CN203178792U true CN203178792U (en) | 2013-09-04 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN2013201740131U Expired - Fee Related CN203178792U (en) | 2013-04-09 | 2013-04-09 | Control apparatus for general control bus processor |
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CN (1) | CN203178792U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104267651A (en) * | 2014-10-27 | 2015-01-07 | 上海龙创节能***股份有限公司 | Bus communication based digital value input and output module |
-
2013
- 2013-04-09 CN CN2013201740131U patent/CN203178792U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104267651A (en) * | 2014-10-27 | 2015-01-07 | 上海龙创节能***股份有限公司 | Bus communication based digital value input and output module |
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Legal Events
Date | Code | Title | Description |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130904 Termination date: 20180409 |