CN203165869U - Wafer testing loading board and wafer testing machine platform - Google Patents
Wafer testing loading board and wafer testing machine platform Download PDFInfo
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- CN203165869U CN203165869U CN 201220729498 CN201220729498U CN203165869U CN 203165869 U CN203165869 U CN 203165869U CN 201220729498 CN201220729498 CN 201220729498 CN 201220729498 U CN201220729498 U CN 201220729498U CN 203165869 U CN203165869 U CN 203165869U
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Abstract
The utility model relates to a wafer testing loading board and a wafer testing machine platform provided with the same. The loading board is arranged below a probe of the wafer testing machine platform, such that metal bumps on the wafer testing loading board can contact with pads on a wafer, and testing can be performed through the above manner. The wafer testing loading board and the wafer testing machine platform of the utility model are characterized in that a method in which the wafer testing loading board is utilized is adopted to replace a traditional method in which a probe is utilized to directly test the wafer, and therefore, the probe can be prevented from being contaminated, and the wafer testing loading board can be replaced fast, and thus, it does not need to spend a large quantity of time in probe cleaning and cost; and further, the test bumps of the wafer testing loading board are adopted to contact with the contact points of chips, traces will be prevented from being left, and therefore, a product can be cleaner and more complete.
Description
Technical field
The utility model relates to a kind of wafer test board, particularly disposes the wafer test board of replaceable wafer test support plate relevant for a kind of usefulness.
Background technology
In semiconductor technology, usually need detect the step of disk, its main purpose is will be at cutting semiconductor disk (wafer) before, probe (probe) with conductivity contacts each chip (die) on the disk earlier, to carry out checking, and the detection defective products, this process is also referred to as wafer level test (Wafer Level Test; WLT).
In present wafer level test process, all be to use probe up to contacting with weld pad (pad) on the chip, to test its electrical characteristic and to draw the chip signal, cooperate peripheral test instrument and software control to reach the purpose of automatic measurement again; And underproof chip can be put signs on, then when chip be unit when cutting into independently chip according to chip, the defective chip that indicates mark can be eliminated by wash one's face.Yet, have hundreds to tens thousand of chips owing to form on the semiconductor wafer, so when testing a semiconductor wafer, need expend the considerable time, and when disk quantity increases, also can cause the rising of cost.
In order to solve the problem points of aforementioned WLT, have at present in wafer test board configuration with hundreds of to tens thousand of probes, and make these probes direct with semiconductor wafer on all chips or semiconductor wafer on FWLT (the Full Wafer Level Test that once contacts of about at least 1/4 to 1/2 chip; The test of wholecircle chip level) method is carried out the wafer level test.Clearly, utilize FWLT, can do the detection of wholecircle sheet faster, economize many times of technology with letter.
Yet, have hundreds to tens thousand of chips because forming on the semiconductor wafer, in the weld pad on probe and the chip repeatedly and after intensive the contact, it can stain pollutant at probe, and may cause detecting inefficacy; So normally the mode by regular clear pin solves; Right because wafer test is to calculate testing expense with the time, so when needed during Chang Qingzhen, except meeting need expend a large amount of man-hours, also can reduce tester's income; In addition, because probe be very thin syringe needle, by the chip that probe contacts, understand staying the measurement vestige at chip, may cause whether can't differentiate be the price that new chip influences chip.
The utility model content
The purpose of this utility model is to provide a kind of wafer test support plate and wafer test board, to improve the defective that exists in the known technology.
For achieving the above object, the wafer test support plate that the utility model provides comprises:
One printed circuit board (PCB), has a upper surface and with respect to a lower surface of this upper surface, upper surface at this printed circuit board (PCB) has a plurality of first electric connection points, have a plurality of second at the lower surface of this printed circuit board (PCB) and electrically connect points, its those first electrically connect point and second electrically connect point and electrically connect each other with those;
One elastic film layer has a upper surface and with respect to a lower surface of this upper surface, has the through hole that a plurality of upper surfaces by this elastic film layer are through to the lower surface of this elastic film layer in this elastic film layer;
A plurality of metal materials are inserted those through holes, and those metal materials that are positioned at those through holes form a plurality of weld pads of going up in the upper surface of this elastic film layer, form a plurality of weld pads down in the lower surface of this elastic film layer; And
A plurality of pins have one first end and one second end, and this first end forms a tie point, and this second end forms a metal coupling; Wherein, this elastic film layer connects the lower surface of this printed circuit board (PCB), and those second electric connection points and weld pad electric connection on those, and those pins connect the lower surface of this elastic film layer, and those weld pad and electric connections of those tie points down.
Described wafer test support plate, wherein this elastic film layer is a macromolecular material.
Described wafer test support plate, wherein this macromolecular material is polyimides.
Described wafer test support plate, wherein those through holes of this elastic film layer form in the etch process mode.
Described wafer test support plate, wherein this metal material is to deposit or electroplating technique is inserted those through holes.
Described wafer test support plate, wherein those metal couplings are that the mode that deposits forms.
Described wafer test support plate, wherein those metal couplings are that the mode of electroplating forms.
Described wafer test support plate wherein has a plurality of distributions in this printed circuit board (PCB), with those first electric connection points and those second electric connection point electric connections.
Described wafer test support plate, wherein this pin is that mode with etch process forms.
The wafer test board that the utility model provides in order to a plurality of chips on the disk are tested, comprising:
One probe base has a upper surface and with respect to a lower surface of this upper surface, has plurality of probes in this probe base, and those probes are to be through to this lower surface by this upper surface, and whenever this probe forms probe upper end and a probe lower end;
One substrate, has a upper surface and with respect to a lower surface of this upper surface, the lower surface of this substrate is connected in the upper surface of this probe base, this substrate has a plurality of distributions, whenever this distribution forms one first end in the upper surface of this substrate, lower surface in this substrate forms one second end, and this of those distributions second end is electrically connected at this probe upper end of those probes;
One measuring head has a base, and this base is connected in the upper surface of this substrate, and electrically connects this first end of those distributions;
Wherein this wafer test board is characterised in that also and comprises:
One wafer test support plate is the lower surface that is connected in this probe base, and this wafer test support plate comprises:
One printed circuit board (PCB), has a upper surface and with respect to a lower surface of this upper surface, upper surface at this printed circuit board (PCB) has a plurality of first electric connection points, lower surface at this printed circuit board (PCB) has a plurality of second electric connection points, its those first electrically connect point and second electrically connect point and electrically connect each other with those, and those first electrically connect some system and are electrically connected at those probe lower ends;
One elastic film layer has a upper surface and with respect to a lower surface of this upper surface, has the through hole that a plurality of upper surfaces by this elastic film layer are through to the lower surface of this elastic film layer in this elastic film layer;
A plurality of metal materials are inserted those through holes, and those metal materials that are positioned at those through holes form a plurality of weld pads of going up in the upper surface of this elastic film layer, form a plurality of weld pads down in the lower surface of this elastic film layer; And
A plurality of pins have one first end and one second end, and this first end forms a tie point, and this second end forms a metal coupling;
Wherein, this elastic film layer connects the lower surface of this printed circuit board (PCB), and those second electric connection points and weld pad electric connection on those, and those pins connect the lower surface of this elastic film layer, and those are weld pad and the electric connection of those tie points down, by this metal coupling on those pins those chips is tested.
Described wafer test board, wherein this elastic film layer is a macromolecular material.
Described wafer test board, wherein this macromolecular material is polyimides.
Described wafer test board, wherein those through holes of this elastic film layer are that mode with etch process forms.
Described wafer test board, wherein this metal material is to deposit or electroplating technique is inserted those through holes.
Described wafer test board, wherein those metal couplings are that the mode that deposits forms.
Described wafer test board, wherein those metal couplings are that the mode of electroplating forms.
Described wafer test board wherein has a plurality of distributions in this printed circuit board (PCB), with those first electric connection points and those second electric connection point electric connections.
Described wafer test board, wherein this pin is that mode with etch process forms.
The utility model also provides a kind of wafer test support plate, comprising:
One printed circuit board (PCB), has a upper surface and with respect to a lower surface of this upper surface, upper surface at this printed circuit board (PCB) has a plurality of first electric connection points, have a plurality of second at the lower surface of this printed circuit board (PCB) and electrically connect points, its those first electrically connect point and second electrically connect point and electrically connect each other with those;
One elastic film layer has a upper surface and with respect to a lower surface of this upper surface, has the through hole that a plurality of upper surfaces by this elastic film layer are through to the lower surface of this elastic film layer in this elastic film layer;
A plurality of metal materials are inserted those through holes, and those metal materials that are positioned at those through holes form a plurality of weld pads of going up in the upper surface of this elastic film layer, form a plurality of weld pads down in the lower surface of this elastic film layer; And
A plurality of metal couplings are formed on those following weld pads;
Wherein, this elastic film layer connects the lower surface of this printed circuit board (PCB), and those second electric connection points and weld pad electric connection on those.
Described wafer test support plate, wherein this elastic film layer is a macromolecular material.
Described wafer test support plate, wherein this macromolecular material is polyimides.
Described wafer test support plate, wherein those through holes of this elastic film layer are that mode with etch process forms.
Described wafer test support plate, wherein this metal material is to deposit or electroplating technique is inserted those through holes.
Described wafer test support plate, wherein those metal couplings are that the mode that deposits forms.
Described wafer test support plate wherein forms in the mode of electroplating in those metal couplings.
Described wafer test support plate wherein has a plurality of distributions in this printed circuit board (PCB), with those first electric connection points and those second electric connection point electric connections.
The utility model also provides a kind of wafer test board, in order to a plurality of chips on the disk are tested, comprising:
One probe base has a upper surface and with respect to a lower surface of this upper surface, has plurality of probes in this probe base, and those probes are through to this lower surface by this upper surface, and whenever this probe forms probe upper end and a probe lower end;
One substrate, has a upper surface and with respect to a lower surface of this upper surface, the lower surface of this substrate is connected in the upper surface of this probe base, this substrate has a plurality of distributions, whenever this distribution forms one first end in the upper surface of this substrate, lower surface in this substrate forms one second end, and this of those distributions second end is electrically connected at this probe upper end of those probes;
One measuring head has a base, and this base is connected in the upper surface of this substrate, and electrically connects this first end of those distributions;
Wherein this wafer test board is characterised in that also and comprises:
One wafer test support plate is connected in the lower surface of this probe base, and this wafer test support plate comprises:
One printed circuit board (PCB), has a upper surface and with respect to a lower surface of this upper surface, upper surface at this printed circuit board (PCB) has a plurality of first electric connection points, lower surface at this printed circuit board (PCB) has a plurality of second electric connection points, its those first electrically connect point and second electrically connect point and electrically connect each other with those, and those first electrically connect some system and are electrically connected at those probe lower ends;
One elastic film layer has a upper surface and with respect to a lower surface of this upper surface, has the through hole that a plurality of upper surfaces by this elastic film layer are through to the lower surface of this elastic film layer in this elastic film layer;
A plurality of metal materials are inserted those through holes, and those metal materials that are positioned at those through holes form a plurality of weld pads of going up in the upper surface of this elastic film layer, form a plurality of weld pads down in the lower surface of this elastic film layer; And
A plurality of metal couplings are formed on those following weld pads;
Wherein, this elastic film layer connects the lower surface of this printed circuit board (PCB), and those second electric connection points and weld pad electric connection on those, and by at those metal couplings those chips being tested.
Described wafer test board, wherein this elastic film layer is a macromolecular material.
Described wafer test board, wherein this macromolecular material is polyimides.
Described wafer test board, wherein those through holes of this elastic film layer are that mode with etch process forms.
Described wafer test board, wherein this metal material is to deposit or electroplating technique is inserted those through holes.
Described wafer test board, wherein those metal couplings are that the mode that deposits forms.
Described wafer test board, wherein those metal couplings are that the mode of electroplating forms.
Described wafer test board wherein has a plurality of distributions in this printed circuit board (PCB), with those first electric connection points and those second electric connection point electric connections.
The wafer test support plate that the utility model proposes and wafer test board when the test metal coupling stains pollutant, only need be changed test carrier plate, therefore need not expend the cost of a large amount of clear pin times and use probe, and increase the speed of test disk; Simultaneously, in the wafer test support plate, dispose elastic film layer by the utility model, so can be by the elasticity of elastic film layer, make when the measuring head of wafer test board presses down, elastic film layer gives certain elastic space thus, so that each metal coupling all can contact with each test point, can not produce destructive compressing to the chip on the disk, also therefore can increase the yield of test; And the wafer test support plate can be replaced disparate modules according to disk or the chip of different size in the technology, makes board that different purposes be arranged; In addition, during with the contact of the test metal coupling contact chip of wafer test support plate, can avoid leaving a trace, make handicraft product more totally complete.
Description of drawings
Fig. 1 is the cutaway view of wafer test support plate of the present utility model;
Fig. 2 is the upward view of elastic film layer of the present utility model, and wherein A is elastic film layer, and B is the elastic film layer partial enlarged drawing;
Fig. 3 is the cutaway view of wafer test board of the present utility model;
Fig. 4 is the cutaway view of another embodiment of wafer test support plate of the present utility model;
Fig. 5 is the upward view of sheet metal of the present utility model, and wherein A is sheet metal, and B is the sheet metal partial enlarged drawing;
Fig. 6 is the cutaway view of another embodiment of wafer test board of the present utility model.
Primary clustering symbol description in the accompanying drawing:
1A, 1B wafer test support plate; 2A, 2B wafer test board; 10 printed circuit board (PCB)s, 101 upper surfaces; 103 lower surfaces; 105 distributions; 12 first electrically connect point; 14 second electrically connect point; 20 elastic film layer; 201 upper surfaces; 203 lower surfaces; 205 through holes; 22 metal materials; Weld pad on 221; 223 times weld pads; 225 metal couplings; 30 sheet metals; 301 upper surfaces; 303 lower surfaces; 305 pins; 32 tie points; 34 metal couplings; 35 pattern area; 40 probe bases; 401 upper surfaces; 403 lower surfaces; 42 probes; 421 probes upper end; 423 probe lower ends; 50 substrates; 501 upper surfaces; 503 lower surfaces; 52 distributions; 521 first ends; 523 second ends; 60 measuring heads; 62 bases; 70 disk placement racks; 80 disks to be measured; 801 chips.
Embodiment
In order to solve the problem of mentioning in the background technology, a main purpose of the present utility model is to provide a kind of wafer test support plate, a kind of replaceable wafer test support plate particularly, except the syringe needle that can replace present use probe directly and the weld pad on the chip contact and do not need to carry out at any time the action of pin clearly, can also be according to the testing requirement of different disks and and can replace the required corresponding wafer test support plate of test quickly and easily, so can increase the speed of wafer level test.
According to above-mentioned purpose, the utility model provides a kind of wafer test support plate, comprise: a printed circuit board (PCB), has a upper surface and with respect to a lower surface of upper surface, upper surface at printed circuit board (PCB) has a plurality of first electric connection points, lower surface at printed circuit board (PCB) has a plurality of second electric connection points, and its this a little first electric connection points a little second electrically connect some electric connection each other therewith; One elastic film layer has a upper surface and with respect to a lower surface of upper surface, has the through hole that a plurality of upper surfaces by elastic film layer are through to the lower surface of elastic film layer in elastic film layer; A plurality of metal materials are to insert this a little through holes, and these a little metal materials that are positioned at these a little through holes form a plurality of weld pads of going up in the upper surface of elastic film layer, form a plurality of weld pads down in the lower surface of elastic film layer; And a plurality of pins, having one first end and one second end, first end forms a tie point, and second end forms a metal coupling; Wherein, elastic film layer connects the lower surface of printed circuit board (PCB), and this a little second electrically connects point and go up weld pad therewith a bit and electrically connect, and these a little pins connect the lower surface of elastic film layer, and these weld pads a little tie points electric connections therewith down a bit.
According to above-mentioned purpose, the utility model provides a kind of wafer test support plate again, comprise: a printed circuit board (PCB), has a upper surface and with respect to a lower surface of upper surface, upper surface at printed circuit board (PCB) has a plurality of first electric connection points, lower surface at printed circuit board (PCB) has a plurality of second electric connection points, and its this a little first electric connection points a little second electrically connect some electric connection each other therewith; One elastic film layer has a upper surface and with respect to a lower surface of upper surface, has the through hole that a plurality of upper surfaces by elastic film layer are through to the lower surface of elastic film layer in elastic film layer; A plurality of metal materials are inserted this a little through holes, and these a little metal materials that are positioned at these a little through holes form a plurality of weld pads of going up in the upper surface of elastic film layer, form a plurality of weld pads down in the lower surface of elastic film layer; And a plurality of metal couplings, be formed on these a little weld pads down; Wherein, elastic film layer connects the lower surface of printed circuit board (PCB), and these a little second electric connection points are gone up the weld pad electric connection therewith a bit.
Another main purpose of the present utility model is to provide a kind of wafer test board, a kind of wafer test board that disposes replaceable wafer test support plate particularly, except the syringe needle that can replace present use probe directly and the weld pad on the chip contact and do not need to carry out at any time the action of pin clearly, can also be according to the testing requirement of different disks and and can replace the required corresponding wafer test support plate of test quickly and easily, so can increase the speed of wafer level test.
According to above-mentioned purpose, the utility model provides a kind of wafer test board, in order to a plurality of chips on the disk are tested, comprise: a probe base, has a upper surface and with respect to a lower surface of upper surface, have plurality of probes in probe base, these a little probes are to be through to lower surface by upper surface, and every probe forms probe upper end and a probe lower end; One substrate, has a upper surface and with respect to a lower surface of upper surface, the lower surface of substrate is connected in the upper surface of probe base, substrate has a plurality of distributions, every distribution forms one first end in the upper surface of substrate, lower surface in substrate forms one second end, and second end of these a little distributions is electrically connected at the probe upper end of these a little probes; One measuring head has a base, and base is connected in the upper surface of substrate, and electrically connects first end of these a little distributions; Wherein the wafer test board is characterised in that: a wafer test support plate, be connected in the lower surface of probe base, the wafer test support plate, comprise: a printed circuit board (PCB), has a upper surface and with respect to a lower surface of upper surface, upper surface at printed circuit board (PCB) has a plurality of first electric connection points, lower surface at printed circuit board (PCB) has a plurality of second electric connection points, its this a little first electric connection points a little second electrically connect some electric connection each other therewith, and these a little first electric connection points are electrically connected at this a little probes lower end; One elastic film layer has a upper surface and with respect to a lower surface of upper surface, has the through hole that a plurality of upper surfaces by elastic film layer are through to the lower surface of elastic film layer in elastic film layer; A plurality of metal materials are inserted this a little through holes, and these a little metal materials that are positioned at these a little through holes form a plurality of weld pads of going up in the upper surface of elastic film layer, form a plurality of weld pads down in the lower surface of elastic film layer; And a plurality of pins, having one first end and one second end, first end forms a tie point, and second end forms a metal coupling; Wherein, elastic film layer connects the lower surface of printed circuit board (PCB), and these a little second electric connection points are gone up weld pad therewith a bit and are electrically connected, and these a little pins connect the lower surface of elastic film layer, and this is weld pad a little tie points electric connections therewith down a bit, by the metal coupling on these a little pins these a little chips are tested.
According to above-mentioned purpose, the utility model provides a kind of wafer test board again, in order to a plurality of chips on the disk are tested, comprise: a probe base, has a upper surface and with respect to a lower surface of upper surface, have plurality of probes in probe base, these a little probes are through to lower surface by upper surface, and every probe forms probe upper end and a probe lower end; One substrate, has a upper surface and with respect to a lower surface of upper surface, the lower surface of substrate is connected in the upper surface of probe base, substrate has a plurality of distributions, every distribution forms one first end in the upper surface of substrate, lower surface in substrate forms one second end, and second end system of these a little distributions is electrically connected at the probe upper end of these a little probes; One measuring head has a base, and base is connected in the upper surface of substrate, and electrically connects first end of these a little distributions; Wherein the wafer test board is characterised in that: a wafer test support plate, be connected in the lower surface of probe base, the wafer test support plate, comprise: a printed circuit board (PCB), has a upper surface and with respect to a lower surface of upper surface, upper surface at printed circuit board (PCB) has a plurality of first electric connection points, lower surface at printed circuit board (PCB) has a plurality of second electric connection points, its this a little first electric connection points a little second electrically connect some electric connection each other therewith, and these a little first electric connection point systems are electrically connected at this a little probes lower end; One elastic film layer has a upper surface and with respect to a lower surface of upper surface, has the through hole that a plurality of upper surfaces by elastic film layer are through to the lower surface of elastic film layer in elastic film layer; A plurality of metal materials are inserted this a little through holes, and these a little metal materials that are positioned at these a little through holes form a plurality of weld pads of going up in the upper surface of elastic film layer, form a plurality of weld pads down in the lower surface of elastic film layer; And a plurality of metal couplings, be formed on these a little weld pads down; Wherein, elastic film layer connects the lower surface of printed circuit board (PCB), and this a little second electrically connects point and go up the weld pad electric connection therewith a bit, and by at these a little metal couplings these a little chips being tested.
For making the purpose of this utility model, technical characterictic and advantage, more the correlative technology field personnel understand and are implemented the utility model, illustrate technical characterictic of the present utility model and execution mode in this conjunction with figs. in follow-up specification, and enumerate preferred embodiment and further specify, right following examples explanation is not in order to limiting the utility model, and is to express the signal relevant with the utility model feature with the accompanying drawing that is hereinafter contrasted.
See also Fig. 1, be the cutaway view of wafer test support plate of the present utility model.As shown in Figure 1, wafer test support plate 1A comprises: a printed circuit board (PCB) 10 has a lower surface 103 that a upper surface 101 reaches with respect to upper surface 101; Upper surface 101 at printed circuit board (PCB) 10 has a plurality of first electric connection points 12, and has a plurality of second electric connection points 14 at the lower surface 103 of printed circuit board (PCB) 10; Wherein have a plurality of distributions 105 in the printed circuit board (PCB) 10, each bar distribution 105 is with each first electric connection point 12 and each the second electric connection point, 14 electric connection.
One elastic film layer 20 has a lower surface 203 that a upper surface 201 reaches with respect to upper surface 201, has the through hole 205 that a plurality of upper surfaces 201 by elastic film layer 20 are through to the lower surface 203 of elastic film layer 20 in elastic film layer 20; The material of elastic film layer 20 of the present utility model be the rubber-like macromolecular material (for example: polyimides; Polyimide, PI); And the mode that forms this through hole 205 can be the etching mode formation with semiconductor technology; Yet the utility model is not limited the generation type of through hole 205 and the material of elastic film layer 20.Then, a plurality of metal materials 22 are inserted in each through hole 205, and formed weld pad 221 in through hole 205 at the upper surface 201 of elastic film layer 20, the lower surface 203 in elastic film layer 20 forms weld pad 223 down simultaneously; The utility model is formed on mode in the through hole 205 with metal material 22, forms with physical vapour deposition (PVD) (PECVD) or the technology mode of electroplating (Plating).Afterwards, form metal coupling 225 (Metal Bump) on the weld pad 223 down in each again; Wherein, the upward view of elastic film layer of the present utility model, as shown in Figure 2.
Refer again to Fig. 1, wafer test support plate 1A of the present utility model is that the last weld pad 221 that will be positioned on elastic film layer 20 upper surfaces 201 is connected to the second electric connection point 14 of the lower surface 103 of printed circuit board (PCB) 10, and is positioned at metal coupling 225 electric connections on elastic film layer 20 lower surfaces 203.In addition, a plurality of second on printed circuit board (PCB) 10 lower surfaces 103 electrically connect point 14 and electrically connect 12 with a plurality of on upper surface 101 to first of both sides fan-out by a plurality of distributions 105 and be connected; Clearly, to electrically connect point 14 than second big for the spacing that has first of fan-out structure to electrically connect 12 of points; Afterwards, a plurality of first on printed circuit board (PCB) 10 upper surfaces 101 can be electrically connected probe base 40 electric connections of point 12 and one wafer test board 2A.
Because, wafer test support plate 1A of the present utility model can be according to the size of the weld pad spacing on the every chips on the disk to be measured, carry out the design of the size of corresponding metal coupling 225 spacings in elastic film layer 20, electrically connected the adjustment of the fan-out distance of point 12 again by the plural number first on printed circuit board (PCB) 10 upper surfaces 101; So the utility model can only need to change wafer test support plate 1A of the present utility model when testing different chips, and do not need to adjust again the part of probe base 40 and the probe 42 of wafer test board 2A, so can increase the speed of test disk.
Then, see also Fig. 3, be the cutaway view of wafer test board of the present utility model.As shown in Figure 3, wafer test board 2A comprises: a probe base 40, has a lower surface 403 that a upper surface 401 reaches with respect to upper surface 401, in probe base 40, has plurality of probes 42, each probe 42 is through to lower surface 403 by upper surface 401, and forms 421 and one probe lower end 423, probe upper end; One substrate 50 has a lower surface 503 that a upper surface 501 reaches with respect to upper surface 501, and the lower surface 503 of substrate 50 is connected in the upper surface 401 of probe base 40; Substrate 50 has a plurality of distributions 52, each distribution 52 forms one first end 521 in the upper surface 501 of substrate 50, lower surface 503 in substrate 50 forms one second end 523, and second end 523 of each distribution 50 is electrically connected at this probe upper end 421 of each probe 42; One measuring head 60 has a base 62, and base 62 is connected in the upper surface 501 of substrate 50, and electrically connects first end 521 of distribution 52; Wafer test support plate 1A is connected in the lower surface 403 of probe base 40; When wafer test support plate 1A of the present utility model was disposed at probe base 40, the probe lower end 423 of its each probe 42 can electrically connect with each first electric connection point 12; And mounting means the utility model of wafer test support plate 1A is not limited to.Below wafer test support plate 1A, have a disk placement rack 70, and place a disk 80 to be measured at disk placement rack 70, have a plurality of uncut chips 801 on the disk 80 to be measured; Wherein elastic film layer 20 can be equal size with disk 80 to be measured, and each metal coupling 225 on elastic film layer 20 is each test point (not being shown among the figure) on corresponding each chip 801; When wafer test board 2A operates, can be by measuring head 60 with wafer test support plate 1A to pressing down, and each metal coupling 225 and each weld pad on each chip 801 electrically connected, to measure each chip 801 on the full wafer disk.
Wafer test board 2A of the present utility model only need change wafer test support plate 1A of the present utility model, can test different chips, and do not need to adjust again the part of probe base 40 and the probe 42 of wafer test board 2A, so can increase the speed of test disk.
Moreover, when a plurality of metal coupling 225 that elastic film layer 20 forms, each metal coupling 225 may be not at grade, if when directly testing, may cause metal coupling 225 partly can't with chip on each weld pad electrically connect, produce the error rate of measuring; So wafer test support plate 1A of the present utility model can be by the elastic characteristic of elastic film layer 20, when testing, printed circuit board (PCB) 10 is pressed to elastic film layer 20, rubber-like characteristic by elastic film layer 20, a plurality of metal couplings 225 can be pressed to chip on each weld pad electrically connect, and can not produce destructive compressing to the chip on the disk, also therefore can increase the yield of test.
In addition, because the utility model is to replace probes with metal coupling 225 to come weld pad on the contact chip; Therefore can avoid staying the measurement vestige at chip, and then make chip more totally complete.
See also Fig. 4, be the cutaway view of another embodiment of wafer test support plate of the present utility model.As shown in Figure 4, wafer test support plate 1B comprises: a printed circuit board (PCB) 10 has a lower surface 103 that a upper surface 101 reaches with respect to upper surface 101; Upper surface 101 at printed circuit board (PCB) 10 has a plurality of first electric connection points 12, and has a plurality of second electric connection points 14 at the lower surface 103 of printed circuit board (PCB) 10; Wherein have a plurality of distributions 105 in the printed circuit board (PCB) 10, each bar distribution 105 is with each first electric connection point 12 and each the second electric connection point, 14 electric connection.
One elastic film layer 20 has a lower surface 203 that a upper surface 201 reaches with respect to upper surface 201, has the through hole 205 that a plurality of upper surfaces 201 by elastic film layer 20 are through to the lower surface 203 of elastic film layer 20 in elastic film layer 20; The material of elastic film layer 20 of the present utility model be the rubber-like macromolecular material (for example: polyimides; Polyimide, PI); And the mode that forms this through hole 205 can be the etching mode formation with semiconductor technology; Yet the utility model is not limited the generation type of through hole 205 and the material of elastic film layer 20.Then, a plurality of metal materials 22 are inserted in each through hole 205, and formed weld pad 221 in through hole 205 at the upper surface 201 of elastic film layer 20, the lower surface 203 in elastic film layer 20 forms weld pad 223 down simultaneously; The utility model is formed on mode in the through hole 205 with metal material 22, forms with physical vapour deposition (PVD) (PECVD) or the technology mode of electroplating (Plating).Clearly, the elastic film layer 20 in the present embodiment can be identical with Fig. 2, and difference between the two is not form metal coupling 225 on the following weld pad 223 of elastic film layer 20.
Refer again to Fig. 4 and Fig. 5, wherein Fig. 5 is the upward view of sheet metal of the present utility model.Sheet metal 30 has a lower surface 303 that a upper surface 301 reaches with respect to upper surface 301; Form the corresponding pattern area 35 of chip a plurality of and to be measured on the sheet metal 30, and in each pattern area 35, be formed with the corresponding pin 305 (as shown in Figure 5) of weld pad on the chip a plurality of and to be measured; And sheet metal 30 is formed the mode of plural pattern area 35 and pin 305, can use Sheet Metal Forming Technology (stamping process) mode to form.Then, have a plurality of tie points 32 at the upper surface 301 of sheet metal 30, and have a plurality of metal couplings 34 (Metal Bump) at the lower surface 303 of sheet metal 30, wherein, tie point 32 electrically connects with pin 305 each other mutually with metal coupling 34; Metal coupling 34 of the present utility model is with physical vapour deposition (PVD) (PECVD), electroplates (Plating) or the formation of routing technology mode, but the utility model is not limited the generation type of metal coupling 34.
Refer again to Fig. 4, wafer test support plate 1B of the present utility model be will be positioned at last weld pad 221 on elastic film layer 20 upper surfaces 201 be connected to printed circuit board (PCB) 10 lower surface 103 second electrically connect point 14, be electrically connected to a plurality of tie points 32 on the sheet metal 30 and be positioned at following weld pad 223 on elastic film layer 20 lower surfaces 203; Clearly, the spacing of a plurality of metal couplings 34 on the lower surface 303 of sheet metal 30 is minimum, and each metal coupling 34 is corresponding with a plurality of weld pads on each chip, so that when test, electrically connects with a plurality of metal couplings 34 and a plurality of weld pads on the chip; And a plurality of tie points 32 on sheet metal 30 upper surfaces 301 are to two ends fan-out (fan out), so the spacing between a plurality of tie points 32 on sheet metal 30 upper surfaces 301 is big than the spacing of a plurality of metal couplings 34 on the lower surface 303 of sheet metal 30 via pin 305.In addition, a plurality of second on printed circuit board (PCB) 10 lower surfaces 103 electrically connect point 14 and electrically connect 12 with a plurality of on upper surface 101 to first of both sides fan-out by a plurality of distributions 105 and be connected; Clearly, to electrically connect point 14 than second big for the spacing that has first of fan-out structure to electrically connect 12 of points; Afterwards, a plurality of first on printed circuit board (PCB) 10 upper surfaces 101 can be electrically connected probe base 40 electric connections of point 12 and one wafer test board 2B.
In addition,, the excess metal in each pattern area 35 need be removed with after elastic film layer 20 is connected at sheet metal 30, only stay pin 305, tie point 32 and metal coupling 34; Wherein, the mode that removes the excess metal in the pattern area 35 can use etching mode to finish.Because, wafer test support plate 1B of the present utility model can carry out the design of different metal projection 34 spacing sizes according to the size of the weld pad spacing on the every chips on the disk to be measured, electrically connect the adjustment of the fan-out distance of point 12 again by the plural number first on printed circuit board (PCB) 10 upper surfaces 101, so in the time of can testing different chips again, only need to change wafer test support plate 1B of the present utility model, and do not need to adjust again the part of probe base 40 and the probe 42 of wafer test board 2B, so can increase the speed of test disk.Moreover, during a plurality of metal coupling 34 on forming the lower surface 303 of sheet metal 30, each metal coupling 34 may be not at grade, if when directly testing, may cause metal coupling 34 partly can't with chip on each weld pad electrically connect, produce the error rate of measuring; So wafer test support plate 1B of the present utility model can be by the elastic characteristic of elastic film layer 20, when testing, printed circuit board (PCB) 10 is pressed to elastic film layer 20, by elastic film layer 20 a plurality of metal couplings 34 on the sheet metal 30 are pressed to chip on each weld pad electrically connect, therefore, can not produce destructive compressing to the chip on the disk, therefore can increase the yield of test yet.
In addition, because the utility model is to replace probes with metal coupling 34 to come weld pad on the contact chip; Therefore can avoid staying the measurement vestige at chip, and then make chip more totally complete.
Then, see also Fig. 6, be the cutaway view of wafer test board of the present utility model.As shown in Figure 6, wafer test board 2B comprises: a probe base 40, has a lower surface 403 that a upper surface 401 reaches with respect to upper surface 401, in probe base 40, has plurality of probes 42, each probe 42 is through to lower surface 403 by upper surface 401, and forms 421 and one probe lower end 423, probe upper end; One substrate 50 has a lower surface 503 that a upper surface 501 reaches with respect to upper surface 501, and the lower surface 503 of substrate 50 is connected in the upper surface 401 of probe base 40; Substrate 50 has a plurality of distributions 52, each distribution 52 forms one first end 521 in the upper surface 501 of substrate 50, lower surface 503 in substrate 50 forms one second end 523, and second end 523 of each distribution 50 is electrically connected at this probe upper end 421 of each probe 42; One measuring head 60 has a base 62, and base 62 is connected in the upper surface 501 of substrate 50, and electrically connects first end 521 of distribution 52; Wafer test support plate 1B is connected in the lower surface 403 of probe base 40; When wafer test support plate 1B of the present utility model was disposed at probe base 40, the probe lower end 423 of its each probe 42 can electrically connect with each first electric connection point 12; And mounting means the utility model of wafer test support plate 1B is not limited to.Below wafer test support plate 1B, have a disk placement rack 70, and place a disk 80 to be measured at disk placement rack 70, have a plurality of uncut chips 801 on the disk 80 to be measured; Wherein sheet metal 30 and disk 80 to be measured are equal size, and each test point (not being shown among the figure) on each metal coupling 34 corresponding each chip 801; When wafer test board 2B operates, can be by measuring head 60 with wafer test support plate 1B to pressing down, and each metal coupling 34 and each weld pad on each chip 801 electrically connected, to measure each chip 801 on the full wafer disk.
Wafer test board 2B of the present utility model only need change wafer test support plate 1B of the present utility model, can test different chips, and does not need to adjust the part of probe base 40 and the probe 42 of wafer test board 2B again, so can increase the speed of test disk.
Moreover, during a plurality of metal coupling 34 on forming the lower surface 303 of sheet metal 30, each metal coupling 34 may be not at grade, if when directly testing, may cause metal coupling 34 partly can't with chip 801 on each weld pad electrically connect, produce the error rate of measuring; So wafer test board 2B of the present utility model utilizes the wafer test support plate 1B that installs thereon, can be by the elastic characteristic of elastic film layer 20, when testing, printed circuit board (PCB) 10 is pressed to elastic film layer 20, by elastic film layer 20 a plurality of metal couplings 34 on the sheet metal 30 are pressed to chip 801 on each weld pad electrically connect, therefore, can not produce destructive compressing to the chip 801 on the disk 80 to be measured, therefore can increase the yield of test yet.
In addition, because the utility model is to replace probes with metal coupling 34 to come weld pad on the contact chip 801; Therefore can avoid staying the measurement vestige at chip 801, and then make chip 801 more totally complete.
Though the utility model is described as above with aforesaid preferred embodiment; so it is not in order to limit the utility model; those skilled in the art are not in breaking away from spirit and scope of the present utility model; when can doing a little change and retouching, therefore the protection range of the present utility model content that should be defined with the claim scope of application is as the criterion.
Claims (8)
1. a wafer test support plate is characterized in that, comprising:
One printed circuit board (PCB), has a upper surface and with respect to a lower surface of this upper surface, upper surface at this printed circuit board (PCB) has a plurality of first electric connection points, have a plurality of second at the lower surface of this printed circuit board (PCB) and electrically connect points, its those first electrically connect point and second electrically connect point and electrically connect each other with those;
One elastic film layer has a upper surface and with respect to a lower surface of this upper surface, has the through hole that a plurality of upper surfaces by this elastic film layer are through to the lower surface of this elastic film layer in this elastic film layer;
A plurality of metal materials are inserted those through holes, and those metal materials that are positioned at those through holes form a plurality of weld pads of going up in the upper surface of this elastic film layer, form a plurality of weld pads down in the lower surface of this elastic film layer; And
A plurality of pins have one first end and one second end, and this first end forms a tie point, and this second end forms a metal coupling; Wherein, this elastic film layer connects the lower surface of this printed circuit board (PCB), and those second electric connection points and weld pad electric connection on those, and those pins connect the lower surface of this elastic film layer, and those weld pad and electric connections of those tie points down.
2. wafer test support plate according to claim 1 is characterized in that, wherein has a plurality of distributions in this printed circuit board (PCB), with those first electric connection points and those second electric connection point electric connections.
3. wafer test board in order to a plurality of chips on the disk are tested, comprising:
One probe base has a upper surface and with respect to a lower surface of this upper surface, has plurality of probes in this probe base, and those probes are to be through to this lower surface by this upper surface, and whenever this probe forms probe upper end and a probe lower end;
One substrate, has a upper surface and with respect to a lower surface of this upper surface, the lower surface of this substrate is connected in the upper surface of this probe base, this substrate has a plurality of distributions, whenever this distribution forms one first end in the upper surface of this substrate, lower surface in this substrate forms one second end, and this of those distributions second end is electrically connected at this probe upper end of those probes;
One measuring head has a base, and this base is connected in the upper surface of this substrate, and electrically connects this first end of those distributions;
Wherein this wafer test board is characterised in that also and comprises:
One wafer test support plate is the lower surface that is connected in this probe base, and this wafer test support plate comprises:
One printed circuit board (PCB), has a upper surface and with respect to a lower surface of this upper surface, upper surface at this printed circuit board (PCB) has a plurality of first electric connection points, lower surface at this printed circuit board (PCB) has a plurality of second electric connection points, its those first electrically connect point and second electrically connect point and electrically connect each other with those, and those first electrically connect some system and are electrically connected at those probe lower ends;
One elastic film layer has a upper surface and with respect to a lower surface of this upper surface, has the through hole that a plurality of upper surfaces by this elastic film layer are through to the lower surface of this elastic film layer in this elastic film layer;
A plurality of metal materials are inserted those through holes, and those metal materials that are positioned at those through holes form a plurality of weld pads of going up in the upper surface of this elastic film layer, form a plurality of weld pads down in the lower surface of this elastic film layer; And
A plurality of pins have one first end and one second end, and this first end forms a tie point, and this second end forms a metal coupling;
Wherein, this elastic film layer connects the lower surface of this printed circuit board (PCB), and those second electric connection points and weld pad electric connection on those, and those pins connect the lower surface of this elastic film layer, and those are weld pad and the electric connection of those tie points down, by this metal coupling on those pins those chips is tested.
4. wafer test board according to claim 3 is characterized in that, wherein has a plurality of distributions in this printed circuit board (PCB), with those first electric connection points and those second electric connection point electric connections.
5. a wafer test support plate is characterized in that, comprising:
One printed circuit board (PCB), has a upper surface and with respect to a lower surface of this upper surface, upper surface at this printed circuit board (PCB) has a plurality of first electric connection points, have a plurality of second at the lower surface of this printed circuit board (PCB) and electrically connect points, its those first electrically connect point and second electrically connect point and electrically connect each other with those;
One elastic film layer has a upper surface and with respect to a lower surface of this upper surface, has the through hole that a plurality of upper surfaces by this elastic film layer are through to the lower surface of this elastic film layer in this elastic film layer;
A plurality of metal materials are inserted those through holes, and those metal materials that are positioned at those through holes form a plurality of weld pads of going up in the upper surface of this elastic film layer, form a plurality of weld pads down in the lower surface of this elastic film layer; And
A plurality of metal couplings are formed on those following weld pads;
Wherein, this elastic film layer connects the lower surface of this printed circuit board (PCB), and those second electric connection points and weld pad electric connection on those.
6. wafer test support plate according to claim 5 is characterized in that, wherein has a plurality of distributions in this printed circuit board (PCB), with those first electric connection points and those second electric connection point electric connections.
7. wafer test board in order to a plurality of chips on the disk are tested, comprising:
One probe base has a upper surface and with respect to a lower surface of this upper surface, has plurality of probes in this probe base, and those probes are through to this lower surface by this upper surface, and whenever this probe forms probe upper end and a probe lower end;
One substrate, has a upper surface and with respect to a lower surface of this upper surface, the lower surface of this substrate is connected in the upper surface of this probe base, this substrate has a plurality of distributions, whenever this distribution forms one first end in the upper surface of this substrate, lower surface in this substrate forms one second end, and this of those distributions second end is electrically connected at this probe upper end of those probes;
One measuring head has a base, and this base is connected in the upper surface of this substrate, and electrically connects this first end of those distributions;
Wherein this wafer test board is characterised in that also and comprises:
One wafer test support plate is connected in the lower surface of this probe base, and this wafer test support plate comprises:
One printed circuit board (PCB), has a upper surface and with respect to a lower surface of this upper surface, upper surface at this printed circuit board (PCB) has a plurality of first electric connection points, lower surface at this printed circuit board (PCB) has a plurality of second electric connection points, its those first electrically connect point and second electrically connect point and electrically connect each other with those, and those first electrically connect some system and are electrically connected at those probe lower ends;
One elastic film layer has a upper surface and with respect to a lower surface of this upper surface, has the through hole that a plurality of upper surfaces by this elastic film layer are through to the lower surface of this elastic film layer in this elastic film layer;
A plurality of metal materials are inserted those through holes, and those metal materials that are positioned at those through holes form a plurality of weld pads of going up in the upper surface of this elastic film layer, form a plurality of weld pads down in the lower surface of this elastic film layer; And
A plurality of metal couplings are formed on those following weld pads;
Wherein, this elastic film layer connects the lower surface of this printed circuit board (PCB), and those second electric connection points and weld pad electric connection on those, and by at those metal couplings those chips being tested.
8. wafer test board according to claim 7 is characterized in that, wherein has a plurality of distributions in this printed circuit board (PCB), with those first electric connection points and those second electric connection point electric connections.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220729498 CN203165869U (en) | 2012-12-24 | 2012-12-24 | Wafer testing loading board and wafer testing machine platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220729498 CN203165869U (en) | 2012-12-24 | 2012-12-24 | Wafer testing loading board and wafer testing machine platform |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203165869U true CN203165869U (en) | 2013-08-28 |
Family
ID=49027034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220729498 Expired - Fee Related CN203165869U (en) | 2012-12-24 | 2012-12-24 | Wafer testing loading board and wafer testing machine platform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203165869U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105572561A (en) * | 2015-12-10 | 2016-05-11 | 华测检测认证集团股份有限公司 | Universal type test device for failure analysis of chip |
| CN113945741A (en) * | 2020-07-15 | 2022-01-18 | 中华精测科技股份有限公司 | Probe card device and fence-shaped probe thereof |
-
2012
- 2012-12-24 CN CN 201220729498 patent/CN203165869U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105572561A (en) * | 2015-12-10 | 2016-05-11 | 华测检测认证集团股份有限公司 | Universal type test device for failure analysis of chip |
| CN113945741A (en) * | 2020-07-15 | 2022-01-18 | 中华精测科技股份有限公司 | Probe card device and fence-shaped probe thereof |
| CN113945741B (en) * | 2020-07-15 | 2023-11-10 | 台湾中华精测科技股份有限公司 | Probe card device and fence-shaped probe thereof |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130828 Termination date: 20151224 |
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| EXPY | Termination of patent right or utility model |