CN203133452U - Array substrate and liquid crystal display device - Google Patents
Array substrate and liquid crystal display device Download PDFInfo
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- CN203133452U CN203133452U CN201220472119.5U CN201220472119U CN203133452U CN 203133452 U CN203133452 U CN 203133452U CN 201220472119 U CN201220472119 U CN 201220472119U CN 203133452 U CN203133452 U CN 203133452U
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- array substrate
- electrode
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- insulating layer
- frame sealing
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- 239000000758 substrate Substances 0.000 title claims abstract description 143
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 32
- 238000007789 sealing Methods 0.000 claims abstract description 40
- 239000003292 glue Substances 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 20
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 3
- 239000010408 film Substances 0.000 description 33
- 239000012945 sealing adhesive Substances 0.000 description 24
- 238000000034 method Methods 0.000 description 16
- 239000000565 sealant Substances 0.000 description 10
- 239000010409 thin film Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000002087 whitening effect Effects 0.000 description 1
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Abstract
The utility model discloses an array substrate and a liquid crystal display device. The array substrate comprises a display area and a lead area, wherein a public electrode lead, an insulation layer and a connection electrode are arranged in the lead area, the insulation layer is located above the public electrode lead, and the connection electrode is located above the insulation layer; the display area comprises a film transistor which comprises a grid electrode, a source electrode, a drain electrode, semiconductor layers and a pixel electrode, wherein the semiconductor layers are located among the grid electrode, the source electrode and the drain electrode, and the pixel electrode is connected with the drain electrode; and the connection electrode comprises a hollow area, and the connection electrode is connected with the public electrode lead through a conductive via hole. According to the technical scheme, the problem that sealing glue connected with a driving circuit area on the array substrate is low in adhesive strength is resolved.
Description
Technical Field
The utility model relates to a liquid crystal display device field especially relates to an array substrate and liquid crystal display device.
Background
The liquid crystal display panel is a main component of the liquid crystal display and comprises an array substrate, a color film substrate, liquid crystal and frame sealing glue, wherein the array substrate and the color film substrate are arranged in a box-to-box mode, and the liquid crystal is filled between the array substrate and the color film substrate. The frame sealing glue used for bonding the array substrate and the color film substrate together is arranged at the peripheral edges of the array substrate and the color film substrate, and is used for sealing the filled liquid crystal, so that the liquid crystal is not contacted with the outside air and impurities, and the liquid crystal is prevented from leaking.
As shown in fig. 1, the sealant region 10 is located at the periphery of an effective display region 11 of the liquid crystal display panel, and on the array substrate, the sealant region 10 includes a connection driving circuit region (also referred to as a sealant region connected to a driving circuit) and a non-connection driving circuit region (also referred to as a sealant region not connected to a driving circuit). The influence of the adhesion strength of the frame sealing adhesive on the liquid crystal display panel is large, and when the adhesion strength of the frame sealing adhesive is low, the problems of the effective display area 11, such as whitening of the periphery, peripheral pollution, poor Gap property, etc., often occur.
The adhesive strength of the frame sealing glue depends on other two factors besides the characteristics of the frame sealing glue, on one hand, the contact area of the frame sealing glue with the surfaces of the array substrate and the color film substrate is the contact area, and the larger contact area is beneficial to improving the adhesive strength between the frame sealing glue and the array substrate and the color film substrate; on the other hand, the adhesive strength of the frame sealing adhesive has a great relationship with the roughness of the surfaces of the array substrate and the color film substrate and the surface materials of the array substrate and the color film substrate. The higher surface roughness is favorable for improving the adhesion strength between the frame sealing glue and the array substrate and the color film substrate, and generally, the surface adhesion of the silicon nitride material is superior to that of metal materials such as ITO and the like. For the first factor, in the manufacturing process of the liquid crystal display panel, the contact area between the sealant and the array substrate and the color film substrate is usually increased to improve the adhesion strength, but as the size of the liquid crystal display panel is limited, as shown in fig. 1, the wider sealant region 10 is very close to the effective display region 11 of the liquid crystal display panel, which may easily cause the peripheral pollution of the effective display region 11, resulting in poor correlation. For the second factor, the surface roughness of the array substrate and the color film substrate is usually increased by a method of arranging a protrusion on the array substrate and the color film substrate, specifically, a method is to arrange a protrusion on the color film substrate, the method can increase the contact area of the frame sealing adhesive and the color film substrate, but the protrusion is formed on the color film substrate through an organic material, so that not only are the process steps increased, but also the used materials are increased, and the manufacturing cost of the liquid crystal display panel is increased; another method is to arrange a protrusion on the array substrate, in which a protrusion structure is formed in the frame sealing adhesive region 10 through the TFT array forming process, which can also increase the contact area between the frame sealing adhesive and the array substrate, but the protrusion can only exist in the non-connected driving circuit region in the frame sealing adhesive region 10, and cannot improve the adhesion strength of the connected driving circuit region in the frame sealing adhesive region 10, and the end difference between the formed protrusion and the peripheral region is about 0.9 μm, when the conductive metal ball or support (such as glass fiber) in the frame sealing adhesive falls on the formed protrusion, the Gap property is also poor, so that the display abnormality occurs in the liquid crystal display panel.
At present, in the periphery of the effective display area 11, the frame sealing glue area 10 connected to the driving circuit area often has various defects due to the low adhesion strength between the frame sealing glue and the ITO conductive metal layer; as shown in fig. 1 and 2, the connection principle of the driving circuit is as follows: the ITO conductive metal layer 12 on the array substrate is conducted with the bottom common electrode layer 14 through the conductive via hole 13 in the frame sealing adhesive area on one hand, and is conducted with the common electrode layer on the color film substrate through the conductive metal ball in the frame sealing adhesive on the other hand, so that the purpose that the voltage of the common electrode layer 14 on the array substrate is the same as that of the common electrode layer on the color film substrate in the display process of the liquid crystal panel is achieved. However, since the adhesion strength of the sealant to the ITO conductive metal layer 12 is smaller than that of the passivation layer (SiNx)15, the adhesion strength of the sealant is often reduced on the surface of the ITO conductive metal layer 12, which may cause poor display performance around the driving circuit region connected to the sealant region 10, such as Side Gap.
SUMMERY OF THE UTILITY MODEL
In view of the above, the present invention provides an array substrate and a liquid crystal display device, which solve the problem of low adhesion strength of the frame sealing adhesive connected to the driving circuit area on the array substrate.
In order to achieve the above purpose, the technical scheme of the utility model is realized like this:
an array substrate comprises a display area and a lead area, wherein a common electrode lead and an insulating layer positioned above the common electrode lead are arranged in the lead area; the display area comprises a thin film transistor, the thin film transistor comprises a grid electrode, a source electrode, a drain electrode, a semiconductor layer and a pixel electrode, the semiconductor layer is positioned among the grid electrode, the source electrode and the drain electrode, the pixel electrode is connected with the drain electrode, and the connecting electrode is provided with a hollow area;
the connecting electrode is connected with the common electrode lead through a conducting through hole.
The array substrate is of a bottom gate structure, the insulating layer is a passivation layer, and the common electrode lead and the grid are on the same layer.
The array substrate is of a bottom gate structure, the insulating layer is a passivation layer, and the common electrode lead is in the same layer with the source electrode and the drain electrode.
The array substrate is of a top gate structure, the insulating layer is a gate insulating layer, and the common electrode lead is in the same layer with the source electrode and the drain electrode.
The figure of each hollow-out area is circular, or elliptical, or polygonal.
Wherein, the size value of each hollow-out area is as follows: the size of each hollow-out area needs to be smaller than the diameter of the conductive metal ball in the frame sealing glue.
Wherein the diameter of the conductive metal ball is 4-5 μm.
Wherein the connection electrode having the hollow area is the same as the pixel electrode in material.
A liquid crystal display device, comprising: a color film substrate, liquid crystal, frame sealing glue and the array substrate of any one of claims 1 to 7; wherein,
the array substrate and the color film substrate are arranged in a box-to-box mode;
the liquid crystal is filled between the array substrate and the color film substrate;
the frame sealing glue is arranged at the peripheral edges of the array substrate and the color film substrate and is used for bonding the array substrate and the color film substrate;
the frame sealing glue is connected with the insulating layer (passivation layer) through the hollow area of the connecting electrode.
The utility model provides an array substrate and liquid crystal display device, wherein array substrate includes display area and lead wire area, is equipped with the public electrode lead wire in the lead wire area, is located the insulating layer of public electrode lead wire top; the display area comprises a thin film transistor, the thin film transistor comprises a grid electrode, a source electrode, a drain electrode, a semiconductor layer and a pixel electrode, the semiconductor layer is positioned among the grid electrode, the source electrode and the drain electrode, the pixel electrode is connected with the drain electrode, and the connecting electrode is provided with a hollow area; the connecting electrode is connected with the common electrode lead through the conducting through hole, so that the roughness of the ITO conducting metal layer is improved, the frame sealing glue can be connected with the insulating layer, the connecting area between the frame sealing glue and the insulating layer is increased, the adhesion strength of the frame sealing glue connected with the driving circuit area on the array substrate is improved, and the problems of poor display and the like of the periphery connected with the driving circuit area are solved.
Drawings
Fig. 1 is a schematic plan view of an array substrate according to the present invention;
FIG. 2 is a schematic cross-sectional view of an array substrate in the prior art;
fig. 3 is a schematic plan view of the driving circuit region connected to the frame sealing adhesive region on the array substrate according to the present invention;
fig. 4 is a schematic cross-sectional view of an array substrate according to the present invention;
fig. 5 is a schematic cross-sectional view of another array substrate according to the present invention.
Description of reference numerals:
10: frame sealing adhesive region 11: display area
12: connection electrode 12 a: connecting the driving circuit region
13: the through via 14: common electrode lead formed in the same layer as the gate
14': common electrode lead formed in the same layer as the source/drain electrodes
15: passivation layer 15 a: insulating layer
16: transparent substrate 17: grid electrode
18: gate insulating layer 19: semiconductor layer
20: doped semiconductor layer 21 a: source electrode
21 b: drain 22: pixel electrode
23 passivation layer for manufacturing common electrode layer and source and drain electrodes at same layer
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The array substrate of the present invention includes a display region 11 and a lead region (including a connection driving circuit region 12a shown in fig. 1), wherein a common electrode lead (see reference numeral 14 of fig. 2, or reference numeral 14' of fig. 5), an insulating layer located above the common electrode lead, and a connection electrode 12 located above an insulating layer 15a (see passivation layer 15 of fig. 2, or passivation layer 15 of fig. 5) are disposed in the lead region, and the connection electrode 12 has a hollow region; the connection electrode 12 is connected to the common electrode lead through the via hole. The common electrode lead is positioned on the common electrode layer, and the connecting electrode is positioned on the ITO conducting metal layer. The display area comprises a thin film transistor, and the thin film transistor comprises a grid electrode, a source electrode, a drain electrode, a semiconductor layer positioned among the grid electrode, the source electrode and the drain electrode, and a pixel electrode connected with the drain electrode.
Here, the connection electrode of the present invention may also be referred to as an ITO conduction metal layer, and the common electrode lead may also be referred to as a common electrode layer, which is not described in detail below.
Referring to fig. 1, the figure is a schematic plan view of the array substrate of the present invention.
The embodiment of the utility model provides an array substrate specifically can include: a frame sealing glue area 10 and an effective display area 11; the frame sealing glue area 10 is located at the periphery of the effective display area 11, the frame sealing glue area 10 comprises a connection driving circuit area and a non-connection driving circuit area, the connection driving circuit area is a partial lead area of which the lead area is located in the frame sealing glue area 10, the frame sealing glue is coated on the connection electrode 12, the connection electrode 12 is provided with a netted hollow area, the hollow structure can be arranged on partial areas or all areas of one area, the hollow structure can be arranged on partial areas or all areas of two areas, and the hollow structure can be arranged on partial areas or all areas of three areas. The hollow-out area shown in fig. 3 may be a part or all of the connection electrode 12, that is, a part of the connection electrode 12 may have a hollow-out structure, or all of the connection electrode 12 may have a hollow-out structure.
Referring to fig. 3, it is a schematic plan view of the driving circuit region connected to the frame sealing adhesive region on the array substrate according to the present invention.
In the connection driving circuit area, the frame sealing glue is coated on the connection electrode 12, the connection electrode 12 has a mesh-shaped hollow area, and the frame sealing glue is connected with the insulating layer 15a through the mesh-shaped hollow area on the connection electrode 12.
Because the adhesion strength of the insulating layer 15a is higher than that of the ITO material, compared with the method in the prior art in which the frame sealing adhesive is only connected with the smooth ITO conducting metal layer 12, the roughness of the connecting electrode 12 is improved, and the frame sealing adhesive can be connected with the insulating layer 15a, so that the adhesion strength of the frame sealing adhesive connected with the driving circuit area on the array substrate can be improved.
The insulating layer 15a may be made of silicon nitride (SiNx), and since the silicon nitride has a better adhesion strength, the adhesion strength of the frame sealing adhesive connected to the driving circuit region on the array substrate may be further improved.
Referring to fig. 4, the figure is a schematic cross-sectional view of an array substrate according to the present invention.
The embodiment of the utility model provides an array substrate can be for the end gate structure, specifically includes: the display device comprises a transparent substrate 16, a grid electrode 17 formed on the transparent substrate 16, a grid insulating layer 18 covering the grid electrode 17, a semiconductor layer 19 positioned on the grid insulating layer 18, a source electrode 21a and a drain electrode 21b positioned on two sides of the semiconductor layer 19 and positioned on the grid insulating layer 18, a passivation layer 15 covering the source electrode 21a and the drain electrode 21b, and a pixel electrode layer 22 connected with the drain electrode 21b through a via hole of the passivation layer 15. The common electrode lead 14 and the gate electrode 17 may be formed in the same layer, that is, in the same layer. In the formation process of the pixel electrode layer 22, the connection electrode 12 having a mesh-like hollow area is simultaneously formed. When the array substrate and the color film substrate of the structure are paired, the frame sealing adhesive is connected with the passivation layer 15 through the hollow area of the connecting electrode 12.
The array substrate may further include a doped semiconductor layer 20 on the semiconductor layer 19.
Referring to fig. 5, the cross-sectional view of another array substrate in the present invention is shown.
The embodiment of the utility model provides an array substrate can be for the end gate structure, specifically includes: the display device comprises a transparent substrate 16, a grid electrode 17 formed on the transparent substrate 16, a grid insulating layer 18 covering the grid electrode 17, a semiconductor layer 19 positioned on the grid insulating layer 18, a source electrode 21a and a drain electrode 21b positioned on two sides of the semiconductor layer 19 and positioned on the grid insulating layer 18, a passivation layer 15 covering the source electrode 21a and the drain electrode 21b, and a pixel electrode layer 22 connected with the drain electrode 21b through a via hole of the passivation layer 15. The common electrode lead 14' and the source and drain electrodes 21a and 21b may be formed in the same layer, that is, in the same layer. In the formation process of the pixel electrode layer 22, the connection electrode 12 having a mesh-like hollow area is simultaneously formed. When the array substrate and the color film substrate of the structure are paired, the frame sealing adhesive is connected with the passivation layer 15 through the hollow area of the connecting electrode 12.
The array substrate may further include a doped semiconductor layer 20 on the semiconductor layer 19.
The embodiment of the utility model provides an array substrate still can be for the top grid structure, works as the embodiment of the utility model discloses when array substrate adopted the top grid structure, the grid was located grid insulating layer top. The common electrode lead, the source electrode and the drain electrode can be formed in the same layer. The connection electrode 12 having the hollow area and the pixel electrode 22 may be made of the same material, and the connection electrode 12 having the mesh-shaped hollow area is formed simultaneously during the formation of the pixel electrode 22. When the array substrate and the color film substrate of the structure are in box-pairing, the frame sealing glue is connected with the gate insulating layer through the hollow area of the connecting electrode 12. Therefore, the embodiment of the utility model provides an array substrate and various membrane substrate when to the box, the insulating layer 15a that the frame sealing glue passes through the fretwork regional connection can be passivation layer 15 (array substrate is the bottom gate structure), also can be the grid insulating layer (array substrate is the top gate structure, not shown in the figure).
The embodiment of the utility model provides an array substrate, every fretwork regional figure can be circular, or oval, or polygon. Among them, polygons may include, but are not limited to: rectangle, rhombus, triangle, pentagon, etc.
The size value of each hollowed-out area can be as follows: the size of each hollow-out area needs to be smaller than the diameter of the conductive metal ball in the frame sealing glue. The requirement for setting the hollow-out regions is only to satisfy the requirement that the conductive metal balls in the frame sealing glue do not leak from any one hollow-out region to the insulating layer 15 a.
The conductive metal balls may have a diameter of 4 to 5 μm.
When the hollow area adopts the standard setting, the conductive metal ball can be prevented from directly contacting the insulating layer 15A, so that the phenomenon that the common electrode leads 14 and 14' of the array substrate and the common electrode layer of the color film substrate cannot be conducted is avoided.
For example, when the hollow area is larger than 4 μm, the conductive metal ball may directly contact with the insulating layer, and the common electrode lead 14 of the array substrate and the common electrode layer of the color filter substrate cannot be conducted, so that the size of each hollow area needs to be smaller than the diameter of the conductive metal ball in the frame sealing adhesive.
Because the number of the conductive metal balls in the frame sealing glue is large, the density of the reticular hollow area is not strictly limited. Preferably, the area of the hollow area of the preferred embodiment is 30% of the area of the connecting electrode 12.
The utility model also provides a liquid crystal display device, this liquid crystal display device includes: a color film substrate, a liquid crystal, a sealant, and any of the aforementioned array substrates.
The array substrate and the color film substrate are arranged in a box-to-box mode; the liquid crystal is filled between the array substrate and the color film substrate; the frame sealing glue is arranged at the peripheral edges of the array substrate and the color film substrate and used for bonding the array substrate and the color film substrate. The frame sealing glue is connected with the insulating layer (passivation layer) through the hollow area of the connecting electrode.
In order to obtain the array substrate, a process for implementing the manufacturing method of the array substrate is described below by taking a bottom gate type array substrate as an example, and the method includes the following steps:
step 1, as shown in fig. 4, a gate metal thin film is deposited on a transparent substrate 16, and a gate electrode 17 and a common electrode lead (common electrode layer) 14 are formed on the transparent substrate 16 through photolithography and etching processes.
Step 2, as shown in fig. 4, successively depositing a gate insulating layer 18, a semiconductor layer (a-Si)19, a source electrode 21a, and a drain electrode 21b on the transparent substrate 16 formed in step 1, and then patterning the semiconductor layer 19 and the source and drain electrodes 21a and 21b on the gate electrode 17 by a half-step photolithography technique and an etching process, and forming a TFT channel pattern. Here, it should be noted that: the layers successively deposited on the transparent substrate 16 formed in step 1 may also include a doped semiconductor layer (n + Si) 20.
And 3, as shown in fig. 4, continuously depositing a passivation layer 15 made of the SiNx material on the transparent substrate 16 formed in the step 2, and forming a TFT via hole and a through via hole 13 in the frame sealing glue region through photoetching and etching processes.
Step 4, as shown in fig. 4, depositing an ITO thin film on the transparent substrate 16 formed in step 3, and then using a mask to block the ultraviolet light emitted by the exposure machine, and forming a pixel electrode 22 in the display region 11; meanwhile, a connection electrode 12 having a mesh-shaped hollow area is formed in the frame sealing adhesive area and connected to the driving circuit area.
Here, the requirement on the etching effect of the ITO film in the connection driving circuit region is not high, as long as the connection electrode 12 having a rough surface and a mesh-shaped hollow region can be formed, and the frame sealing adhesive can contact with the passivation layer 15 of the array substrate, so that the mesh-shaped hollow region of the connection electrode can have a wide design range.
By adopting the manufacturing method of the array substrate, on the basis of not increasing the using amount of the mask plates, the surface roughness of the connecting electrode 12 connected with the driving circuit area in the frame sealing glue area can be increased, and the frame sealing glue is contacted with the passivation layer 15, so that the adhesion strength of the frame sealing glue connected with the driving circuit area and the array substrate is increased, and the probability of bad occurrence is reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. An array substrate comprises a display area and a lead area, wherein a common electrode lead and an insulating layer positioned above the common electrode lead are arranged in the lead area; the display device comprises an insulating layer, a display area and a pixel electrode, wherein the insulating layer is arranged on the display area;
the connecting electrode is connected with the common electrode lead through a conducting through hole.
2. The array substrate of claim 1, wherein the array substrate is a bottom gate structure, the insulating layer is a passivation layer, and the common electrode lead is on the same layer as the gate.
3. The array substrate of claim 1, wherein the array substrate is a bottom gate structure, the insulating layer is a passivation layer, and the common electrode lead is on the same layer as the source electrode and the drain electrode.
4. The array substrate of claim 1, wherein the array substrate is a top gate structure, the insulating layer is a gate insulating layer, and the common electrode lead is on the same layer as the source and drain electrodes.
5. The array substrate of any one of claims 1 to 4, wherein the pattern of each hollowed-out area is circular, or elliptical, or polygonal.
6. The array substrate of any one of claims 1 to 4, wherein the size of each hollowed-out region is selected from the group consisting of: the size of each hollow-out area needs to be smaller than the diameter of the conductive metal ball in the frame sealing glue.
7. The array substrate of claim 6, wherein the conductive metal balls have a diameter of 4 μm to 5 μm.
8. The array substrate of claim 2, wherein the connection electrode having the hollowed-out region is made of the same material as the pixel electrode.
9. A liquid crystal display device, comprising: a color film substrate, liquid crystal, frame sealing glue and the array substrate of any one of claims 1 to 7; wherein,
the array substrate and the color film substrate are arranged in a box-to-box mode;
the liquid crystal is filled between the array substrate and the color film substrate;
the frame sealing glue is arranged at the peripheral edges of the array substrate and the color film substrate and is used for bonding the array substrate and the color film substrate;
the frame sealing glue is connected with the insulating layer through the hollow area of the connecting electrode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201220472119.5U CN203133452U (en) | 2012-09-14 | 2012-09-14 | Array substrate and liquid crystal display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201220472119.5U CN203133452U (en) | 2012-09-14 | 2012-09-14 | Array substrate and liquid crystal display device |
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| CN109613776B (en) * | 2019-01-16 | 2020-12-04 | 惠科股份有限公司 | Array substrate and display device |
| CN114594635A (en) * | 2022-04-01 | 2022-06-07 | Tcl华星光电技术有限公司 | Display device and display panel thereof |
| CN114594635B (en) * | 2022-04-01 | 2024-01-26 | Tcl华星光电技术有限公司 | Display device and display panel thereof |
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