CN203085515U - Semiconductor packaging body - Google Patents

Semiconductor packaging body Download PDF

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Publication number
CN203085515U
CN203085515U CN2013200050196U CN201320005019U CN203085515U CN 203085515 U CN203085515 U CN 203085515U CN 2013200050196 U CN2013200050196 U CN 2013200050196U CN 201320005019 U CN201320005019 U CN 201320005019U CN 203085515 U CN203085515 U CN 203085515U
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CN
China
Prior art keywords
bonding pad
chip bonding
lead
wire
package body
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Expired - Fee Related
Application number
CN2013200050196U
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Chinese (zh)
Inventor
严柱阳
郑润载
全五燮
孙焌瑞
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QUICK KOREA SEMICONDUCTOR CO Ltd
Fairchild Korea Semiconductor Ltd
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QUICK KOREA SEMICONDUCTOR CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A semiconductor packaging body includes a chip pad which comprises a conductive material and has a first thickness, semiconductor chips which are arranged the top surface of the chip pad and are electrically connected to the chip pad, lead wires which are connected with the chip pad and have a second thickness smaller than the first thickness, and a base layer which is arranged on the bottom surface of the chip pad and has a heat radiation surface.

Description

Semiconductor package body
The cross reference of related application
The application require on January 6th, 2012 to Korea S Department of Intellectual Property the priority in the Korean Utility Model Application 10-2012-0000158 that submits, its disclosure all is incorporated herein by reference.
Technical field
The utility model relates to a kind of semiconductor package body, and more specifically, relates to a kind of semiconductor package body that comprises chip bonding pad.
Background technology
Because electronic installation has high speed, big capacity and miniaturization characteristic recently, so there is the demand that increases in the structure and the manufacture method that can discharge the heat that is produced by semiconductor package body effectively.
Summary of the invention
The utility model provides a kind of high semiconductor package body of making the radiation efficiency of efficient and excellence that has.
According to one side of the present utility model, a kind of semiconductor package body is provided, comprising: chip bonding pad (diepaddle), described chip bonding pad comprises electric conducting material, and has first thickness; Semiconductor chip, described semiconductor chip is arranged on the top surface of described chip bonding pad, and is electrically connected to described chip bonding pad; Lead-in wire, described lead-in wire is connected to described chip bonding pad, and has second thickness less than described first thickness; And basalis, described basalis is arranged on the basal surface of described chip bonding pad, and has surface thermal radiation.
Described basalis can comprise the epoxy resin of high heat conduction.
Described semiconductor package body can also comprise containment member, and described containment member partly centers on described semiconductor chip, described chip bonding pad and described lead-in wire, and is used to make the lower surface of described basalis to expose.
Described basalis can form the part of molded components.
By using ultrasonic wave or laser welding between described lead-in wire and described chip bonding pad, to form the coupling part.
The twice that described first thickness can be described second thickness or three times.
Described first thickness can be in the scope between about 1 to about 2 millimeters.
Description of drawings
By detailed description, will more be expressly understood illustrative embodiments of the present utility model below in conjunction with accompanying drawing.
Fig. 1 is the perspective view according to the semiconductor package body of execution mode of the present utility model;
Fig. 2 is the cross-sectional view of the semiconductor package body of Fig. 1;
Fig. 3 A to 3D is the cross-sectional view of method that is used to describe the semiconductor package body of shop drawings 1;
Fig. 4 is the cross-sectional view according to the semiconductor package body of another execution mode of the present utility model; And
Fig. 5 is the cross-sectional view according to the semiconductor package body of another execution mode of the present utility model.
Embodiment
Now with reference to the accompanying drawing of the illustrative embodiments of the utility model shown in it, the utility model is described more fully.Yet, the utility model can be included in many multi-form in, and should not be interpreted as being limited in herein the execution mode of setting forth; More properly, provide these execution modes, make that the utility model content will be comprehensive and complete, and fully design of the present utility model is conveyed to those of ordinary skill in the art.
Equally, because for example manufacturing technology and/or deviation, expectation may take place and the departing from of shape shown.Therefore, execution mode of the present utility model should not be interpreted as limiting the concrete shape that the zone is shown herein, but for example comprises owing to make the error in shape that causes.In the drawings, identical Reference numeral is represented components identical.In addition, schematically show different elements and zone among the figure.Therefore, the utility model relative size of being not limited to illustrate in the drawings and at interval.In this article the term of Shi Yonging " and/or " comprise one or more relevant list the arbitrary of project and whole combinations.When being in before a series of elements such as statements such as " at least one ", the whole row of modified elements, and do not modify the discrete component of these row.
Fig. 1 is the perspective view according to the semiconductor package body 1000 of the utility model execution mode.Fig. 2 is the cross-sectional view along the semiconductor package body 1000 of the line II-II ' acquisition of Fig. 1.
Though Shuo Ming reason has been omitted the molded components (molding member) 180 that is used to protect internal structure in Fig. 1 for convenience, figure 2 illustrates molded components 180.
See figures.1.and.2, semiconductor package body 1000 comprises chip bonding pad 110, is arranged on basalis (base layer) 100 and a plurality of first semiconductor chip 160a to the, three semiconductor chip 160c under the chip bonding pad 110.Semiconductor package body 1000 also comprises first lead-in wire, 120, second lead-in wire 130, multiple conducting wires 170 (first lead is to privates 171,173,175 and 177) and molded components 180.
Chip bonding pad 110 is arranged on the top surface of basalis 100, and is attached to first lead-in wire 120 via coupling part 125.By using ultrasonic wave or laser to come the welding chip pad 110 and first lead-in wire 120 can form coupling part 125.Chip bonding pad 110 can comprise metal material.Chip bonding pad 110 can be formed by for example copper (Cu), and can be configured to comprise the multilayer of two or more metals.Chip bonding pad 110 has first thickness T 1, and first thickness T 1 can be in the scope between about 1 to 2 millimeter.First thickness T 1 is greater than first lead-in wire, 120 second thickness T 2, and for example first thickness T 1 is the twice of second thickness T 2 or three times.By using thicker relatively metal material to form chip bonding pad 110, can improve the radiation efficiency and the exothermal efficiency of chip bonding pad 110.
The first semiconductor chip 160a and the second semiconductor chip 160b are installed on the chip bonding pad 110 via adhesive phase 150.Adhesive phase 150 can be formed by metallicity epoxy resin or solder material.The size of semiconductor chip 160a and 160b and quantity are not limited to those sizes and the quantity shown in Fig. 1 and Fig. 2, and can make amendment by different way.
The 3rd semiconductor chip 160c can be installed on the sub-chip bonding pad 135 that separates with chip bonding pad 110, to reduce and to be suppressed at that issuable heat exchanges (cross-talking) between the 3rd semiconductor chip 160c and the first semiconductor chip 160a and the second semiconductor chip 160b.
Sub-chip bonding pad 135 can extend to form as one from second lead-in wire 130.Therefore, the 3rd thickness T 3 of sub-chip bonding pad 135 can be identical with the 4th thickness T 4 of second lead-in wire 130.And the 3rd thickness T 3 can be identical with second thickness T 2 of first lead-in wire 120.Perhaps, can use the separate substrate (separate substrate) with second lead-in wire, 130 separate control means to replace sub-chip bonding pad 135.
The first semiconductor chip 160a to the, three semiconductor chip 160c can be connected to each other, and/or are electrically connected to first lead-in wire, 120 and second lead-in wire 130 via lead 170.The first semiconductor chip 160a to the, three semiconductor chip 160c can comprise power device and/or control device.Power device goes for motor drive, power inverter, rectifier, power factor correction (PFC) or display drive apparatus.Yet scope of the present utility model is not limited thereto.Perhaps, the first semiconductor chip 160a to the, three semiconductor chip 160c can include source apparatus.For example, this active device can comprise and is selected from mos field effect transistor (MOSFET), igbt (IGBT) and diode, or the device of its combination.
First lead-in wire 120 can be connected to chip bonding pad 110, and can stretch out from molded components 180.Second lead-in wire 130 can stretch out from molded components 180.First lead-in wire, 120 and second lead-in wire 130 can be electrically connected to external circuit with the first semiconductor chip 160a to the, three semiconductor chip 160c, and can be provided by the lead frame (not shown).Though Fig. 1 and Fig. 2 illustrate 120 and one second lead-in wires 130 of one first lead-in wire, many first lead-in wires 120 and second lead-in wire 130 can be set.
Basalis 100 is arranged on the basal surface of chip bonding pad 110.Basalis 100 can comprise high-thermal-conductivity epoxy resin.By using epoxy resin to form basalis 100, basalis 100 can form than unfertile land relatively.Therefore, can implement thermal radiation effectively towards basalis 100 lower surfaces.Perhaps, basalis 100 can be formed by for example high-thermal-conductivity epoxy resin or ceramic material.High-thermal-conductivity epoxy resin or ceramic material can or apply by filling, sputter and form.
Basalis 100 can have the 5th thickness T 5 less than first thickness T 1 of chip bonding pad 110.The 5th thickness T 5 can be in the scope between about 200 to 700 microns, for example 500 microns.The lower surface of basalis 100 is exposed to outside the molded components 180 at least in part to be used as surface thermal radiation.In order to improve radiation efficiency, the radiator (not shown) can also join the lower surface of basalis 100 to.
According to the utility model, by the constant angle of bend and position and the relative thicker chip bonding pad 110 of formation that keeps first lead-in wire 120 and second lead-in wire 130, basalis 100 can form than unfertile land, the therefore whole radiation efficiency that has improved semiconductor package body 1000.
Lead 170 can be transferred to the first semiconductor chip 160a to the, three semiconductor chip 160c and first lead-in wire, 120 and second lead-in wire 130 with the signal of telecommunication via the contact point (not shown).
Molded components 180 partly seals the first semiconductor chip 160a to the, three semiconductor chip 160c, chip bonding pad 110, sub-chip bonding pad 135 and first lead-in wire, 120 and second lead-in wire 130.Molded components 180 can form the lower surface that makes basalis 100 and expose.Molded components 180 can be formed by for example EMC.
Fig. 3 A to 3D is the cross-sectional view of method that is used to describe the semiconductor package body 1000 of shop drawings 1.
With reference to Fig. 3 A, the first semiconductor chip 160a and the second semiconductor chip 160b are installed on the chip bonding pad 110 via adhesive phase 150.In this regard, chip bonding pad 110 can be independent metallic substrate.Chip bonding pad 110 can comprise metal material.Chip bonding pad 110 can be formed by for example Cu, maybe can be configured to comprise the multilayer of two or more metals.Chip bonding pad 110 can have the thickness in the scope between 1 to 2 millimeter greatly.Adhesive phase 150 can comprise electric conducting material, for example metallicity epoxy resin or solder material.
With reference to Fig. 3 B, first lead-in wire, 120 and second lead-in wire 130 is provided by the lead frame (not shown), and first lead-in wire 120 is attached to chip bonding pad 110.First lead-in wire 120 can be attached to chip bonding pad 110 by using ultrasonic wave or laser welding.Because first lead-in wire, 120 and second lead-in wire 130 has different-thickness with chip bonding pad 110, may need high manufacturing cost so form as the chip bonding pad 110 of one and the process of first lead-in wire 120.Yet, as described in the utility model, when first lead-in wire 120 is attached to chip bonding pad 110 by welding, can reduces manufacturing cost, and can improve the reliability of semiconductor package body 1000.
With reference to Fig. 3 C, the 3rd semiconductor chip 160c be installed to second the lead-in wire the 130 sub-chip bonding pads 135 that are connected on.Sub-chip bonding pad 135 can form the part of second lead-in wire 130, perhaps can be configured to be used for the separate substrate of control device.
Next, implement by using lead 170 (first lead is to privates 171,173,175 and 177) the first semiconductor chip 160a to the, three semiconductor chip 160c and first lead-in wire, 120 and second lead-in wire, the 130 wire bond methods that are electrically connected.
With reference to Fig. 3 D, enforcement is formed for the process with the molded components 180 of the first semiconductor chip 160a to the, three semiconductor chip 160c, chip bonding pad 110, sub-chip bonding pad 135 and the sealing of first lead-in wire, 120 and second lead-in wire, 130 parts.In this regard, molded components 180 is not formed on the lower surface of chip bonding pad 110, and sunk area R forms the lower surface that makes chip bonding pad 110 and exposes.
Next, see figures.1.and.2, implement to form the process of basalis 100.Basalis 100 can pass through to fill sunk area R with high-thermal-conductivity epoxy resin, and high-thermal-conductivity epoxy resin is solidified to form, and therefore finishes the manufacturing of the semiconductor package body 1000 shown in Fig. 1 and Fig. 2.
Fig. 4 is the cross-sectional view according to the semiconductor package body 2000 of another execution mode of the present utility model.
In Fig. 4, represent identical parts with Reference numeral identical among Fig. 1 and Fig. 2, therefore will omit its repeat specification.
With reference to Fig. 4, semiconductor package body 2000 comprises chip bonding pad 110, is formed on basalis 100a, the first semiconductor chip 160a to the, three semiconductor chip 160c under the chip bonding pad 110.Semiconductor package body 2000 also comprises first lead-in wire, 120, second lead-in wire 130, multiple conducting wires 170 and molded components 180.
Basalis 100a is arranged on the basal surface of chip bonding pad 110.Basalis 100a comprises the ground floor 101, the second layer 102 of sequence stack and the 3rd layer 103.Basalis 100a can (DBC) substrate or insulated metal substrate (IMS) form by for example directly covering copper (directbond copper).
When basalis 100a was formed by the DBC substrate, the second layer 102 can comprise ceramic insulating material, for example Al 2O 3, AlN, SiO 2Or BeO.Ground floor 101 and the 3rd layer 103 can comprise electric conducting material, for example Cu.
When basalis 100a was formed by IMS, ground floor 101 can comprise aluminium (Al) plate with excellent heat-radiating characteristic.The second layer 102 can comprise the epoxy resin with excellent heat resistance and electric insulation.Can comprise metal material for the 3rd layer 103 with excellent electric conductivity, for example, at least a in Cu, gold (Au), silver (Ag), Al and the nickel (Ni).
Basalis 100a can have the thickness between about 300 to 1200 microns, for example 500 microns.The lower surface of basalis 100a can be exposed to outside the molded components 180 at least in part to be used as surface thermal radiation.
Fig. 5 is the cross-sectional view according to the semiconductor package body 3000 of another execution mode of the present utility model.
In Fig. 5, represent identical parts with Reference numeral identical among Fig. 1 and Fig. 2, therefore will omit its repeat specification.
With reference to Fig. 5, semiconductor package body 3000 comprises chip bonding pad 110, is arranged on basalis 100b and the first semiconductor chip 160a to the, three semiconductor chip 160c under the chip bonding pad 110.Semiconductor package body 3000 also comprises first lead-in wire, 120, second lead-in wire 130, lead 170 and molded components 180a.
In the present embodiment, therefore basalis 100b forms the part of molded components 180a by forming with molded components 180a identical materials.
According to semiconductor package body of the present utility model, by forming thicker relatively chip bonding pad that forms by metal material and the basalis that the relative thin that is formed by high-thermal-conductivity epoxy resin is set, radiate heat effectively, and can realize the performance of semiconductor package body reliably.
According to semiconductor package body of the present utility model, chip bonding pad is attached to lead-in wire by welding, therefore can improve the manufacturing efficient and the reliability of semiconductor package body.
Though specifically illustrated and the utility model be described with reference to its illustrative embodiments, will understand, can carry out different variation of form and details therein and do not break away from the spirit and scope of claims.

Claims (7)

1. semiconductor package body comprises:
Chip bonding pad, described chip bonding pad comprises electric conducting material, and has first thickness;
Semiconductor chip, described semiconductor chip is arranged on the top surface of described chip bonding pad, and is electrically connected to described chip bonding pad;
Lead-in wire, described lead-in wire is connected to described chip bonding pad, and has second thickness less than described first thickness; And
Basalis, described basalis is arranged on the basal surface of described chip bonding pad, and has surface thermal radiation.
2. semiconductor package body according to claim 1, wherein, described basalis comprises the epoxy resin of high heat conduction.
3. semiconductor package body according to claim 1 also comprises containment member, and described containment member partly centers on described semiconductor chip, described chip bonding pad and described lead-in wire, and is used to make the lower surface of described basalis to expose.
4. semiconductor package body according to claim 3, wherein, described basalis forms the part of molded components.
5. semiconductor package body according to claim 1 wherein, forms the coupling part by using ultrasonic wave or laser welding between described lead-in wire and described chip bonding pad.
6. semiconductor package body according to claim 1, wherein, the twice that described first thickness is described second thickness or three times.
7. semiconductor package body according to claim 1, wherein, described first thickness is between about 1 millimeter to about 2 millimeters.
CN2013200050196U 2012-01-06 2013-01-05 Semiconductor packaging body Expired - Fee Related CN203085515U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2012-0000158 2012-01-06
KR2020120000158U KR200483254Y1 (en) 2012-01-06 2012-01-06 Semiconductor package

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018018952A (en) * 2016-07-28 2018-02-01 三菱電機株式会社 Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101994727B1 (en) * 2013-12-18 2019-07-01 삼성전기주식회사 Power module Package and Manufacturing Method for the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3256587B2 (en) * 1992-02-21 2002-02-12 株式会社東芝 High thermal conductive radiator and method of manufacturing the same
US5387554A (en) * 1992-09-10 1995-02-07 Vlsi Technology, Inc. Apparatus and method for thermally coupling a heat sink to a lead frame
KR200265087Y1 (en) * 1996-06-27 2002-08-16 주식회사 하이닉스반도체 Heat dissipation structure of semiconductor package
JP4037589B2 (en) 2000-03-07 2008-01-23 三菱電機株式会社 Resin-encapsulated power semiconductor device
JP3691790B2 (en) * 2001-12-27 2005-09-07 株式会社三井ハイテック Semiconductor device manufacturing method and semiconductor device manufactured by the method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018018952A (en) * 2016-07-28 2018-02-01 三菱電機株式会社 Semiconductor device
CN107665875A (en) * 2016-07-28 2018-02-06 三菱电机株式会社 Semiconductor device

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