CN202916787U - Chip with extra-low stand-by power consumption - Google Patents
Chip with extra-low stand-by power consumption Download PDFInfo
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- CN202916787U CN202916787U CN 201220596481 CN201220596481U CN202916787U CN 202916787 U CN202916787 U CN 202916787U CN 201220596481 CN201220596481 CN 201220596481 CN 201220596481 U CN201220596481 U CN 201220596481U CN 202916787 U CN202916787 U CN 202916787U
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Abstract
The utility model discloses a chip with extra-low stand-by power consumption. The chip comprises a stand-by normally-open area circuit, a digital center area circuit, a real-time clock circuit and an electric level conversion circuit. The real-time clock circuit uses a first power supply, and the digital center area circuit and the stand-by normally-open area circuit use a second power supply. The stand-by normally-open area circuit is used for processing wake-up requests in a stand-by mode, wakes up the chip and enables the chip to be in a work mode. The digital center area circuit is the core of the chip and works normally in the work mode. The real-time clock circuit finishes maintenance of a system clock, is used for generating continuous discontinuity and timing, and normally works in the stand-by mode. The chip enables a small-scale stand-by circuit to be obtained.
Description
Technical field
The utility model relates to a kind of microelectronics technology, specifically a kind of low-power dissipation SOC technology.By adopting above-mentioned framework, can obtain the very low SOC chip of stand-by power consumption.
Background technology
Fast development along with integrated circuit technique, with panel computer, smart mobile phone is that the electronic consumer products of representative is popularized fast, ultra-large SOC (system on a chip) (System on Chip based on deep-submicron, SoC) technology has become one of gordian technique that 21 century attracts most attention, and the user requires more and more higher to the properties of this series products.The complex task that many past must process at power PC (Personal Computer), such as Email, web page browsing, shooting take pictures, the application function such as media play can carry out at portable terminal.At present, high-performance SoC product emerges in an endless stream in market, and system's flying power is weak, heating is serious because this series products power consumption causes more greatly.Therefore how to reduce the entire system power consumption, prolong system and become the problem that whole SoC industry is needed solution badly service time.So require the integrated circuit (IC) design personnel when design SoC chip, the power consumption under the standby mode taken in as a main design objective.
For a typical cmos digital integrated circuit, power consumption mainly is divided into saltus step power consumption, short-circuit dissipation, electricity leakage power dissipation three parts.The saltus step power consumption discharges and recharges generation by the output capacitor of CMOS door, and short-circuit dissipation is produced by the transient state open-circuit current that causes during the signal conversion in the circuit, and electricity leakage power dissipation mainly is to be produced by factors such as electrostatic current, leakage currents.In a SoC System on Chip/SoC, dynamic power consumption is the main source of overall power.But along with the progress of technique, especially enter 65 nanometers after, the quiescent dissipation proportion will increase substantially.
Low-power Technology traditionally all is to start with from the dynamic power consumption that reduces system, by clock gating unit each module clock of system is controlled, when not needing this module work under certain application conditions, the clock of this module is closed, reduce the unnecessary redirect of circuit, reduced system's dynamic power consumption.Because under standby mode, most modules can not worked for a long time, by the power gating technology idle modular power source is turn-offed, reduce simultaneously the static system power consumption when reducing system's dynamic power consumption.The circuit that keeps small part is used for controlling the low energy consumption operation mode of whole chip, the low-power consumption request of process software makes system enter standby mode, simultaneously in the time of the needs system works, wake whole system up and enter mode of operation, this partial circuit is called power management unit.The characteristics of this technology are that power management unit and digital core district share a linear voltage stabilization source, when chip enters standby mode, close linear source of stable pressure to the power supply in digital core district, keep the power supply to power management unit, make power management unit be in normal mode of operation.Still working in linear voltage stabilization source under standby mode, itself has consumed very large power consumption.Very most of logic of power management unit is not in mode of operation simultaneously, but Power supply is arranged still yet, has consumed equally very most of power consumption.This low-power consumption framework can reduce the power consumption under the standby mode to a certain extent, but chip can not obtain extremely low stand-by power consumption.
The utility model content
Technical matters: the purpose of this utility model is the deficiency for existing low-power chip framework, proposes a kind of effectively, has the chip of utmost point low standby power loss.By adopting this chip, so that chip consumes few power consumption under standby mode, effective prolongs standby time.There are simultaneously two kinds of wake source available, when wake-up signal is arranged, waken system, again normal operation.
Technical scheme: for solving the problems of the technologies described above, the utility model provides a kind of chip with utmost point low standby power loss, and this chip comprises standby Chang Kai district circuit, digital core district circuit, real time clock circuit, level shifting circuit;
Real time clock circuit uses the first power supply, and the normal boot-strap circuit of digital core district circuit and standby uses second source;
Described standby Chang Kai district circuit is used for processing wake request in standby mode, wakes described chip up, makes it enter mode of operation;
Described digital core district circuit is the core of chip, this partial circuit normal operation in mode of operation;
The maintenance of described real time clock circuit completion system clock, for generation of interrupting continuously and carrying out timing, still work during this circuit standby mode;
Between real time clock circuit and digital core district circuit, be provided with the first level shifting circuit, between standby Chang Kai district's circuit and digital core district circuit, be provided with the second electrical level change-over circuit;
Described the first level shifting circuit is responsible for the signal level of different voltage domains is changed with the second electrical level change-over circuit, satisfies the requirement of voltage domain signal level.
Preferably, described standby Chang Kai district circuit comprises the standby mode state machine module, wake module, and the clock generating module, Chang Kai district reseting module is often opened and is used input/output module; Standby Chang Kai district circuit is not under any circumstance all cut off the power supply by the outer 3.3V Power supply of sheet; , each module all has a clock signal in the standby Chang Kai district circuit, so that this module normal operation;
Described standby mode state machine is used for receiving outside standby request signal, when receiving the signal that enters standby mode, mode of operation is switched to standby mode;
Described wake module is used for receiving wake-up signal, and when it had detected wake-up signal, chip returned to mode of operation;
Described clock generating module is used for providing the clock signal of all modules of standby Chang Kai district; Simultaneously when chip enters standby mode, use the clock of all modules except often opening the usefulness input/output module in the Clock Gating Technique turning off standby Chang Kai district;
Described Chang Kai district reseting module is used to chip that reset signal is provided, the resetting of completion system;
Described often opening with input/output module is used in standby mode making chip enter mode of operation for chip provides wake request.
Preferably, described digital core district circuit comprises core processor, storer, direct memory access module, intelligent card interface, UART Universal Asynchronous Receiver Transmitter module, universal serial bus, Ke Guan closed zone GIO, USB interface, digital core district power managed module, secure digital input-output card (SDIO) module, A/D converter, high performance bus, peripheral bus;
Core processor, storer, direct memory access module are connected on the high performance bus, intelligent card interface, UART Universal Asynchronous Receiver Transmitter module, universal serial bus, Ke Guan closed zone GIO, USB interface, digital core district power managed module, secure digital input-output card (SDIO) module, A/D converter are connected on the peripheral bus, and peripheral bus is connected on the high performance bus by bus interface again; When chip operation, core processor is accessed module in the digital core space by high performance bus;
Digital core district circuit is powered by 1 1.8V linear voltage stabilization source, and under standby mode, the Enable Pin in this 1.8V linear voltage stabilization source is cut off, and comprises that the digital core district circuit power of this source of stable pressure is all closed.
Preferably, described real time clock circuit is by the 3V powered battery; Under standby mode, provide the timing wake-up function simultaneously; Before entering standby mode, wakeup time is set, the current time is sent wake-up signal when arriving wakeup time, wakes whole system up by the wake module in the standby Chang Kai district, makes it withdraw from standby mode, enters mode of operation.
Beneficial effect: core concept of the present utility model is that standby Chang Kai district is divided out from digital core district sheet, and gives this partial circuit power supply by the sheet external power.Because digital core district power supply is no longer power supply under standby mode, therefore can directly the linear voltage stabilization source be closed, the digital core district no longer consumes any power consumption, thereby has obtained extremely low stand-by power consumption.In a chip that has designed, the stand-by power consumption that obtains is less than 2.6uA with this low-power consumption framework applications, the advantage of this utility model and remarkable result.
Description of drawings
Fig. 1 is SoC general frame structural drawing;
Fig. 2 is digital core district circuit frame structural drawing;
Fig. 3 is Chang Kai district stand-by circuit frame construction drawing;
Fig. 4 is standby mode state conversion synoptic diagram.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described further.
Core concept of the present utility model is that Chang Kai district stand-by circuit is divided out from digital core district sheet, and gives this partial circuit power supply by the sheet external power.Because digital core district power supply is no longer power supply under standby mode, therefore can directly the linear voltage stabilization source be closed, the digital core district no longer consumes any power consumption, thereby has obtained extremely low stand-by power consumption.In a chip that has designed, the stand-by power consumption that obtains can illustrate advantage and the remarkable result of this utility model less than 2.6uA with this low-power consumption framework applications.
The chip with utmost point low standby power loss that the utility model provides, this chip comprise standby Chang Kai district circuit, digital core district circuit, real time clock circuit, level shifting circuit;
Real time clock circuit uses the first power supply, and the normal boot-strap circuit of digital core district circuit and standby uses second source;
Described standby Chang Kai district circuit is used for processing wake request in standby mode, wakes described chip up, makes it enter mode of operation;
Described digital core district circuit is the core of chip, this partial circuit normal operation in mode of operation;
The maintenance of described real time clock circuit completion system clock, for generation of interrupting continuously and carrying out timing, still work during this circuit standby mode;
Between real time clock circuit and digital core district circuit, be provided with the first level shifting circuit, between standby Chang Kai district's circuit and digital core district circuit, be provided with the second electrical level change-over circuit;
Described the first level shifting circuit is responsible for the signal level of different voltage domains is changed with the second electrical level change-over circuit, satisfies the requirement of voltage domain signal level.
Described standby Chang Kai district circuit comprises the standby mode state machine module, wake module, and the clock generating module, Chang Kai district reseting module is often opened and is used input/output module; Standby Chang Kai district circuit is not under any circumstance all cut off the power supply by the outer 3.3V Power supply of sheet; , each module all has a clock signal in the standby Chang Kai district circuit, so that this module normal operation;
Described standby mode state machine is used for receiving outside standby request signal, when receiving the signal that enters standby mode, mode of operation is switched to standby mode;
Described wake module is used for receiving wake-up signal, and when it had detected wake-up signal, chip returned to mode of operation;
Described clock generating module is used for providing the clock signal of all modules of standby Chang Kai district; Simultaneously when chip enters standby mode, use the clock of all modules except often opening the usefulness input/output module in the Clock Gating Technique turning off standby Chang Kai district;
Described Chang Kai district reseting module is used to chip that reset signal is provided, the resetting of completion system;
Described often opening with input/output module is used in standby mode making chip enter mode of operation for chip provides wake request.
Described digital core district circuit comprises core processor, storer, direct memory access module, intelligent card interface, UART Universal Asynchronous Receiver Transmitter module, universal serial bus, Ke Guan closed zone GIO, USB interface, digital core district power managed module, secure digital input-output card (SDIO) module, A/D converter, high performance bus, peripheral bus;
Core processor, storer, direct memory access module are connected on the high performance bus, intelligent card interface, UART Universal Asynchronous Receiver Transmitter module, universal serial bus, Ke Guan closed zone GIO, USB interface, digital core district power managed module, secure digital input-output card (SDIO) module, A/D converter are connected on the peripheral bus, and peripheral bus is connected on the high performance bus by bus interface again; When chip operation, core processor is accessed module in the digital core space by high performance bus;
Digital core district circuit is powered by 1 1.8V linear voltage stabilization source, and under standby mode, the Enable Pin in this 1.8V linear voltage stabilization source is cut off, and comprises that the digital core district circuit power of this source of stable pressure is all closed.
Described real time clock circuit is by the 3V powered battery; Under standby mode, provide the timing wake-up function simultaneously; Before entering standby mode, wakeup time is set, the current time is sent wake-up signal when arriving wakeup time, wakes whole system up by the wake module in the standby Chang Kai district, makes it withdraw from standby mode, enters mode of operation.
This programme is for the larger problem of stand-by power consumption in the existing SoC chip low-power consumption framework, the proposition of creativity a kind of SoC chip architecture with utmost point low standby power loss.With reference to figure 1, the utility model is divided into standby Chang Kai district circuit with whole SoC chip, digital core district circuit, real time clock circuit, four modules of level shifting circuit.And first three module is respectively by the outer 3.3V power supply of sheet, 1.8V linear voltage stabilization source, 3V powered battery, and level shifting circuit is by 3.3V and 1.8V two-way Power supply.
Fig. 2 is digital core district circuit, this partial circuit is the core of whole chip, has comprised core processor, storer, intelligent card interface, UART Universal Asynchronous Receiver Transmitter, universal serial bus, direct memory access module, Ke Guan closed zone GIO, USB interface, SDIO module, A/D modular converter, digital core district power managed module, high performance bus, peripheral bus.Core processor, storer, direct memory access module are connected on the high performance bus, intelligent card interface, UART Universal Asynchronous Receiver Transmitter module, universal serial bus, Ke Guan closed zone GIO, USB interface, digital core district power managed module, secure digital input-output card (SDIO) module, A/D converter are connected on the peripheral bus, and peripheral bus is connected on the high performance bus by bus interface again.When chip operation, core processor is accessed module in the digital core space by high performance bus.
In mode of operation, digital core district power management unit cooperates the power managed function of finishing chip with Chang Kai district power management unit, so that system can use different Low-power Technology according to the difference of application scenarios, reaches the purpose that reduces power consumption.Digital core district circuit is powered by 1 1.8V linear voltage stabilization source, and under standby mode, the Enable Pin in this 1.8V linear voltage stabilization source is cut off, and comprises that the digital core district power supply of this source of stable pressure is all closed.Because closing of source of stable pressure, the circuit in digital core district will no longer consume any power consumption.
Fig. 3 is Chang Kai district stand-by circuit, processes wake request when this partial circuit mainly is responsible for standby mode, wakes whole chip up, makes it enter mode of operation; Comprise the standby mode state machine, wake module, the clock generating module, Chang Kai district reseting module is often opened the module with input and output GPIO.Chang Kai district stand-by circuit working method is as follows: when software decision-making system current task is handled, and Processing tasks no longer for a comparatively long period of time, just can the configuration software register, and so that system enters standby mode.
When Chang Kai district stand-by circuit obtained standby request that system sends, the standby mode state machine referring to Fig. 4, was processed this standby request according to the state flow process of setting.The first step utilizes Clock Gating Technique that the clock of each module in the digital core district is cut away, and these modules are no longer worked.Second step switches to the 32KHZ low-speed clock with the clock of Chang Kai district stand-by circuit by original 8MHZ high-frequency clock, reduces the dynamic power consumption of stand-by circuit.The 3rd step, the 8MHZ high speed crystal oscillator that sheet is outer was closed, and reduced the power consumption of this part circuit.Owing to can close digital core district power supply under the standby mode, close and cause the output signal of this partial circuit not stationary state to occur in the pass of power supply, so the 4th step added isolated location (isolation), with the output signal in digital core district with often open the isolation of stand-by circuit and real time clock circuit.The 5th step was the linear voltage stabilization source of closing in the digital core district, so that comprise the state that the digital core district circuit in this linear voltage stabilization source all is in does not have power supply, whole digital core district does not consume any power consumption under standby mode.The 6th step was by Chang Kai district reset circuit digital core space circuit to be resetted, so that its system when waking up is in reset mode, whole chip is owing to indeterminate state and cisco unity malfunction when avoiding system wake-up.The 7th step was by Chang Kai district clock generating module the 32KHZ clock to be carried out frequency division, producing the 4KHZ clock uses to Chang Kai district stand-by circuit, utilize simultaneously Clock gating with Chang Kai district stand-by circuit all circuit clocks except often opening the GPIO module, as much as possible reduce stand-by power consumption.
Wake module detects the wake-up signal wakes whole system, and enabled systems clock is then opened the linear voltage stabilization source in digital core district, whole chip resets, system enters normal mode of operation, has so just withdrawed from standby mode, and whole circuit returns to normal operating conditions.Wake-up signal wakes generation up by the level of real-time clock timing wake-up or Chang Kai district GPIO, and the technology of this respect is very ripe, can directly utilize.
When the real time clock circuit during Fig. 1 describes provides for system, minute, second, calendar, equal time information regularly, this partial circuit is by outside 3V powered battery.Under standby mode, provide the timing wake-up function simultaneously.Before entering standby mode, wakeup time is set, the current time is sent wake-up signal when arriving wakeup time, wakes whole system up by Chang Kai district wake module, makes it withdraw from standby mode, enters mode of operation.
Because Chang Kai district stand-by circuit, digital core district circuit, real time clock circuit are in different voltage domains, communication to each other needs level shifting circuit, therefore between each voltage domain, need to insert level shifting circuit, this technology is very ripe in SOC, can be applied to easily in this low-power consumption framework.
Such as Fig. 2 and Fig. 3, the utility model is divided into two parts with traditional chip power-consumption administrative unit, and a part is responsible for processing the power managed under the standby mode in standby Chang Kai district.A part is in the digital core district, and the low-power consumption of system is processed when being responsible for mode of operation.The very effective circuit scale that reduces the Chang Kai district of such division is so that system has less stand-by circuit.The power supply in simultaneously standby Chang Kai district does not need the linear voltage stabilization source, directly utilizes the power supply of sheet external power, can close the linear voltage stabilization source of chip fully like this under standby mode, obtains extremely low stand-by power consumption.
This practicality is divided into standby Chang Kai district circuit with whole SoC chip, digital core district circuit, real time clock circuit, four modules of level shifting circuit.And first three module is respectively by 1.8V linear voltage stabilization source, 3V powered battery in the outer 3.3V power supply of sheet, the sheet, and level shifting circuit is by 3.3V and 1.8V two-way Power supply.Build by such framework, obtained small stand-by circuit, thereby obtained extremely low stand-by power consumption.
The above only is preferred embodiments of the present utility model; protection domain of the present utility model is not limited with above-mentioned embodiment; as long as the equivalence that those of ordinary skills do according to the utility model institute disclosure is modified or changed, all should include in the protection domain of putting down in writing in claims.
Claims (4)
1. the chip with utmost point low standby power loss is characterized in that, this chip comprises standby Chang Kai district circuit, digital core district circuit, real time clock circuit, level shifting circuit;
Real time clock circuit uses the first power supply, and the normal boot-strap circuit of digital core district circuit and standby uses second source;
Described standby Chang Kai district circuit is used for processing wake request in standby mode, wakes described chip up, makes it enter mode of operation;
Described digital core district circuit is the core of chip, this partial circuit normal operation in mode of operation;
The maintenance of described real time clock circuit completion system clock, for generation of interrupting continuously and carrying out timing, still work during this circuit standby mode;
Between real time clock circuit and digital core district circuit, be provided with the first level shifting circuit, between standby Chang Kai district's circuit and digital core district circuit, be provided with the second electrical level change-over circuit;
Described the first level shifting circuit is responsible for the signal level of different voltage domains is changed with the second electrical level change-over circuit, satisfies the requirement of voltage domain signal level.
2. the chip with utmost point low standby power loss according to claim 1 is characterized in that, described standby Chang Kai district circuit comprises the standby mode state machine module, wake module, and the clock generating module, Chang Kai district reseting module is often opened and is used input/output module; Standby Chang Kai district circuit is not under any circumstance all cut off the power supply by the outer 3.3V Power supply of sheet; , each module all has a clock signal in the standby Chang Kai district circuit, so that this module normal operation;
Described standby mode state machine is used for receiving outside standby request signal, when receiving the signal that enters standby mode, mode of operation is switched to standby mode;
Described wake module is used for receiving wake-up signal, and when it had detected wake-up signal, chip returned to mode of operation;
Described clock generating module is used for providing the clock signal of all modules of standby Chang Kai district; Simultaneously when chip enters standby mode, use the clock of all modules except often opening the usefulness input/output module in the Clock Gating Technique turning off standby Chang Kai district;
Described Chang Kai district reseting module is used to chip that reset signal is provided, the resetting of completion system;
Described often opening with input/output module is used in standby mode making chip enter mode of operation for chip provides wake request.
3. the chip with utmost point low standby power loss according to claim 1, it is characterized in that described digital core district circuit comprises core processor, storer, direct memory access module, intelligent card interface, UART Universal Asynchronous Receiver Transmitter module, universal serial bus, Ke Guan closed zone GIO, USB interface, digital core district power managed module, secure digital input and output card module, A/D converter, high performance bus, peripheral bus;
Core processor, storer, direct memory access module are connected on the high performance bus, intelligent card interface, UART Universal Asynchronous Receiver Transmitter module, universal serial bus, Ke Guan closed zone GIO, USB interface, digital core district power managed module, secure digital input and output card module, A/D converter are connected on the peripheral bus, and peripheral bus is connected on the high performance bus by bus interface again; When chip operation, core processor is accessed module in the digital core space by high performance bus;
Digital core district circuit is powered by 1 1.8V linear voltage stabilization source, and under standby mode, the Enable Pin in this 1.8V linear voltage stabilization source is cut off, and comprises that the digital core district circuit power of this source of stable pressure is all closed.
4. the chip with utmost point low standby power loss according to claim 1 is characterized in that, described real time clock circuit is by the 3V powered battery; Under standby mode, provide the timing wake-up function simultaneously; Before entering standby mode, wakeup time is set, the current time is sent wake-up signal when arriving wakeup time, wakes whole system up by the wake module in the standby Chang Kai district, makes it withdraw from standby mode, enters mode of operation.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902350A (en) * | 2012-11-13 | 2013-01-30 | 江苏东大集成电路***工程技术有限公司 | Chip extra-low in standby power consumption |
| CN107678532A (en) * | 2017-10-20 | 2018-02-09 | 苏州国芯科技有限公司 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
| CN110265029A (en) * | 2019-06-21 | 2019-09-20 | 百度在线网络技术（北京）有限公司 | Speech chip and electronic equipment |
| CN110908430B (en) * | 2019-10-22 | 2021-01-08 | 珠海市杰理科技股份有限公司 | Controller, data processing method, computer device, and storage medium |
| IT202000009193A1 (en) * | 2020-04-28 | 2021-10-28 | Campagnolo Srl | BICYCLE COMPONENT EQUIPPED WITH ELECTRONIC DEVICE |
-
2012
- 2012-11-13 CN CN 201220596481 patent/CN202916787U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902350A (en) * | 2012-11-13 | 2013-01-30 | 江苏东大集成电路***工程技术有限公司 | Chip extra-low in standby power consumption |
| CN107678532A (en) * | 2017-10-20 | 2018-02-09 | 苏州国芯科技有限公司 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
| CN110265029A (en) * | 2019-06-21 | 2019-09-20 | 百度在线网络技术（北京）有限公司 | Speech chip and electronic equipment |
| CN110908430B (en) * | 2019-10-22 | 2021-01-08 | 珠海市杰理科技股份有限公司 | Controller, data processing method, computer device, and storage medium |
| IT202000009193A1 (en) * | 2020-04-28 | 2021-10-28 | Campagnolo Srl | BICYCLE COMPONENT EQUIPPED WITH ELECTRONIC DEVICE |
| EP3905004A1 (en) * | 2020-04-28 | 2021-11-03 | Campagnolo S.r.l. | Bicycle component provided with electronic device |
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Granted publication date: 20130501 Termination date: 20131113 |