CN202888176U

CN202888176U - ESD device structure based on BCD technology

Info

Publication number: CN202888176U
Application number: CN 201220245250
Authority: CN
Inventors: 陈宏冰; 陈忠志; 曾珂; 徐敏
Original assignee: SHANGHAI TENGYI SEMICONDUCTORS CO Ltd
Current assignee: SHANGHAI TENGYI SEMICONDUCTORS CO Ltd
Priority date: 2012-05-29
Filing date: 2012-05-29
Publication date: 2013-04-17
Anticipated expiration: 2022-05-29

Abstract

The utility model discloses an ESD device structure based on the BCD technology. The ESD device structure comprises an ESD NMOS unit. The ESD NMOS unit is provided with a P-type active injection zone and N-type active injection zones. A VSS end is connected onto the P-type active injection zone. Active pole ends or drain pole ends are connected onto the N-type active injection zones. The N-type active injection zones, at the drain pole ends, are connected through an N-type trap diffusion zone. One end of the N-type well diffusion zone is an access port of an input press welding point, and the other end of the N-type trap diffusion zone is a drain pole end of the ESD NMOS unit. Gates are disposed between source pole ends and the drain pole ends. Compared with the prior art, the ESD device structure is of a round structure and allows an N well to be adopted at the drain ends to restrict surface ESD current concentration caused by silicide (silicification), thereby effectively realizing ESD (electronic static discharge) power dissipation and enhancing current ESD (electronic static discharge) capabilities of a device. Meanwhile, an area utilization rate becomes higher, costs for manufacturing products are lowered, and purposes of the ESD device structure are achieved.

Description

ESD device architecture under a kind of BCD technique

Technical field

The utility model relates to a kind of device architecture, particularly a kind of GCNMOS ESD(grid coupling capacitance N-type metal-oxide semiconductor (MOS) based on BCD technique, static discharge) device architecture.

Background technology

Development along with integrated circuit, the ESD(static discharge) for the IC(integrated circuit) impact of chip is day by day serious, and particularly under BCD technique, most of techniques have added the silication injection technique, although greatly reduce device contacts resistance, also reduced the ESD device reliability simultaneously.How not increase the extra mask version on the basis; it is high to design a kind of area utilization; the ESD(static discharge) current capacity is strong; low-cost; can avoid again silication injection technique under the BCD technique to the ESD(static discharge) protection device construction of adverse effect, more and more become the problem that the designer need to consider.

The ESD(static discharge), extensively appear at the IC(integrated circuit) the processes such as manufacturing, encapsulation, transportation and use in, in application in the past, what numerous designers generally adopted is GGNMOS(grid coupling capacitance N-type metal-oxide semiconductor (MOS)) the ESD(static discharge of structure) device deals with common PIN(packaging pin) the ESD(static discharge of pin), drain to the distance of grid by increasing DGD() solve the drain terminal heating problem.

As shown in Figure 1; existing GCNMOS ESD(grid coupling capacitance N-type metal-oxide semiconductor (MOS); static discharge) device connects as follows: the source(source that is used as the NMOS pipe 10 of ESD) end is connected to gnd(ground) end 20; the gate(grid of NMOS pipe 10) end is connected to gnd(ground by gate resistance 11) end 20; the p-substrate(P substrate of NMOS pipe 10) end is given birth to resistance 12 by substrate and is connected to gnd(ground) drain(of end 20, NMOS pipe 10 leaks) be connected to the pad(that needs protection by defeated current-limiting resistance 13 and input pressure welding point) 30.

As shown in Figure 2, existing GGNMOS ESD(grid coupling capacitance N-type metal-oxide semiconductor (MOS) static discharge) device is opened and during work: when pad(input pressure welding point) on have the ESD(static discharge) during voltage, high potential so that the N+ drain region to the p-substrate(P substrate) PN junction produce reverse leakage, this reverse leakage fails to be convened for lack of a quorum at the p-substrate(P substrate) voltage of dead resistance generation, and this voltage can be loaded into according to connection the gate(grid of NMOS pipe) on the end, to its lower substrate p-substrate(P substrate) cause transoid.Parasitic NPN triode at this time, because base p-substrate(P substrate) current potential constantly rises, when the p-substrate(P substrate) to its emitter N+(NMOS source electrode) when current potential reaches positively biased, the parasitic NPN triode is opened, and keeps simultaneously the lower voltage of triode conducting to minimum value.

As shown in Figure 3, this current potential that makes parasitic triode emitter positively biased is exactly illustrated vt1, and this voltage is the flyback voltage first time.If the ESD(static discharge) overtension surpasses vt2, i.e. flyback voltage for the second time, then device can the failure puncture, as shown in Figure 4.

When for the first time flyback occurs, the ESDNPN structure ESD(static discharge of releasing) electric current, i.e. ESD(static discharge) device is in normal operating conditions.

Because BCD technique has generally adopted the silicide(silication now) Techniques For Reducing semiconductor surface resistivity, this is so that common NMOS(N type metal oxide semiconductor) as the ESD(static discharge) when protecting, the MOS(metal-oxide semiconductor (MOS)) device drain(leakage) steady resistance of end is less than normal, at the ESD(static discharge) when event occurs, electric current is concentrated easily and is caused device reliability to reduce, in order to address this problem, two kinds of common methods are arranged usually:

1, increases the drain terminal contact hole to the distance of polysilicon gate, can increase area like this, thereby increase cost;

2, increasing one deck silication trapping layer, not at the ESD(static discharge) drain terminal of device forms the silicon thing, so just can increase contact hole to the resistance of Si-gate, so that CURRENT DISTRIBUTION is even, the bleed off ability of raising electric current; Thereby shortcoming is to need to increase a photoetching process to have increased cost.

Therefore, need especially the ESD device architecture under a kind of BCD technique, solved the problem of above-mentioned existing existence.

The utility model content

The purpose of this utility model is to provide the ESD device architecture under a kind of BCD technique, for the defective that above-mentioned existing technology exists, has the manufacturing cost of reduction, improves ESD current drain ability and improves the withstand voltage design feature of ESD.

The technical problem that the utility model solves can realize by the following technical solutions:

ESD device architecture under a kind of BCD technique, it is characterized in that, it comprises ESD NMOS unit, be provided with the active injection region of P type and the active injection region of N-type on the described ESD NMOS unit, be connected with the VSS end on the active injection region of described P type, described N-type is connected with source terminal or drain electrode end on the active injection region, connect by N trap diffusion region between the active injection region of the N-type of described drain electrode end, one end of N trap diffusion region is the access interface of input pressure welding point, the other end of N trap diffusion region is the drain electrode end of ESDNMOS unit, is provided with gate terminal between described source terminal and the described drain electrode end.

In an embodiment of the present utility model, the length of described N trap diffusion region is 7.0-8.0um, and the length of active area that described N trap diffusion region covers the drain electrode end of NMOS is 0.4-0.8um, and described N trap diffusion region is positioned at that length is 0.6-1.0um under the field oxide.

Further, preferably, the length of described N trap diffusion region is 7.5um, and the length of active area that described N trap diffusion region covers the drain electrode end of NMOS is 0.55um, and described N trap diffusion region is positioned at that length is 0.8um under the field oxide.

In an embodiment of the present utility model, described ESD NMOS unit is rounded.

In an embodiment of the present utility model, inside, described ESD NMOS unit is provided with contact hole, and described contact hole is circular configuration.

ESD device architecture under the BCD technique of the present utility model compared with prior art has following features:

The first, at common GCNMOS(grid coupling capacitance N-type metal-oxide semiconductor (MOS)) on the architecture basics, used totally 9 layers of mask(light shield commonly used such as active area, N-type injection region, P type injection region, polysilicon layer, N trap diffusion region and contact hole etching layer), the not extra reticle that increases;

The second, remove the surperficial silicide(silication of drain terminal by changing device architecture), with the ESD(static discharge) electric current is driven on the darker N trap, thus make the power dissipation zone darker, and be unlikely to concentrate on device surface; On the other hand, introduce the N trap in the drain region, being equivalent to increases the collector electrode degree of depth of original parasitic NPN pipe, thereby has increased the electric current collection ability after the conducting of parasitic NPN pipe, greatly improves the ESD(static discharge) device reliability and ESD(static discharge) the current drain ability.

Three, be circular with device structure design, can be in the constant situation of area, increase MOSFET(metal-oxide semiconductor (MOS)) effective channel width, also increased the equivalent emitter area of parasitic ESD NPN pipe, guarantee that simultaneously all directions turn-on condition is consistent, the ESD(static discharge) device evenly triggers, and prevents that device portions from triggering the electric current that causes and concentrating, and improves area utilization and device performance.

ESD device architecture under the BCD technique of the present utility model, compared with prior art, adopt circular device architecture, introduce N trap restriction silicide(silication at drain terminal) the surperficial ESD electric current that causes concentrates, effectively carry out the ESD(static discharge) power dissipation, improved device ESD(static discharge) the current drain ability, higher area utilization has reduced cost of goods manufactured simultaneously, realizes the purpose of this utility model.

Characteristics of the present utility model can be consulted this case detailed description graphic and following better execution mode and be obtained to be well understood to.

Description of drawings

Fig. 1 is the circuit theory diagrams of existing GCNMOS ESD device;

Fig. 2 is the space of a whole page schematic diagram of existing GCNMOS ESD device;

Fig. 3 is the generalized section of existing GCNMOS ESD device;

Fig. 4 is the puncture flyback IV curve synoptic diagram of existing GCNMOS ESD device;

Fig. 5 is the space of a whole page schematic diagram of the ESD device architecture under the BCD technique of the present utility model;

Fig. 6 is the generalized section of the ESD device architecture under the BCD technique of the present utility model.

Embodiment

For technological means, creation characteristic that the utility model is realized, reach purpose and effect is easy to understand, below in conjunction with concrete diagram, further set forth the utility model.

As shown in Figure 5 and Figure 6, ESD device architecture under the BCD technique of the present utility model, it comprises ESD NMOS unit 100, be provided with the active injection region 200 of P type and the active injection region 300 of N-type on the described ESD NMOS unit 100, be connected with the VSS end on the active injection region 200 of described P type, described N-type is connected with source terminal S or drain electrode end D on the active injection region 300, connect by N trap diffusion region 400 between the active injection region 300 of the N-type of described drain electrode end D, one end of N trap diffusion region 400 is the access interface of input pressure welding point, the other end of N trap diffusion region 400 is the drain electrode end D of ESD NMOS unit, is provided with gate terminal Gate between described source terminal S and the described drain electrode end D.

In the utility model, the length of described N trap diffusion region 400 is 7.0-8.0um, and the length of active area that described N trap diffusion region 400 covers the drain electrode end of NMOS is 0.4-0.8um, and described N diffusion region 400 is positioned at that length is 0.6-1.0um under the field oxide.

Preferably, the length of described N trap diffusion region 400 is 7.5um, and the length of active area that described N trap diffusion region 400 covers the drain electrode end D of NMOS is 0.55um, and described N trap diffusion region 400 is positioned at that length is 0.8um under the field oxide.

In the utility model, described ESD NMOS unit 100 is rounded, and 100 inside, described ESD NMOS unit are provided with contact hole 110, and described contact hole 110 is circular configuration.

ESD device architecture under the BCD technique of the present utility model has adopted under the field oxide N trap without the characteristics of silicide, can utilize the N trap self-resistance ESD(static discharge that effectively dissipates) heat energy.Its collector electrode when the parasitic NPN pipe is opened becomes the Nwell(N trap by thin layer N+ simultaneously), be equivalent to increase the collector electrode area, the ESD(static discharge of more effectively releasing) electric current.

Circular configuration is made in described ESD NMOS unit 100, can make each NMOS(N type metal oxide semiconductor) environment of living in is roughly the same, unit can be opened simultaneously, thereby guaranteed whole ESD(static discharge) current capacity.

Calculate and to find by device size and the total channel width of device, on identical chip area, ESD device architecture under the BCD technique of the present utility model has higher devices use rate, utilize total device widths/total device area to obtain: the total device widths of circular device/total device area ≈ 0.11775, and the total device widths of square device commonly used/total device area ≈ 0.07143.Find out that thus circular device is more saved area under the identical device channel width.

More than show and described basic principle of the present utility model and principal character and advantage of the present utility model.The technical staff of the industry should understand; the utility model is not restricted to the described embodiments; that describes in above-described embodiment and the specification just illustrates principle of the present utility model; under the prerequisite that does not break away from the utility model spirit and scope; the utility model also has various changes and modifications; these changes and improvements all fall in claimed the utility model scope, and the claimed model of the utility model is defined by appending claims and equivalent thereof.

Claims

1. the ESD device architecture under the BCD technique, it is characterized in that, it comprises ESD NMOS unit, be provided with the active injection region of P type and the active injection region of N-type on the described ESD NMOS unit, be connected with the VSS end on the active injection region of described P type, described N-type is connected with source terminal or drain electrode end on the active injection region, connect by N trap diffusion region between the active injection region of the N-type of described drain electrode end, one end of N trap diffusion region is the access interface of input pressure welding point, the other end of N trap diffusion region is the drain electrode end of ESDNMOS unit, is provided with gate terminal between described source terminal and the described drain electrode end.

2. the ESD device architecture under the BCD technique as claimed in claim 1, it is characterized in that, the length of described N trap diffusion region is 7.0-8.0um, the length of active area that described N trap diffusion region covers the drain electrode end of NMOS is 0.4-0.8um, and described N trap diffusion region is positioned at that length is 0.6-1.0um under the field oxide.

3. the ESD device architecture under the BCD technique as claimed in claim 2, it is characterized in that preferably, the length of described N trap diffusion region is 7.5um, the length of active area that described N trap diffusion region covers the drain electrode end of NMOS is 0.55um, and described N trap diffusion region is positioned at that length is 0.8um under the field oxide.

4. the ESD device architecture under the BCD technique as claimed in claim 1 is characterized in that, described ESD NMOS unit is rounded.

5. the ESD device architecture under the BCD technique as claimed in claim 1 is characterized in that, inside, described ESD NMOS unit is provided with contact hole, and described contact hole is circular configuration.