CN202855255U - Switch matrix control circuit with three-wire serial connection peripheral interface - Google Patents
Switch matrix control circuit with three-wire serial connection peripheral interface Download PDFInfo
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Abstract
The utility model provides a switch matrix control circuit with a three-wire serial connection peripheral interface. The switch matrix control circuit comprises an upper control circuit, a shift register group and a PIN driver, wherein the shift register group comprises at least one shift resister. According to the switch matrix control circuit, the connection of each shift resister in the shift resister group with the upper control circuit only needs three control wires which are a data wire, a set wire and a clock wire, the number of the control wires is greatly reduced, and output port resource of the upper control circuit is reduced. At the same time, according to the switch matrix control circuit, a parallel data output end of each shift resister is connected with an input end of the PIN driver, which means that each shift resister directly outputs a control signal to the PIN driver, the adding of a control circuit such as a single chip microcomputer, an FPGA or the like is not needed, the design and test difficulties of the product are reduced, and for the product, the guarantee of the reliability of a device is facilitated.
Description
Technical Field
The application relates to the technical field of microwave matrix switch bus design, in particular to a switch matrix control circuit of a three-wire serial peripheral interface.
Background
The switch matrix is a device which combines and distributes the radio frequency signals input by a plurality of input devices and performs multi-output on the available radio frequency signals at the same time. A conventional switch matrix is driven by a PIN (positive-intrinsic semiconductor) driver, which is controlled by a TTL (transistor-transistor Logic level), and the number of channels of the PIN driver required by the switch matrix circuit determines the number of channels of the TTL. For different switch matrix circuits, different numbers of PIN drivers are required.
Currently, there are two more common switch matrix control methods, including: a parallel control mode and a control mode of an asynchronous serial interface RS (Recommended Standard) 232. Two switch matrix control methods will be described by taking control as an example.
The specific working principle of the parallel control mode is that the upper control circuit provides 72 TTL control lines which are respectively connected to 72 PIN drivers of the 12 x 6G switch matrix circuit, so that the 12 x 6G switch matrix circuit is directly controlled. However, this parallel control method requires too many control lines, so that it is inconvenient to assemble the upper control circuit using the parallel control method in a circuit with a high requirement on size, and the upper control circuit cannot provide a large number of control lines.
The specific working principle of the control mode of the asynchronous serial interface RS232 is that the switch matrix circuit is connected with the upper control circuit through the asynchronous serial interface RS 232. The upper control circuit and the asynchronous serial interface RS232 are only connected with three control lines of a receiving line, a transmitting line and a ground wire, and the number of the control lines is greatly reduced. However, the switch matrix circuit needs to analyze the RS232 serial port communication protocol, outputs a required 72-bit TTL control signal after the analysis is successful, and then connects the 72-bit control signal to the PIN driver to realize the control of the switch matrix. Therefore, the switch matrix circuit needs to be added with a single chip microcomputer or a control circuit such as a Field Programmable Gate Array (FPGA) to analyze the RS232 serial port communication protocol, and a software design part needs to be added, so that great technical difficulties are correspondingly increased for designing and testing products with high reliability requirements.
SUMMERY OF THE UTILITY MODEL
To the above problem, the present application provides a switch matrix control circuit of three-wire serial peripheral interface, too many control lines that need with the adoption parallel control mode among the solution prior art, be inconvenient for assemble in the higher circuit of size requirement, the problem that the host control circuit can not provide a large amount of control lines simultaneously, and adopt asynchronous serial interface RS 232's control mode to need to increase control circuits such as singlechip or FPGA to carry out the analysis to RS232 serial port communication protocol, and need to increase the software design part, design and test to the product that the reliability requirement is high, all the corresponding problem that has increased very big technical difficulty. The technical scheme is as follows:
the application provides a three-way serial peripheral interface's switch matrix control circuit, includes: the upper control circuit and the PIN driver which adds a thin layer of low-doped intrinsic semiconductor layer between the P and N semiconductor materials of the common diode also comprise:
the input end of the shift register group is connected with the sending port of the upper control circuit, and the output end of the shift register group is connected with the input end of the PIN driver; the transmitting ports of the upper control circuit comprise a serial data signal transmitting port, a clock signal transmitting port and a setting signal transmitting port; the shift register group comprises at least one shift register;
the input end of the shift register group comprises a serial data input end of each shift register, a shift register clock pulse input end of each shift register and a storage register clock pulse input end of each shift register; the output end of the shift register group comprises a serial data output end of each shift register and a parallel data output end of each shift register;
the clock pulse input end of each shift register is connected with the clock signal sending port through a clock line;
the clock pulse input end of the storage register of each shift register is connected with the set signal sending port through a set bit line;
the serial data input end of the first shift register in the shift register group is connected with the serial data signal sending port through a data line; the serial data input ends of other shift registers in the shift register group are connected with the serial data output end of the previous adjacent shift register;
and the parallel data output end of each shift register is connected with the input end of the PIN driver.
Preferably, the shift register comprises a model 54HC595 shift register.
Preferably, the PIN driver comprises a model number JLQ-22 driver.
Preferably, the PIN driver comprises 4 inputs and 4 outputs, wherein,
and 4 input ends of the PIN driver are respectively connected with 4 parallel data output ends of the shift register.
Preferably, the method further comprises the following steps:
the first transmitting circuit is connected with a serial data signal transmitting port of the upper control circuit;
the second transmitting circuit is connected with a clock signal transmitting port of the upper control circuit;
a third transmitting circuit connected to a set signal transmitting port of the upper control circuit;
the first receiving circuit is connected with the output end of the first transmitting circuit;
the second receiving circuit is connected with the output end of the second transmitting circuit;
the third receiving circuit is connected with the output end of the third transmitting circuit; wherein,
the output end of the first receiving circuit is connected with the serial data input end of a first shift register in the shift register group;
the output end of the second receiving circuit is connected with the clock pulse input end of each shift register in the shift register group;
the output end of the third receiving circuit is connected with the clock pulse input end of the storage register of each shift register in the shift register group;
the first transmitting circuit, the second transmitting circuit and the third transmitting circuit are three transmitting circuits with the same structure;
the first receiving circuit, the second receiving circuit and the third receiving circuit are three receiving circuits with the same structure.
By applying the technical scheme, the connection between each shift register in the shift register group in the switch matrix control circuit of the three-wire serial peripheral interface and the upper control circuit only needs three control wires, namely a data wire, a bit line and a clock wire, so that the number of the control wires is greatly reduced, and the output port resource of the upper control circuit is saved. Meanwhile, the parallel data output end of each shift register in the application is connected with the input end of the PIN driver, namely, each shift register directly outputs a control signal to the PIN driver, a single chip microcomputer or FPGA and other control circuits are not needed to be added, a software design part is not needed to be added, the design and test difficulty of a product is reduced, and the reliability of a device is convenient to guarantee for the product.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application;
fig. 2 is a schematic structural diagram of a shift register in a switch matrix control circuit of a three-wire serial peripheral interface according to the present application;
fig. 3 is another schematic structural diagram of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application;
fig. 4 is a schematic structural diagram of a PIN driver in a switch matrix control circuit of a three-wire serial peripheral interface according to the present application;
fig. 5 is a schematic structural diagram of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application;
fig. 6 is a schematic structural diagram of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application;
fig. 7 is a schematic signal transmission diagram of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application;
fig. 8 is a schematic structural diagram of a transmitting circuit of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application;
fig. 9 is a schematic structural diagram of a receiving circuit of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the present application, the number of shift registers in the shift register group may be set according to the number of paths of the PIN drivers required by the switch matrix circuit. In the following description of the embodiments, a detailed description of a switch matrix circuit requiring different PIN driver paths is given based on the main idea of the present application.
One embodiment
Referring to fig. 1, a schematic structural diagram of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application is shown, including: an upper control circuit 100, a shift register group 200, and a PIN driver 300.
The input end of the shift register group 200 is connected to the transmission port of the upper control circuit 100, and the output end is connected to the input end of the PIN driver 300.
The shift register group 200 includes at least one shift register 201. In this embodiment, the shift register 201 may be a model 54HC595 shift register.
Specifically, please refer to fig. 2, which shows a schematic structural diagram of a shift register in a switch matrix control circuit of a three-wire serial peripheral interface according to the present application. The shift register 201 includes 16-bit pins, pins 1 to 7, i.e., Q1 to Q7, pin 15, i.e., Q0, and Q0 to Q7, which are 8-bit parallel data output terminals of the shift register 201; pin 8, namely GND, is a port for connecting a ground wire; pin 9, Q' 7, is a serial data output that can be connected to pin 14 of the next adjacent shift register 201 to implement cascade connection with the next shift register 201.
It should be noted that the cascade connection between the shift registers 201 is to expand the input serial data to the conversion of the parallel data output of more than 8 bits. One shift register 201 comprises 8-bit parallel data output ends, and the cascade connection of a plurality of shift registers 201 comprises a plurality of 8-bit parallel data output ends, namely, the conversion of serial data expansion to more 8-bit parallel data output is realized.
The pin 11, i.e., SCK, is a clock input terminal of the shift register, and the shift register 201 performs sampling storage on input serial data when an input clock signal is at a rising edge.
It should be noted that the serial data is input according to the principle that the low bit enters first and the high bit enters last, and the data acquisition is to store the one-bit data of the current serial data when the input clock pulse signal is at the rising edge.
The pin 12, namely RCK, is a clock pulse input end of the storage register, and when the input set pulse signal is at a rising edge, all serial data stored in the current shift register 201 corresponds to the output end of the shift register 201, and is latched at the output end of the corresponding shift register 201.
The pin 14 or SER is a serial data input terminal of the shift register 201, and serial data input from the outside is received through the pin 14 or SER.
The transmission ports of the upper control circuit 100 include a serial data signal transmission port 101, a clock signal transmission port 102, and a set signal transmission port 103.
It should be noted that, in this embodiment, the number of the shift registers 201 in the shift register group 200 is determined by the number of lines of the PIN drivers required in the switch matrix circuit, and for the switch matrix circuit requiring one or two PIN drivers, one shift register group 201 in the shift register group 200 can be satisfactorily connected to the PIN drivers in the switch matrix circuit, please refer to fig. 3, which shows another structural schematic diagram of the switch matrix control circuit of the three-wire serial peripheral interface provided in this application, the shift register group 200 includes only one shift register 201, wherein,
the pin 11 of the shift register 201, i.e., the clock pulse input terminal of the SCK shift register, is connected to the clock signal transmission port 102 of the upper control circuit 100 via a clock line.
The RCK memory register clock pulse input terminal, which is the pin 12 of the shift register 201, is connected to the set signal transmission port 103 of the upper control circuit 100 via a set bit line.
The pin 14 of the shift register 201, i.e., the SER serial data input terminal, is connected to the serial data signal transmission port 101 of the upper control circuit 100 via a data line.
In particular, in this embodiment, PIN driver 300 may select a driver model JLQ-22 that includes 4 inputs and 4 outputs. Please refer to fig. 4, which illustrates a schematic structural diagram of a PIN driver in a switch matrix control circuit of a three-wire serial peripheral interface according to the present application. The PIN driver 300 comprises 14-bit PINs, and the PINs 1, 4, 6 and 7, namely OUT1 to OUT4, are 4 output terminals of the PIN driver 300; pins 2, 8 and 14, NC, are ports that do not need to be connected; pin 3, VCC, is a port for connection to an external supply voltage; pin 5, VEE, is the port to which the external negative voltage is connected.
IN the present embodiment, the 4 parallel data output terminals Q0 to Q3 IN the shift register 201 are sequentially selected IN sequence to be respectively connected to the 4 input terminals IN1 to IN4 of the PIN driver 300. Therefore, one shift register 201 can output 8 parallel data, that is, two PIN drivers 300 can be connected. In a switch matrix circuit requiring only one or two PIN drivers 300 to be connected, only one shift register 201 is included in the shift register group 200 to satisfy the requirement.
Of course, in the switch matrix circuit to which a plurality of PIN drivers 300 need to be connected, the corresponding shift register group 200 includes a plurality of shift registers 201, please refer to fig. 5 and fig. 6, where fig. 5 shows another schematic structural diagram of a switch matrix control circuit of a three-wire serial peripheral interface provided in the present application, which mainly describes a connection relationship of each shift register 201 in the shift register group 200. Fig. 6 shows a schematic diagram of another structure of a switch matrix control circuit of a three-wire serial peripheral interface provided in the present application, which mainly describes a connection relationship between the shift register 201 in the shift register group 200 and the PIN driver 300. In particular, the amount of the solvent to be used,
the SCK shift register clock pulse input terminal, which is the pin 11 of each shift register 201 in the shift register group 200, is connected to the clock signal transmission port 102 of the upper control circuit 100 via a clock line.
The RCK memory register clock pulse input terminal, which is the pin 12 of each shift register 201 in the shift register group 200, is connected to the set signal transmission port 103 of the upper control circuit 100 via a set bit line.
The pin 14 of the first shift register 201 in the shift register group 200, i.e., the SER serial data input end, is connected to the serial data signal transmission port 101 of the upper control circuit through a data line.
IN the 8-bit parallel data output terminal of the shift register 201 of the shift register group 200, i.e., the PIN 15Q 0, the PINs 1 to 7Q 1 to Q7, Q0 to Q3 are sequentially and correspondingly connected to the input terminals IN1 to IN4 of one PIN driver 300, and Q4 to Q7 are sequentially and correspondingly connected to the input terminals IN1 to IN4 of one PIN driver 300.
In the present embodiment, the transmission ports of the upper control circuit 100 include a serial data signal transmission port 101, a clock signal transmission port 102, and a set signal transmission port 103. Wherein,
the serial data signal transmission port 101 of the upper control circuit 100 is connected to the first shift register 201 in the shift register group 200 through a data line, and transmits a serial data signal to the shift register group 200. In particular, the serial data signal enters first at the low bits and last at the high bits.
The clock signal transmitting port 102 of the upper control circuit 100 is connected to the clock pulse input end of each shift register 201 in the shift register group 200 through a clock line, and transmits a clock pulse signal to the shift register group 200. Specifically, the clock pulse signal frequency is 1MHz, and when the clock pulse signal is at a rising edge, the shift register 201 in the shift register group 200 performs sampling on the input serial data, and stores the sampled data in the shift register 201. When the clock pulse signal is at the rising edge again, the input serial data is sampled again, and the sampled data is also stored in the shift register 201. The input serial data is sampled once every time the clock pulse signal is at a rising edge, and the sampled data is stored in the shift register 201.
In this embodiment, the shift registers 201 have 8-bit parallel data output ports, and each shift register 201 collects and stores data corresponding to one parallel data output port in the shift register 201. Specifically, the data collected and stored for the first time corresponds to the first parallel data output port of the shift register 201, i.e., the pin Q0, the data collected and stored for the second time will be shifted to the second parallel data output port of the shift register 201, i.e., the pin Q1, the data collected and stored for the second time corresponds to the first parallel data output port of the shift register 201, i.e., the pin Q0, the data collected and stored for the third time will be shifted to the third parallel data output port of the shift register 201, i.e., the pin Q2, the data collected and stored for the second time will be shifted to the second parallel data output port of the shift register 201, i.e., the pin Q1, and the data collected and stored for the third time corresponds to the first parallel data output port of the shift register 201, i.e., the pin Q0. In this form, each time data is collected and saved, the previously collected and saved data is shifted once.
One shift register 201 comprises 8-bit parallel data output ends, so that one shift register 201 can only collect and store data at most 8 times. When one shift register 201 has acquired and stored data for 8 times and the shift register 201 needs to acquire and store data again, at this time, one shift register 201 cannot meet the requirement, so that a plurality of shift registers 201 need to be cascaded to realize the purpose of acquiring and storing multi-bit data.
The set signal transmitting port 103 of the upper control circuit 100 is connected to the clock pulse input end of the storage register of each shift register 201 in the shift register group 200 through a set line, and transmits a set pulse signal to the shift register group 200. After the shift registers 201 in the shift register group 200 receive the set pulse signal sent by the upper control circuit 100, when the set pulse signal is at a rising edge, the data collected and stored in each shift register 201 in the shift register group 200 is latched and output corresponding to the parallel data output end of each shift register 201, and meanwhile, the data collected and stored before is emptied.
Please refer to fig. 7, which shows a signal transmission schematic diagram of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application. Each clock pulse signal corresponds to a bit in the serial data, and the set pulse signal is delayed from the last clock pulse signal in the clock pulse signals in one period. After all clock pulse signals are sent, a set pulse signal is sent to the shift registers 201, and the data collected and stored in the shift registers 201 are latched and output corresponding to the parallel data output end of each shift register 201.
By applying the technical scheme, the shift registers 201 in the shift register group 200 in the switch matrix control circuit of the three-wire serial peripheral interface provided by the application are connected with the upper control circuit 100 only by three control wires, namely a data wire, a bit line and a clock wire, so that the number of the control wires is greatly reduced, and the output port resources of the upper control circuit 100 are saved. Meanwhile, the parallel data output end of each shift register 201 in the application is connected with the input end of the PIN driver 300, namely, each shift register directly outputs a control signal to the PIN driver 300, a single chip microcomputer or FPGA and other control circuits are not required to be added, a software design part is not required to be added, the design and test difficulty of a product is reduced, and the reliability of a device is convenient to guarantee for the product.
Another embodiment
In this embodiment, a 12 × 6G switch matrix circuit is controlled as an example. In a 12 × 6G switch matrix circuit, a total of 12 × 6=72 PIN driving circuits are required for current driving. PIN driver 300 is a model JLQ-22 driver that includes 4 inputs, and thus a total of 72/4 to 18 PIN drivers 300 are required for a 12 x 6G switch matrix circuit.
The shift registers 201 are model 54HC595 shift registers, and each shift register 201 includes 8 parallel data output terminals, that is, each shift register 201 can provide 8 PIN driving circuits, so that 72/8-9 shift registers 201 are required in total for the 12 × 6G switch matrix circuit.
Specifically, please refer to fig. 5 and fig. 6, which include: shift register set 200 and PIN driver 300. The shift register group 200 includes 9 shift registers 201.
The SCK shift register clock pulse input terminal, which is the pin 11 of each shift register 201 in the shift register group 200, is connected to the clock signal transmission port 102 of the upper control circuit 100 via a clock line.
The RCK memory register clock pulse input terminal, which is the pin 12 of each shift register 201 in the shift register group 200, is connected to the set signal transmission port 103 of the upper control circuit 100 via a set bit line.
The pin 14 of the first shift register 201 in the shift register group 200, i.e., the SER serial data input end, is connected to the serial data signal transmission port 101 of the upper control circuit 100 through a data line.
The PIN 15 and the PIN 1 to 3 parallel data output terminals of each shift register 201 IN the shift register group 200 are sequentially and correspondingly connected with the PINs 9, 10, 12 and 13 of a PIN driver 300, namely 4 input terminals of IN1 to IN 4; PINs 4 to 7 of the parallel data output terminal of each shift register 201 IN the shift register group 200 are sequentially connected to PINs 9, 10, 12 and 13 of a PIN driver 300, i.e., 4 input terminals of IN1 to IN 4.
In this embodiment, the serial data signal transmitting port 101 of the upper control circuit 100 is connected to the first shift register 201 in the shift register group 200 through a data line, and transmits the serial data signal transmitted by the upper control circuit 100 to the first shift register 201 in the shift register group 200.
Each shift register 201 in the shift register group 200 is connected to the clock signal transmission port 102 of the upper control circuit 100 via a clock line, and constantly receives a clock pulse signal transmitted from the upper control circuit 100. The frequency of the clock pulse signal is 1MHz, and when the clock pulse signal is at a rising edge, the shift register 201 in the shift register group 200 performs data acquisition on input serial data, and stores the acquired data in the shift register 201. The shifting principle of the collected and stored data in each shift register 201 in the shift register group 200 and the corresponding relationship with the parallel data output end of each shift register 201 have been described in detail in the above embodiments, and are not described herein again.
In the present embodiment, a total of 72 parallel data outputs are required, so that data is distributed to the parallel data outputs of all 9 shift registers 201.
Each shift register 201 in the shift register group 200 is connected to the set signal transmission port 103 of the upper control circuit 100 via a set line, and constantly receives a set pulse signal transmitted from the upper control circuit 100. After each shift register 201 in the shift register group 200 receives the set pulse signal, when the set pulse signal is at a rising edge, the data collected and stored in each shift register 201 in the shift register group 200 is latched and output corresponding to the parallel data output end of each shift register 201, and meanwhile, the data collected and stored before is emptied.
At this time, each shift register 201 in the shift register group 200 transmits the parallel data signal to the connected PIN driver 300 through the parallel data output terminal, thereby implementing current driving on the 72-way PIN driving circuit.
Yet another embodiment
In the above embodiment, the upper control circuit 100 includes three transmission ports, and the serial data signal, the clock pulse signal, and the set pulse signal are transmitted to the shift register group 200 by connecting to the shift register group 200 through three control lines. In the present embodiment, three transmitting circuits with the same structure and three receiving circuits with the same structure are provided between the upper control circuit 100 and the shift register group 200, that is, three transmitting circuits with the same structure and three receiving circuits with the same structure are provided on three control lines between the upper control circuit 100 and the shift register group 200, so that it is not necessary to design different transmitting circuits and receiving circuits according to different signals transmitted by the upper control circuit 100, and the design is simple. The transmitting circuits and the receiving circuits are in one-to-one correspondence, an input end of each transmitting circuit is connected to one transmitting port of the upper control circuit 100, and an output end of each receiving circuit is connected to one input end of the shift register set 200.
In this embodiment, because the serial data signal, the clock pulse signal, and the set pulse signal sent by the upper control circuit 100 may have signal instability and the pulse voltage is too low or too high, when the shift register group 200 receives the serial data signal, the clock pulse signal, and the set pulse signal sent by the upper control circuit 100, the operation of the shift register 201 is unstable, so that the service life of the shift register 201 is reduced, and even the shift register 201 may be burned out. Therefore, in the present embodiment, a transmitting circuit and a receiving circuit are added to process signals to avoid burning out the shift register 201.
Referring to fig. 8 and 9, fig. 8 is a schematic diagram illustrating a structure of a transmitting end circuit of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application, and fig. 9 is a schematic diagram illustrating a structure of a receiving circuit of a switch matrix control circuit of a three-wire serial peripheral interface according to the present application. On the basis of the above embodiment, the method further includes: the first transmitting circuit, the second transmitting circuit, the third transmitting circuit, the first receiving circuit, the second receiving circuit, and the third receiving circuit. Wherein,
the first transmission circuit is connected to a serial data signal transmission port 101 of the upper control circuit 100, the second transmission circuit is connected to a clock signal transmission port 102 of the upper control circuit 100, and the third transmission circuit is connected to a set signal transmission port 103 of the upper control circuit 100.
The first receiving circuit is connected with the output end of the first transmitting circuit, the second receiving circuit is connected with the output end of the second transmitting circuit, and the third receiving circuit is connected with the output end of the third transmitting circuit.
The output end of the first receiving circuit is connected with the serial data input end of the first shift register 201 in the shift register group 200, the output end of the second receiving circuit is connected with the shift register clock pulse input end of each shift register 201 in the shift register group 200, and the output end of the third receiving circuit is connected with the storage register clock pulse input end of each shift register 201 in the shift register group 200.
Meanwhile, the first transmitting circuit, the second transmitting circuit and the third transmitting circuit are three transmitting circuits with the same structure, and the first receiving circuit, the second receiving circuit and the third receiving circuit are three receiving circuits with the same structure.
In this embodiment, the upper control circuit 100 sends a signal to the sending circuit, the signal is transmitted to the receiving circuit through the sending circuit, and finally the receiving circuit sends the signal to the shift register set 200.
By applying the above technical scheme, in the present application, three transmitting circuits with the same structure and three receiving circuits with the same structure are arranged between the upper control circuit 100 and the shift register group 200, and a serial data signal, a clock pulse signal and a set pulse signal transmitted in the upper control circuit 100 are firstly converted into another type of signal to be processed, and then are converted into a signal receivable by the shift register 201 to be transmitted, so that interference of a signal with too low or too high pulse voltage in the signal is overcome, and the shift register 201 is protected.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The switch matrix control circuit of the three-wire serial peripheral interface provided by the present application is introduced in detail, and a specific example is applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiment is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (5)
1. A switch matrix control circuit for a three-wire serial peripheral interface, comprising: the upper control circuit and the PIN driver which adds a thin layer of low-doped intrinsic semiconductor layer between the P and N semiconductor materials of the common diode are characterized by also comprising:
the input end of the shift register group is connected with the sending port of the upper control circuit, and the output end of the shift register group is connected with the input end of the PIN driver; the transmitting ports of the upper control circuit comprise a serial data signal transmitting port, a clock signal transmitting port and a setting signal transmitting port; the shift register group comprises at least one shift register;
the input end of the shift register group comprises a serial data input end of each shift register, a shift register clock pulse input end of each shift register and a storage register clock pulse input end of each shift register; the output end of the shift register group comprises a serial data output end of each shift register and a parallel data output end of each shift register;
the clock pulse input end of each shift register is connected with the clock signal sending port through a clock line;
the clock pulse input end of the storage register of each shift register is connected with the set signal sending port through a set bit line;
the serial data input end of the first shift register in the shift register group is connected with the serial data signal sending port through a data line; the serial data input ends of other shift registers in the shift register group are connected with the serial data output end of the previous adjacent shift register;
and the parallel data output end of each shift register is connected with the input end of the PIN driver.
2. The switch matrix control circuit of claim 1, wherein the shift register comprises a model 54HC595 shift register.
3. The switch matrix control circuit of claim 1, wherein the PIN driver comprises a model number JLQ-22 driver.
4. The switch matrix control circuit of claim 3, wherein the PIN driver includes 4 inputs and 4 outputs, wherein,
and 4 input ends of the PIN driver are respectively connected with 4 parallel data output ends of the shift register.
5. The switch matrix control circuit of claim 1, further comprising:
the first transmitting circuit is connected with a serial data signal transmitting port of the upper control circuit;
the second transmitting circuit is connected with a clock signal transmitting port of the upper control circuit;
a third transmitting circuit connected to a set signal transmitting port of the upper control circuit;
the first receiving circuit is connected with the output end of the first transmitting circuit;
the second receiving circuit is connected with the output end of the second transmitting circuit;
the third receiving circuit is connected with the output end of the third transmitting circuit; wherein,
the output end of the first receiving circuit is connected with the serial data input end of a first shift register in the shift register group;
the output end of the second receiving circuit is connected with the clock pulse input end of each shift register in the shift register group;
the output end of the third receiving circuit is connected with the clock pulse input end of the storage register of each shift register in the shift register group;
the first transmitting circuit, the second transmitting circuit and the third transmitting circuit are three transmitting circuits with the same structure;
the first receiving circuit, the second receiving circuit and the third receiving circuit are three receiving circuits with the same structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220496407 CN202855255U (en) | 2012-09-26 | 2012-09-26 | Switch matrix control circuit with three-wire serial connection peripheral interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220496407 CN202855255U (en) | 2012-09-26 | 2012-09-26 | Switch matrix control circuit with three-wire serial connection peripheral interface |
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| Publication Number | Publication Date |
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| CN202855255U true CN202855255U (en) | 2013-04-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220496407 Expired - Lifetime CN202855255U (en) | 2012-09-26 | 2012-09-26 | Switch matrix control circuit with three-wire serial connection peripheral interface |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103729326A (en) * | 2013-12-06 | 2014-04-16 | 南京智达康无线通信科技股份有限公司 | GPIO expansion method based on shifting registers |
| CN105510800A (en) * | 2015-12-01 | 2016-04-20 | 华大半导体有限公司 | Electronic label testing device and implementation method capable of simplifying PAD design |
| CN108646299A (en) * | 2018-03-30 | 2018-10-12 | 中国空间技术研究院 | A kind of satellite fabric interface load end Test Diode circuit |
| CN109062851A (en) * | 2018-08-22 | 2018-12-21 | 同源微（北京）半导体技术有限公司 | Control the Transmission system and method, subsystem, computer equipment and computer readable storage medium of data |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
-
2012
- 2012-09-26 CN CN 201220496407 patent/CN202855255U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103729326A (en) * | 2013-12-06 | 2014-04-16 | 南京智达康无线通信科技股份有限公司 | GPIO expansion method based on shifting registers |
| CN105510800A (en) * | 2015-12-01 | 2016-04-20 | 华大半导体有限公司 | Electronic label testing device and implementation method capable of simplifying PAD design |
| CN108646299A (en) * | 2018-03-30 | 2018-10-12 | 中国空间技术研究院 | A kind of satellite fabric interface load end Test Diode circuit |
| CN109062851A (en) * | 2018-08-22 | 2018-12-21 | 同源微（北京）半导体技术有限公司 | Control the Transmission system and method, subsystem, computer equipment and computer readable storage medium of data |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
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