CN202840486U - Phase loss and phase dislocation detecting circuit of three-phase power source - Google Patents
Phase loss and phase dislocation detecting circuit of three-phase power source Download PDFInfo
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- CN202840486U CN202840486U CN 201220444149 CN201220444149U CN202840486U CN 202840486 U CN202840486 U CN 202840486U CN 201220444149 CN201220444149 CN 201220444149 CN 201220444149 U CN201220444149 U CN 201220444149U CN 202840486 U CN202840486 U CN 202840486U
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Abstract
The utility model relates to the technical field of voltage stabilization and voltage regulation of a three-phase power source and especially relates to a phase loss and phase dislocation detecting circuit of the three-phase power source. The phase loss and phase dislocation detecting circuit of the three-phase power source includes a signal converting circuit 100, a signal collecting circuit 200 and a signal processing and driving circuit 300. An output terminal of the signal converting circuit is connected with an input terminal of the signal collecting circuit 200. An output terminal of the signal collecting circuit is connected with an input terminal of the signal processing and driving circuit 300. Compared with the prior art, the signal converting circuit 100 of the phase loss and phase dislocation detecting circuit of the three-phase power source converts the three-phase power source to signals suitable for being collected by the signal collecting circuit 200. The signal collecting circuit 200 collects the signals and sends to the signal processing and driving circuit 300. If the signal processing and driving circuit 300 receives phase dislocation signals or phase loss signals, the signals processing and driving circuit 300 sends protection signals, so that the occurrence of faults is avoided. The phase loss and phase dislocation detecting circuit of the three-phase power source provided by the utility model has characteristics that the phase loss and phase dislocation detecting circuit of the three-phase power source is simple in circuit structure, easy to realize, good in stability and high in anti-interference capability.
Description
Technical field
The utility model relates to the voltage regulation of voltage regulation technical field of three phase mains, particularly relates to a kind of phase shortage and misphase testing circuit of three phase mains.
Background technology
Arranged in the three phase mains dividing of A phase, B phase and C phase.If according to the phase sequence circuit access motor of A, B, C, motor forward; And according to A, C, B phase sequence access motor, motor reverses exactly.The normal operation of the phase ordered pair power consumption equipment of three-phase alternating current has great significance, and does not allow to occur anti-phase in a lot of situations.Normally in service, in case phase sequence is anti-phase, rotation direction also will change, and this essential phase sequence of introducing in the control of phoresying equipment is detected, otherwise will cause equipment fault, even personal injury.The circuit that prior art also exists phase sequence to detect, but have the demand that circuit of testing the phase sequence poor stability, antijamming capability are strong, be difficult to satisfy modern industry and life now.
Therefore, need badly a kind of good stability of avoiding weak point of the prior art, antijamming capability strong, need not high withstand voltage phase shortage and misphase testing circuit.
The utility model content
The purpose of this utility model is to avoid weak point of the prior art and phase shortage and the misphase testing circuit that a kind of simple in structure, good stability, antijamming capability are strong, need not high withstand voltage three phase mains is provided.
The purpose of this utility model is achieved through the following technical solutions.
A kind of misphase of three phase mains and open-phase protection circuit; comprise signaling conversion circuit 100, signal acquisition circuit 200 and signal processing and drive circuit 300; the output of signaling conversion circuit 100 is connected with the input of signal acquisition circuit 200; the output of signal acquisition circuit 200 and signal are processed and the input of drive circuit 300 is connected, and signal processing and drive circuit 300 receive that misphase or default phase signal then send guard signal.
Wherein, signaling conversion circuit 100 comprises resistance R 1, resistance R 2, resistance R 11, resistance R 12, resistance R 19, resistance R 20, resistance R 21, resistance R 22, resistance R 23, resistance R 25, resistance R 26, resistance R 27, resistance R 29, resistance R 30, resistance R 6, voltage transformer T1, voltage transformer T2, voltage transformer T3, capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10 and capacitor C 13;
Signal acquisition circuit 200 comprises resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 18, capacitor C 2, capacitor C 3, capacitor C 6, capacitor C 8, capacitor C 9, capacitor C 11, capacitor C 12, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, capacitor C 19, chip U2 and crystal oscillator Y1; Signal is processed and drive circuit 300 comprises resistance R 28, exclusion R10, chip U1, light-emitting diode D1, light-emitting diode D2, light-emitting diode D3, diode D4, triode Q1 and relay K 1;
The first pin P101 of binding post P1 is connected with an end of resistance R 22, an end of resistance R 25, and the other end of resistance R 22 is connected with the first input end T201 of voltage transformer T2, and the other end of resistance R 25 is connected with the first input end T301 of voltage transformer T3;
One end of the crus secunda P102 of binding post P1 and an end of resistance R 11, resistance R 19, the first input end T101 of the other end of resistance R 11 and voltage transformer T1, the other end of resistance R 19 is connected with the second input T202 of voltage transformer T2;
One end of the tripod P103 of binding post P1 and an end of resistance R 1, resistance R 29, the second input T102 of the other end of resistance R 1 and voltage transformer T1, the other end of resistance R 29 is connected with the second input T302 of voltage transformer T3;
The first output T103 of voltage transformer T1 is connected with an end of resistance R 6, an end of resistance R 2, and the second output T104 of voltage transformer T1 is connected with the other end of resistance R 6, an end of resistance R 12; The other end of resistance R 2 is connected with an end of capacitor C 1, an end of resistance R 13, the tenth tripod U213 of chip U2; The other end of resistance R 12 is connected with an end of capacitor C 4, an end of resistance R 14, the 14 pin U214 of chip U2;
The first output T203 of voltage transformer T2 is connected with an end of resistance R 20, an end of resistance R 21, and the second output T204 of voltage transformer T2 is connected with the other end of resistance R 21, an end of resistance R 23; The other end of resistance R 20 is connected with an end of capacitor C 5, an end of resistance R 15, the 16 pin U216 of chip U2; The other end of resistance R 23 is connected with an end of capacitor C 7, an end of resistance R 16, the 17 pin U217 of chip U2; The first output T303 of voltage transformer T3 is connected with an end of resistance R 27, resistance R 26 1 ends, and the second output T304 of voltage transformer T3 is connected with the other end of resistance R 27, an end of resistance R 30; The other end of resistance R 26 is connected with the 19 pin U219 of chip U2 with an end of capacitor C 10, an end of resistance R 17; The other end of resistance R 30 is connected with an end of capacitor C 13, an end of resistance R 18, the 20 pin U220 of chip U2;
The other end of the other end of the other end of the other end of the other end of the other end of capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10, capacitor C 13 is ground connection respectively;
The other end of the other end of the other end of the other end of the other end of the other end of resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 148 is connected with the 11 pin U211 of chip U2;
One end of capacitor C 2, one end of capacitor C 6, one end of capacitor C 8, one end of capacitor C 9, one end of capacitor C 11, one end of capacitor C 14, one end of capacitor C 15, one end of capacitor C 16, one end of capacitor C 18, the negative electrode of capacitor C 3, the negative electrode of capacitor C 12, the negative electrode of capacitor C 17, the negative electrode of capacitor C 19, the octal U208 of chip U2, the 15 pin U215 of chip U2, the 20 tripod U223 of chip U2, the 24 pin U224 of chip U2, the 44 pin U244 ground connection of chip U2;
The other end of capacitor C 11 is connected with the 12 pin U212, the power supply of chip U2;
The other end of capacitor C 15 is connected with the tenth octal U218, the power supply of chip U2;
The other end of capacitor C 18 is connected with the 30 tripod U233, the power supply of chip U2;
The positive pole of capacitor C 19 is connected with the 30 tripod U233, the power supply of chip U2;
The other end of capacitor C 16 is connected with the 34 pin U234, the power supply of chip U2;
The positive pole of capacitor C 17 is connected with the 34 pin U234, the power supply of chip U2;
The other end of capacitor C 2 is connected with the 6th pin U206 of chip U2;
The positive pole of capacitor C 3 is connected with the 34 pin U234 of chip U2;
The other end of capacitor C 6 is connected with the 40 tripod U243 of chip U2, the end of crystal oscillator Y1;
The other end of capacitor C 8 is connected with the other end of crystal oscillator Y1, the 42 pin U242 of chip U2;
The other end of capacitor C 9 is connected with the other end of power supply, capacitor C 12, the 41 pin U241 of chip U2, the other end of capacitor C 14, the 39 pin U239 of chip U2;
The 39 pin U239, the 41 pin U241 of chip U2 of the 34 pin U234, the chip U2 of the 30 tripod U233, the chip U2 of the tenth octal U218, the chip U2 of the 12 pin U212, the chip U2 of chip U2 are connected with power supply;
The first pin U201 of chip U2 is connected with the 4th pin U104 of chip U1;
The crus secunda U202 of chip U2 is connected with the 5th pin U105 of chip U1;
The 30 octal U238 of chip U2 is connected with the 6th pin U106 of chip U1;
The 37 pin U237 of chip U2 is connected with the 11 pin U111 of chip U1;
The 36 pin U236 of chip U2 is connected with the 12 pin U112 of chip U1;
The 35 pin U235 of chip U2 is connected with the tenth tripod U113 of chip U1;
The 22 pin U122 ground connection of the octal U108 of chip U1, chip U1;
The 20 pin U120 of the 21 pin U121, the chip U1 of the 7th pin U107, the chip U1 of chip U1 is connected with an end of power supply, resistance R 28, and the other end of resistance R 28 is connected with the first pin U101 of chip U1;
One end of relay K 1 is connected with the negative electrode of power supply, diode D4, and the positive pole of diode D4 is connected with the other end of relay K 1, the collector electrode of triode Q1;
Triode Q1 grounded emitter;
The base stage of triode Q1 is connected with the 15 pin U115 of chip U1;
The first pin R101 of exclusion R10 is connected with power supply;
The crus secunda R102 of exclusion R10 is connected with the positive pole of light-emitting diode D1, and the negative pole of light-emitting diode D1 is connected with the 14 pin U114 of chip U1;
The tripod R103 of exclusion R10 is connected with the positive pole of light-emitting diode D2, and the negative pole of light-emitting diode D2 is connected with the 16 pin U116 of chip U1;
The 4th pin R104 of exclusion R10 is connected with the positive pole of light-emitting diode D3, and the negative pole of light-emitting diode D3 is connected with the 17 pin U117 of chip U1.
Wherein, voltage transformer T1, voltage transformer T2 and voltage transformer T3 are the current mode voltage transformer.
Wherein, the model of voltage transformer T1, voltage transformer T2 and voltage transformer T3 is Trans Ideal.
Wherein, the nominal resistance of resistance R 1, resistance R 11, resistance R 19, resistance R 22 and resistance R 25 is divided equally 150k;
The nominal resistance of resistance R 2, resistance R 12, resistance R 20, resistance R 23, resistance R 26 and resistance R 30 is divided equally 1k2;
The nominal resistance of resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17 and resistance R 18 is divided equally 10k.
Wherein, the capacitance of capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10 and capacitor C 13 is 0.01uF;
The capacitance of capacitor C 11, capacitor C 15, capacitor C 18, capacitor C 16, capacitor C 2, capacitor C 14 and capacitor C 9 is 0.1uF;
Capacitor C 3, capacitor C 19, capacitor C 187 and capacitor C 12 are polar capacitor, and capacitance is 10uF;
The capacitance of capacitor C 6 is 20uF.
Wherein, crystal oscillator is the 24.576MHZ crystal oscillator.
Wherein, the model of chip U2 is ATT7022.
Wherein, the model of chip U1 is Atmega8-16PI.
The beneficial effects of the utility model: a kind of misphase of three phase mains and open-phase protection circuit; comprise signaling conversion circuit 100, signal acquisition circuit 200 and signal processing and drive circuit 300; the output of signaling conversion circuit 100 is connected with the input of signal acquisition circuit 200; the output of signal acquisition circuit 200 and signal are processed and the input of drive circuit 300 is connected, and signal processing and drive circuit 300 receive that misphase or default phase signal then send guard signal.Compared with prior art; signaling conversion circuit 100 of the present utility model converts three phase mains to and is fit to the signal that signal acquisition circuit 200 gathers; signal acquisition circuit 200 gathers this signal and issues signal processing and drive circuit 300; signal is processed and drive circuit 300 receives that misphase or default phase signal then send guard signal, has avoided the generation of fault.The utlity model has circuit structure is simple and easy to realize good stability, the characteristics that antijamming capability is strong.
Description of drawings
Utilize accompanying drawing that the utility model is described further, but the content in the accompanying drawing does not consist of any restriction of the present utility model.
Fig. 1 is the misphase of a kind of three phase mains of the present utility model and the structural representation of open-phase protection circuit.
Include among Fig. 1: signaling conversion circuit 100, signal acquisition circuit 200, signal processing and drive circuit 300,
The tripod P103 of crus secunda P102, the binding post P1 of the first pin P101, the binding post P1 of binding post P1, binding post P1,
The 4th pin R104 of tripod R103, the exclusion R10 of crus secunda R102, the exclusion R10 of the first pin R101, the exclusion R10 of resistance R 1, resistance R 2, resistance R 11, resistance R 12, resistance R 19, resistance R 20, resistance R 21, resistance R 22, resistance R 23, resistance R 25, resistance R 26, resistance R 27, resistance R 29, resistance R 30, resistance R 6, resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 18, resistance R 28, exclusion R10, exclusion R10,
Capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10, capacitor C 13, capacitor C 2, capacitor C 3, capacitor C 6, capacitor C 8, capacitor C 9, capacitor C 11, capacitor C 12, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, capacitor C 19,
Crystal oscillator Y1, relay K 1, light-emitting diode D1, light-emitting diode D2, light-emitting diode D3, diode D4, triode Q1,
The second output T104 of the first output T103, the voltage transformer T1 of the second input T102, the voltage transformer T1 of the first input end T101 of voltage transformer T1, voltage transformer T1, voltage transformer T1,
The second output T204 of the first output T203, the voltage transformer T1 of the second input T202, the voltage transformer T1 of the first input end T201 of voltage transformer T2, voltage transformer T1, voltage transformer T1,
The second output T304 of the first output T303, the voltage transformer T1 of the second input T302, the voltage transformer T1 of the first input end T301 of voltage transformer T3, voltage transformer T1, voltage transformer T1,
The first pin U101 of chip U1, the 5th pin U105 of chip U1, the 6th pin U106 of chip U1, the 7th pin U107 of chip U1, the octal U108 of chip U1, the 11 pin U111 of chip U1, the 12 pin U112 of chip U1, the tenth tripod U113 of chip U1, the 14 pin U114 of chip U1, the 15 pin U115 of chip U1, the 16 pin U116 of chip U1, the 17 pin U117 of chip U1, the 20 pin U120 of chip U1, the 11 pin U121 of chip U1, the 22 pin U122 of chip U1;
The first pin U201 of chip U2, the crus secunda U202 of chip U2, the 5th pin U205 of chip U2, the octal U208 of chip U2, the 11 pin U211 of chip U2, the 12 pin U212 of chip U2, the tenth tripod U213 of chip U2, the 14 pin U214 of chip U2, the 15 pin U215 of chip U2, the 16 pin U216 of chip U2, the 17 pin U217 of chip U2, the tenth octal U218 of chip U2, the 19 pin U219 of chip U2, the 20 pin U220 of chip U2, the 20 tripod U223 of chip U2, the 24 pin U224 of chip U2, the 30 tripod U233 of chip U2, the 34 pin U234 of chip U2, the 35 pin U235 of chip U2, the 36 pin U236 of chip U2, the 37 pin U237 of chip U2, the 30 octal U238 of chip U2, the 39 pin U239 of chip U2, the 41 pin U241 of chip U2, the 42 pin U242 of chip U2, the 40 tripod U243 of chip U2, the 44 pin U244 of chip U2.
Embodiment
The utility model is described in further detail with the following Examples.
A kind of misphase of three phase mains and open-phase protection circuit; as shown in Figure 3; comprise signaling conversion circuit 100, signal acquisition circuit 200 and signal processing and drive circuit 300; the output of signaling conversion circuit 100 is connected with the input of signal acquisition circuit 200; the output of signal acquisition circuit 200 and signal are processed and the input of drive circuit 300 is connected, and signal processing and drive circuit 300 receive that misphase or default phase signal then send guard signal.Signaling conversion circuit 100 of the present utility model converts three phase mains to and is fit to the signal that signal acquisition circuit 200 gathers; signal acquisition circuit 200 gathers this signal and issues signal processing and drive circuit 300; signal is processed and drive circuit 300 receives that misphase or default phase signal then send guard signal, has avoided the generation of fault.
Wherein, signaling conversion circuit 100 comprises resistance R 1, resistance R 2, resistance R 11, resistance R 12, resistance R 19, resistance R 20, resistance R 21, resistance R 22, resistance R 23, resistance R 25, resistance R 26, resistance R 27, resistance R 29, resistance R 30, resistance R 6, voltage transformer T1, voltage transformer T2, voltage transformer T3, capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10 and capacitor C 13;
Signal acquisition circuit 200 comprises resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 18, capacitor C 2, capacitor C 3, capacitor C 6, capacitor C 8, capacitor C 9, capacitor C 11, capacitor C 12, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, capacitor C 19, chip U2 and crystal oscillator Y1;
Signal is processed and drive circuit 300 comprises resistance R 28, exclusion R10, chip U1, light-emitting diode D1, light-emitting diode D2, light-emitting diode D3, diode D4, triode Q1 and relay K 1;
The first pin P101 of binding post P1 is connected with an end of resistance R 22, an end of resistance R 25, and the other end of resistance R 22 is connected with the first input end T201 of voltage transformer T2, and the other end of resistance R 25 is connected with the first input end T301 of voltage transformer T3;
One end of the crus secunda P102 of binding post P1 and an end of resistance R 11, resistance R 19, the first input end T101 of the other end of resistance R 11 and voltage transformer T1, the other end of resistance R 19 is connected with the second input T202 of voltage transformer T2;
One end of the tripod P103 of binding post P1 and an end of resistance R 1, resistance R 29, the second input T102 of the other end of resistance R 1 and voltage transformer T1, the other end of resistance R 29 is connected with the second input T302 of voltage transformer T3; The first output T103 of voltage transformer T1 is connected with an end of resistance R 6, an end of resistance R 2, and the second output T104 of voltage transformer T1 is connected with the other end of resistance R 6, an end of resistance R 12; The other end of resistance R 2 is connected with an end of capacitor C 1, an end of resistance R 13, the tenth tripod U213 of chip U2; The other end of resistance R 12 is connected with an end of capacitor C 4, an end of resistance R 14, the 14 pin U214 of chip U2;
The first output T203 of voltage transformer T2 is connected with an end of resistance R 20, an end of resistance R 21, and the second output T204 of voltage transformer T2 is connected with the other end of resistance R 21, an end of resistance R 23; The other end of resistance R 20 is connected with an end of capacitor C 5, an end of resistance R 15, the 16 pin U216 of chip U2; The other end of resistance R 23 is connected with an end of capacitor C 7, an end of resistance R 16, the 17 pin U217 of chip U2;
The first output T303 of voltage transformer T3 is connected with an end of resistance R 27, resistance R 26 1 ends, and the second output T304 of voltage transformer T3 is connected with the other end of resistance R 27, an end of resistance R 30; The other end of resistance R 26 is connected with the 19 pin U219 of chip U2 with an end of capacitor C 10, an end of resistance R 17; The other end of resistance R 30 is connected with an end of capacitor C 13, an end of resistance R 18, the 20 pin U220 of chip U2;
The other end of the other end of the other end of the other end of the other end of the other end of capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10, capacitor C 13 is ground connection respectively;
The other end of the other end of the other end of the other end of the other end of the other end of resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 148 is connected with the 11 pin U211 of chip U2;
One end of capacitor C 2, one end of capacitor C 6, one end of capacitor C 8, one end of capacitor C 9, one end of capacitor C 11, one end of capacitor C 14, one end of capacitor C 15, one end of capacitor C 16, one end of capacitor C 18, the negative electrode of capacitor C 3, the negative electrode of capacitor C 12, the negative electrode of capacitor C 17, the negative electrode of capacitor C 19, the octal U208 of chip U2, the 15 pin U215 of chip U2, the 20 tripod U223 of chip U2, the 24 pin U224 of chip U2, the 44 pin U244 ground connection of chip U2;
The other end of capacitor C 11 is connected with the 12 pin U212, the power supply of chip U2;
The other end of capacitor C 15 is connected with the tenth octal U218, the power supply of chip U2;
The other end of capacitor C 18 is connected with the 30 tripod U233, the power supply of chip U2;
The positive pole of capacitor C 19 is connected with the 30 tripod U233, the power supply of chip U2;
The other end of capacitor C 16 is connected with the 34 pin U234, the power supply of chip U2;
The positive pole of capacitor C 17 is connected with the 34 pin U234, the power supply of chip U2;
The other end of capacitor C 2 is connected with the 6th pin U206 of chip U2;
The positive pole of capacitor C 3 is connected with the 34 pin U234 of chip U2;
The other end of capacitor C 6 is connected with the 40 tripod U243 of chip U2, the end of crystal oscillator Y1;
The other end of capacitor C 8 is connected with the other end of crystal oscillator Y1, the 42 pin U242 of chip U2;
The other end of capacitor C 9 is connected with the other end of power supply, capacitor C 12, the 41 pin U241 of chip U2, the other end of capacitor C 14, the 39 pin U239 of chip U2;
The 39 pin U239, the 41 pin U241 of chip U2 of the 34 pin U234, the chip U2 of the 30 tripod U233, the chip U2 of the tenth octal U218, the chip U2 of the 12 pin U212, the chip U2 of chip U2 are connected with power supply;
The first pin U201 of chip U2 is connected with the 4th pin U104 of chip U1;
The crus secunda U202 of chip U2 is connected with the 5th pin U105 of chip U1;
The 30 octal U238 of chip U2 is connected with the 6th pin U106 of chip U1;
The 37 pin U237 of chip U2 is connected with the 11 pin U111 of chip U1;
The 36 pin U236 of chip U2 is connected with the 12 pin U112 of chip U1;
The 35 pin U235 of chip U2 is connected with the tenth tripod U113 of chip U1;
The 22 pin U122 ground connection of the octal U108 of chip U1, chip U1;
The 20 pin U120 of the 21 pin U121, the chip U1 of the 7th pin U107, the chip U1 of chip U1 is connected with an end of power supply, resistance R 28, and the other end of resistance R 28 is connected with the first pin U101 of chip U1;
One end of relay K 1 is connected with the negative electrode of power supply, diode D4, and the positive pole of diode D4 is connected with the other end of relay K 1, the collector electrode of triode Q1;
Triode Q1 grounded emitter;
The base stage of triode Q1 is connected with the 15 pin U115 of chip U1;
The first pin R101 of exclusion R10 is connected with power supply;
The crus secunda R102 of exclusion R10 is connected with the positive pole of light-emitting diode D1, and the negative pole of light-emitting diode D1 is connected with the 14 pin U114 of chip U1;
The tripod R103 of exclusion R10 is connected with the positive pole of light-emitting diode D2, and the negative pole of light-emitting diode D2 is connected with the 16 pin U116 of chip U1;
The 4th pin R104 of exclusion R10 is connected with the positive pole of light-emitting diode D3, and the negative pole of light-emitting diode D3 is connected with the 17 pin U117 of chip U1.
The voltage transformer T1 of the present embodiment, voltage transformer T2 and voltage transformer T3 are the current mode voltage transformer.
The nominal resistance of the resistance R 1 of the present embodiment, resistance R 11, resistance R 19, resistance R 22 and resistance R 25 is divided equally 150k; The nominal resistance of resistance R 2, resistance R 12, resistance R 20, resistance R 23, resistance R 26 and resistance R 30 is divided equally 1k2; The nominal resistance of resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17 and resistance R 18 is divided equally 10k.
In the present embodiment, the capacitance of capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10 and capacitor C 13 is 0.01uF; The capacitance of capacitor C 11, capacitor C 15, capacitor C 18, capacitor C 16, capacitor C 2, capacitor C 14 and capacitor C 9 is 0.1uF; Capacitor C 3, capacitor C 19, capacitor C 187 and capacitor C 12 are polar capacitor, and capacitance is 10uF; The capacitance of capacitor C 6 is 20uF.
The crystal oscillator of the present embodiment is the 24.576MHZ crystal oscillator, and the model of chip U2 is ATT7022, and the model of chip U1 is Atmega8-16PI, and the model of voltage transformer T1, voltage transformer T2 and voltage transformer T3 is Trans Ideal.
Signaling conversion circuit 100 of the present utility model is to adopt electromagnetic principle the high pressure three phase mains to be converted to the three phase mains of low pressure, send in the signal acquisition circuit 200 through behind the capacitor filtering, signal acquisition circuit 200 utilizes analog-to-digital conversion mechanism to convert the three-phase simulation signal of low pressure to be beneficial to the chip processing digital signal, signal is processed and drive circuit 300 therefrom reads its signal, judges its misphase, phase shortage based on the principle features of three-phase electricity.If misphase, open phase relay action occur, send guard signal, avoided the generation of fault.The utlity model has circuit structure is simple and easy to realize good stability, the characteristics that antijamming capability is strong.
Should be noted that at last; above embodiment only is used for the explanation the technical solution of the utility model but not to the restriction of the utility model protection range; although with reference to preferred embodiment the utility model has been done detailed description; those of ordinary skill in the art is to be understood that; can make amendment or be equal to replacement the technical solution of the utility model, and not break away from essence and the scope of technical solutions of the utility model.
Claims (9)
1. the misphase of a three phase mains and open-phase protection circuit; it is characterized in that: comprise signaling conversion circuit 100, signal acquisition circuit 200 and signal processing and drive circuit 300; the output of described signaling conversion circuit 100 is connected with the input of described signal acquisition circuit 200; the output of described signal acquisition circuit 200 processes with described signal and the input of drive circuit 300 is connected, and signal processing and drive circuit 300 receive that misphase or default phase signal then send guard signal.
2. the misphase of a kind of three phase mains according to claim 1 and open-phase protection circuit is characterized in that:
Described signaling conversion circuit 100 comprises resistance R 1, resistance R 2, resistance R 11, resistance R 12, resistance R 19, resistance R 20, resistance R 21, resistance R 22, resistance R 23, resistance R 25, resistance R 26, resistance R 27, resistance R 29, resistance R 30, resistance R 6, voltage transformer T1, voltage transformer T2, voltage transformer T3, capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10 and capacitor C 13;
Described signal acquisition circuit 200 comprises resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 18, capacitor C 2, capacitor C 3, capacitor C 6, capacitor C 8, capacitor C 9, capacitor C 11, capacitor C 12, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, capacitor C 19, chip U2 and crystal oscillator Y1;
Described signal is processed and drive circuit 300 comprises resistance R 28, exclusion R10, chip U1, light-emitting diode D1, light-emitting diode D2, light-emitting diode D3, diode D4, triode Q1 and relay K 1;
The first pin P101 of binding post P1 is connected with an end of resistance R 22, an end of resistance R 25, and the other end of resistance R 22 is connected with the first input end T201 of voltage transformer T2, and the other end of resistance R 25 is connected with the first input end T301 of voltage transformer T3;
One end of the crus secunda P102 of binding post P1 and an end of resistance R 11, resistance R 19, the first input end T101 of the other end of resistance R 11 and voltage transformer T1, the other end of resistance R 19 is connected with the second input T202 of voltage transformer T2;
One end of the tripod P103 of binding post P1 and an end of resistance R 1, resistance R 29, the second input T102 of the other end of resistance R 1 and voltage transformer T1, the other end of resistance R 29 is connected with the second input T302 of voltage transformer T3;
The first output T103 of voltage transformer T1 is connected with an end of resistance R 6, an end of resistance R 2, and the second output T104 of voltage transformer T1 is connected with the other end of resistance R 6, an end of resistance R 12; The other end of resistance R 2 is connected with an end of capacitor C 1, an end of resistance R 13, the tenth tripod U213 of chip U2; The other end of resistance R 12 is connected with an end of capacitor C 4, an end of resistance R 14, the 14 pin U214 of chip U2;
The first output T203 of voltage transformer T2 is connected with an end of resistance R 20, an end of resistance R 21, and the second output T204 of voltage transformer T2 is connected with the other end of resistance R 21, an end of resistance R 23; The other end of resistance R 20 is connected with an end of capacitor C 5, an end of resistance R 15, the 16 pin U216 of chip U2; The other end of resistance R 23 is connected with an end of capacitor C 7, an end of resistance R 16, the 17 pin U217 of chip U2;
The first output T303 of voltage transformer T3 is connected with an end of resistance R 27, resistance R 26 1 ends, and the second output T304 of voltage transformer T3 is connected with the other end of resistance R 27, an end of resistance R 30; The other end of resistance R 26 is connected with the 19 pin U219 of chip U2 with an end of capacitor C 10, an end of resistance R 17; The other end of resistance R 30 is connected with an end of capacitor C 13, an end of resistance R 18, the 20 pin U220 of chip U2;
The other end of the other end of the other end of the other end of the other end of the other end of capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10, capacitor C 13 is ground connection respectively;
The other end of the other end of the other end of the other end of the other end of the other end of resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 148 is connected with the 11 pin U211 of chip U2;
One end of capacitor C 2, one end of capacitor C 6, one end of capacitor C 8, one end of capacitor C 9, one end of capacitor C 11, one end of capacitor C 14, one end of capacitor C 15, one end of capacitor C 16, one end of capacitor C 18, the negative electrode of capacitor C 3, the negative electrode of capacitor C 12, the negative electrode of capacitor C 17, the negative electrode of capacitor C 19, the octal U208 of chip U2, the 15 pin U215 of chip U2, the 20 tripod U223 of chip U2, the 24 pin U224 of chip U2, the 44 pin U244 ground connection of chip U2;
The other end of capacitor C 11 is connected with the 12 pin U212, the power supply of chip U2;
The other end of capacitor C 15 is connected with the tenth octal U218, the power supply of chip U2;
The other end of capacitor C 18 is connected with the 30 tripod U233, the power supply of chip U2;
The positive pole of capacitor C 19 is connected with the 30 tripod U233, the power supply of chip U2;
The other end of capacitor C 16 is connected with the 34 pin U234, the power supply of chip U2;
The positive pole of capacitor C 17 is connected with the 34 pin U234, the power supply of chip U2;
The other end of capacitor C 2 is connected with the 6th pin U206 of chip U2;
The positive pole of capacitor C 3 is connected with the 34 pin U234 of chip U2;
The other end of capacitor C 6 is connected with the 40 tripod U243 of chip U2, the end of crystal oscillator Y1;
The other end of capacitor C 8 is connected with the other end of crystal oscillator Y1, the 42 pin U242 of chip U2;
The other end of capacitor C 9 is connected with the other end of power supply, capacitor C 12, the 41 pin U241 of chip U2, the other end of capacitor C 14, the 39 pin U239 of chip U2;
The 39 pin U239, the 41 pin U241 of chip U2 of the 34 pin U234, the chip U2 of the 30 tripod U233, the chip U2 of the tenth octal U218, the chip U2 of the 12 pin U212, the chip U2 of chip U2 are connected with power supply;
The first pin U201 of chip U2 is connected with the 4th pin U104 of chip U1;
The crus secunda U202 of chip U2 is connected with the 5th pin U105 of chip U1;
The 30 octal U238 of chip U2 is connected with the 6th pin U106 of chip U1;
The 37 pin U237 of chip U2 is connected with the 11 pin U111 of chip U1;
The 36 pin U236 of chip U2 is connected with the 12 pin U112 of chip U1;
The 35 pin U235 of chip U2 is connected with the tenth tripod U113 of chip U1;
The 22 pin U122 ground connection of the octal U108 of chip U1, chip U1;
The 20 pin U120 of the 21 pin U121, the chip U1 of the 7th pin U107, the chip U1 of chip U1 is connected with an end of power supply, resistance R 28, and the other end of resistance R 28 is connected with the first pin U101 of chip U1
One end of relay K 1 is connected with the negative electrode of power supply, diode D4, and the positive pole of diode D4 is connected with the other end of relay K 1, the collector electrode of triode Q1;
Triode Q1 grounded emitter;
The base stage of triode Q1 is connected with the 15 pin U115 of chip U1;
The first pin R101 of exclusion R10 is connected with power supply;
The crus secunda R102 of exclusion R10 is connected with the positive pole of light-emitting diode D1, and the negative pole of light-emitting diode D1 is connected with the 14 pin U114 of chip U1;
The tripod R103 of exclusion R10 is connected with the positive pole of light-emitting diode D2, and the negative pole of light-emitting diode D2 is connected with the 16 pin U116 of chip U1;
The 4th pin R104 of exclusion R10 is connected with the positive pole of light-emitting diode D3, and the negative pole of light-emitting diode D3 is connected with the 17 pin U117 of chip U1.
3. the misphase of a kind of three phase mains according to claim 2 and open-phase protection circuit, it is characterized in that: described voltage transformer T1, voltage transformer T2 and voltage transformer T3 are the current mode voltage transformer.
4. the misphase of a kind of three phase mains according to claim 3 and open-phase protection circuit, it is characterized in that: the model of described voltage transformer T1, voltage transformer T2 and voltage transformer T3 is Trans Ideal.
5. the misphase of a kind of three phase mains according to claim 2 and open-phase protection circuit, it is characterized in that: the nominal resistance of resistance R 1, resistance R 11, resistance R 19, resistance R 22 and resistance R 25 is divided equally 150k;
The nominal resistance of resistance R 2, resistance R 12, resistance R 20, resistance R 23, resistance R 26 and resistance R 30 is divided equally 1k2;
The nominal resistance of resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 17 and resistance R 18 is divided equally 10k.
6. the misphase of a kind of three phase mains according to claim 2 and open-phase protection circuit, it is characterized in that: the capacitance of capacitor C 1, capacitor C 4, capacitor C 5, capacitor C 7, capacitor C 10 and capacitor C 13 is 0.01uF;
The capacitance of capacitor C 11, capacitor C 15, capacitor C 18, capacitor C 16, capacitor C 2, capacitor C 14 and capacitor C 9 is 0.1uF;
Capacitor C 3, capacitor C 19, capacitor C 187 and capacitor C 12 are polar capacitor, and capacitance is 10uF;
The capacitance of capacitor C 6 is 20uF.
7. the misphase of a kind of three phase mains according to claim 2 and open-phase protection circuit, it is characterized in that: described crystal oscillator is the 24.576MHZ crystal oscillator.
8. the misphase of a kind of three phase mains according to claim 2 and open-phase protection circuit, it is characterized in that: the model of described chip U2 is ATT7022.
9. the misphase of a kind of three phase mains according to claim 2 and open-phase protection circuit, it is characterized in that: the model of described chip U1 is Atmega8-16PI.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220444149 CN202840486U (en) | 2012-09-03 | 2012-09-03 | Phase loss and phase dislocation detecting circuit of three-phase power source |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220444149 CN202840486U (en) | 2012-09-03 | 2012-09-03 | Phase loss and phase dislocation detecting circuit of three-phase power source |
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| Publication Number | Publication Date |
|---|---|
| CN202840486U true CN202840486U (en) | 2013-03-27 |
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| CN 201220444149 Expired - Fee Related CN202840486U (en) | 2012-09-03 | 2012-09-03 | Phase loss and phase dislocation detecting circuit of three-phase power source |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107786311A (en) * | 2016-08-26 | 2018-03-09 | 成都芯瑞科技股份有限公司 | Device for detecting code error |
-
2012
- 2012-09-03 CN CN 201220444149 patent/CN202840486U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107786311A (en) * | 2016-08-26 | 2018-03-09 | 成都芯瑞科技股份有限公司 | Device for detecting code error |
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